gus_dma.c 7.0 KB

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  1. /*
  2. * Routines for GF1 DMA control
  3. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  4. *
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19. *
  20. */
  21. #include <sound/driver.h>
  22. #include <asm/dma.h>
  23. #include <linux/slab.h>
  24. #include <sound/core.h>
  25. #include <sound/gus.h>
  26. static void snd_gf1_dma_ack(struct snd_gus_card * gus)
  27. {
  28. unsigned long flags;
  29. spin_lock_irqsave(&gus->reg_lock, flags);
  30. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, 0x00);
  31. snd_gf1_look8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL);
  32. spin_unlock_irqrestore(&gus->reg_lock, flags);
  33. }
  34. static void snd_gf1_dma_program(struct snd_gus_card * gus,
  35. unsigned int addr,
  36. unsigned long buf_addr,
  37. unsigned int count,
  38. unsigned int cmd)
  39. {
  40. unsigned long flags;
  41. unsigned int address;
  42. unsigned char dma_cmd;
  43. unsigned int address_high;
  44. // snd_printk("dma_transfer: addr=0x%x, buf=0x%lx, count=0x%x\n", addr, (long) buf, count);
  45. if (gus->gf1.dma1 > 3) {
  46. if (gus->gf1.enh_mode) {
  47. address = addr >> 1;
  48. } else {
  49. if (addr & 0x1f) {
  50. snd_printd("snd_gf1_dma_transfer: unaligned address (0x%x)?\n", addr);
  51. return;
  52. }
  53. address = (addr & 0x000c0000) | ((addr & 0x0003ffff) >> 1);
  54. }
  55. } else {
  56. address = addr;
  57. }
  58. dma_cmd = SNDRV_GF1_DMA_ENABLE | (unsigned short) cmd;
  59. #if 0
  60. dma_cmd |= 0x08;
  61. #endif
  62. if (dma_cmd & SNDRV_GF1_DMA_16BIT) {
  63. count++;
  64. count &= ~1; /* align */
  65. }
  66. if (gus->gf1.dma1 > 3) {
  67. dma_cmd |= SNDRV_GF1_DMA_WIDTH16;
  68. count++;
  69. count &= ~1; /* align */
  70. }
  71. snd_gf1_dma_ack(gus);
  72. snd_dma_program(gus->gf1.dma1, buf_addr, count, dma_cmd & SNDRV_GF1_DMA_READ ? DMA_MODE_READ : DMA_MODE_WRITE);
  73. #if 0
  74. snd_printk("address = 0x%x, count = 0x%x, dma_cmd = 0x%x\n", address << 1, count, dma_cmd);
  75. #endif
  76. spin_lock_irqsave(&gus->reg_lock, flags);
  77. if (gus->gf1.enh_mode) {
  78. address_high = ((address >> 16) & 0x000000f0) | (address & 0x0000000f);
  79. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  80. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_HIGH, (unsigned char) address_high);
  81. } else
  82. snd_gf1_write16(gus, SNDRV_GF1_GW_DRAM_DMA_LOW, (unsigned short) (address >> 4));
  83. snd_gf1_write8(gus, SNDRV_GF1_GB_DRAM_DMA_CONTROL, dma_cmd);
  84. spin_unlock_irqrestore(&gus->reg_lock, flags);
  85. }
  86. static struct snd_gf1_dma_block *snd_gf1_dma_next_block(struct snd_gus_card * gus)
  87. {
  88. struct snd_gf1_dma_block *block;
  89. /* PCM block have bigger priority than synthesizer one */
  90. if (gus->gf1.dma_data_pcm) {
  91. block = gus->gf1.dma_data_pcm;
  92. if (gus->gf1.dma_data_pcm_last == block) {
  93. gus->gf1.dma_data_pcm =
  94. gus->gf1.dma_data_pcm_last = NULL;
  95. } else {
  96. gus->gf1.dma_data_pcm = block->next;
  97. }
  98. } else if (gus->gf1.dma_data_synth) {
  99. block = gus->gf1.dma_data_synth;
  100. if (gus->gf1.dma_data_synth_last == block) {
  101. gus->gf1.dma_data_synth =
  102. gus->gf1.dma_data_synth_last = NULL;
  103. } else {
  104. gus->gf1.dma_data_synth = block->next;
  105. }
  106. } else {
  107. block = NULL;
  108. }
  109. if (block) {
  110. gus->gf1.dma_ack = block->ack;
  111. gus->gf1.dma_private_data = block->private_data;
  112. }
  113. return block;
  114. }
  115. static void snd_gf1_dma_interrupt(struct snd_gus_card * gus)
  116. {
  117. struct snd_gf1_dma_block *block;
  118. snd_gf1_dma_ack(gus);
  119. if (gus->gf1.dma_ack)
  120. gus->gf1.dma_ack(gus, gus->gf1.dma_private_data);
  121. spin_lock(&gus->dma_lock);
  122. if (gus->gf1.dma_data_pcm == NULL &&
  123. gus->gf1.dma_data_synth == NULL) {
  124. gus->gf1.dma_ack = NULL;
  125. gus->gf1.dma_flags &= ~SNDRV_GF1_DMA_TRIGGER;
  126. spin_unlock(&gus->dma_lock);
  127. return;
  128. }
  129. block = snd_gf1_dma_next_block(gus);
  130. spin_unlock(&gus->dma_lock);
  131. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  132. kfree(block);
  133. #if 0
  134. printk("program dma (IRQ) - addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n", addr, (long) buffer, count, cmd);
  135. #endif
  136. }
  137. int snd_gf1_dma_init(struct snd_gus_card * gus)
  138. {
  139. mutex_lock(&gus->dma_mutex);
  140. gus->gf1.dma_shared++;
  141. if (gus->gf1.dma_shared > 1) {
  142. mutex_unlock(&gus->dma_mutex);
  143. return 0;
  144. }
  145. gus->gf1.interrupt_handler_dma_write = snd_gf1_dma_interrupt;
  146. gus->gf1.dma_data_pcm =
  147. gus->gf1.dma_data_pcm_last =
  148. gus->gf1.dma_data_synth =
  149. gus->gf1.dma_data_synth_last = NULL;
  150. mutex_unlock(&gus->dma_mutex);
  151. return 0;
  152. }
  153. int snd_gf1_dma_done(struct snd_gus_card * gus)
  154. {
  155. struct snd_gf1_dma_block *block;
  156. mutex_lock(&gus->dma_mutex);
  157. gus->gf1.dma_shared--;
  158. if (!gus->gf1.dma_shared) {
  159. snd_dma_disable(gus->gf1.dma1);
  160. snd_gf1_set_default_handlers(gus, SNDRV_GF1_HANDLER_DMA_WRITE);
  161. snd_gf1_dma_ack(gus);
  162. while ((block = gus->gf1.dma_data_pcm)) {
  163. gus->gf1.dma_data_pcm = block->next;
  164. kfree(block);
  165. }
  166. while ((block = gus->gf1.dma_data_synth)) {
  167. gus->gf1.dma_data_synth = block->next;
  168. kfree(block);
  169. }
  170. gus->gf1.dma_data_pcm_last =
  171. gus->gf1.dma_data_synth_last = NULL;
  172. }
  173. mutex_unlock(&gus->dma_mutex);
  174. return 0;
  175. }
  176. int snd_gf1_dma_transfer_block(struct snd_gus_card * gus,
  177. struct snd_gf1_dma_block * __block,
  178. int atomic,
  179. int synth)
  180. {
  181. unsigned long flags;
  182. struct snd_gf1_dma_block *block;
  183. block = kmalloc(sizeof(*block), atomic ? GFP_ATOMIC : GFP_KERNEL);
  184. if (block == NULL) {
  185. snd_printk(KERN_ERR "gf1: DMA transfer failure; not enough memory\n");
  186. return -ENOMEM;
  187. }
  188. *block = *__block;
  189. block->next = NULL;
  190. #if 0
  191. printk("addr = 0x%x, buffer = 0x%lx, count = 0x%x, cmd = 0x%x\n", block->addr, (long) block->buffer, block->count, block->cmd);
  192. #endif
  193. #if 0
  194. printk("gus->gf1.dma_data_pcm_last = 0x%lx\n", (long)gus->gf1.dma_data_pcm_last);
  195. printk("gus->gf1.dma_data_pcm = 0x%lx\n", (long)gus->gf1.dma_data_pcm);
  196. #endif
  197. spin_lock_irqsave(&gus->dma_lock, flags);
  198. if (synth) {
  199. if (gus->gf1.dma_data_synth_last) {
  200. gus->gf1.dma_data_synth_last->next = block;
  201. gus->gf1.dma_data_synth_last = block;
  202. } else {
  203. gus->gf1.dma_data_synth =
  204. gus->gf1.dma_data_synth_last = block;
  205. }
  206. } else {
  207. if (gus->gf1.dma_data_pcm_last) {
  208. gus->gf1.dma_data_pcm_last->next = block;
  209. gus->gf1.dma_data_pcm_last = block;
  210. } else {
  211. gus->gf1.dma_data_pcm =
  212. gus->gf1.dma_data_pcm_last = block;
  213. }
  214. }
  215. if (!(gus->gf1.dma_flags & SNDRV_GF1_DMA_TRIGGER)) {
  216. gus->gf1.dma_flags |= SNDRV_GF1_DMA_TRIGGER;
  217. block = snd_gf1_dma_next_block(gus);
  218. spin_unlock_irqrestore(&gus->dma_lock, flags);
  219. if (block == NULL)
  220. return 0;
  221. snd_gf1_dma_program(gus, block->addr, block->buf_addr, block->count, (unsigned short) block->cmd);
  222. kfree(block);
  223. return 0;
  224. }
  225. spin_unlock_irqrestore(&gus->dma_lock, flags);
  226. return 0;
  227. }