pxa2xx-ac97.c 10 KB

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  1. /*
  2. * linux/sound/pxa2xx-ac97.c -- AC97 support for the Intel PXA2xx chip.
  3. *
  4. * Author: Nicolas Pitre
  5. * Created: Dec 02, 2004
  6. * Copyright: MontaVista Software Inc.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/init.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/wait.h>
  18. #include <linux/delay.h>
  19. #include <sound/driver.h>
  20. #include <sound/core.h>
  21. #include <sound/pcm.h>
  22. #include <sound/ac97_codec.h>
  23. #include <sound/initval.h>
  24. #include <asm/irq.h>
  25. #include <linux/mutex.h>
  26. #include <asm/hardware.h>
  27. #include <asm/arch/pxa-regs.h>
  28. #include <asm/arch/audio.h>
  29. #include "pxa2xx-pcm.h"
  30. static DEFINE_MUTEX(car_mutex);
  31. static DECLARE_WAIT_QUEUE_HEAD(gsr_wq);
  32. static volatile long gsr_bits;
  33. /*
  34. * Beware PXA27x bugs:
  35. *
  36. * o Slot 12 read from modem space will hang controller.
  37. * o CDONE, SDONE interrupt fails after any slot 12 IO.
  38. *
  39. * We therefore have an hybrid approach for waiting on SDONE (interrupt or
  40. * 1 jiffy timeout if interrupt never comes).
  41. */
  42. static unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  43. {
  44. unsigned short val = -1;
  45. volatile u32 *reg_addr;
  46. mutex_lock(&car_mutex);
  47. /* set up primary or secondary codec space */
  48. reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
  49. reg_addr += (reg >> 1);
  50. /* start read access across the ac97 link */
  51. GSR = GSR_CDONE | GSR_SDONE;
  52. gsr_bits = 0;
  53. val = *reg_addr;
  54. if (reg == AC97_GPIO_STATUS)
  55. goto out;
  56. if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1) <= 0 &&
  57. !((GSR | gsr_bits) & GSR_SDONE)) {
  58. printk(KERN_ERR "%s: read error (ac97_reg=%d GSR=%#lx)\n",
  59. __FUNCTION__, reg, GSR | gsr_bits);
  60. val = -1;
  61. goto out;
  62. }
  63. /* valid data now */
  64. GSR = GSR_CDONE | GSR_SDONE;
  65. gsr_bits = 0;
  66. val = *reg_addr;
  67. /* but we've just started another cycle... */
  68. wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_SDONE, 1);
  69. out: mutex_unlock(&car_mutex);
  70. return val;
  71. }
  72. static void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
  73. {
  74. volatile u32 *reg_addr;
  75. mutex_lock(&car_mutex);
  76. /* set up primary or secondary codec space */
  77. reg_addr = (ac97->num & 1) ? &SAC_REG_BASE : &PAC_REG_BASE;
  78. reg_addr += (reg >> 1);
  79. GSR = GSR_CDONE | GSR_SDONE;
  80. gsr_bits = 0;
  81. *reg_addr = val;
  82. if (wait_event_timeout(gsr_wq, (GSR | gsr_bits) & GSR_CDONE, 1) <= 0 &&
  83. !((GSR | gsr_bits) & GSR_CDONE))
  84. printk(KERN_ERR "%s: write error (ac97_reg=%d GSR=%#lx)\n",
  85. __FUNCTION__, reg, GSR | gsr_bits);
  86. mutex_unlock(&car_mutex);
  87. }
  88. static void pxa2xx_ac97_reset(struct snd_ac97 *ac97)
  89. {
  90. /* First, try cold reset */
  91. GCR &= GCR_COLD_RST; /* clear everything but nCRST */
  92. GCR &= ~GCR_COLD_RST; /* then assert nCRST */
  93. gsr_bits = 0;
  94. #ifdef CONFIG_PXA27x
  95. /* PXA27x Developers Manual section 13.5.2.2.1 */
  96. pxa_set_cken(1 << 31, 1);
  97. udelay(5);
  98. pxa_set_cken(1 << 31, 0);
  99. GCR = GCR_COLD_RST;
  100. udelay(50);
  101. #else
  102. GCR = GCR_COLD_RST;
  103. GCR |= GCR_CDONE_IE|GCR_SDONE_IE;
  104. wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
  105. #endif
  106. if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR))) {
  107. printk(KERN_INFO "%s: cold reset timeout (GSR=%#lx)\n",
  108. __FUNCTION__, gsr_bits);
  109. /* let's try warm reset */
  110. gsr_bits = 0;
  111. #ifdef CONFIG_PXA27x
  112. /* warm reset broken on Bulverde,
  113. so manually keep AC97 reset high */
  114. pxa_gpio_mode(113 | GPIO_OUT | GPIO_DFLT_HIGH);
  115. udelay(10);
  116. GCR |= GCR_WARM_RST;
  117. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  118. udelay(500);
  119. #else
  120. GCR |= GCR_WARM_RST|GCR_PRIRDY_IEN|GCR_SECRDY_IEN;
  121. wait_event_timeout(gsr_wq, gsr_bits & (GSR_PCR | GSR_SCR), 1);
  122. #endif
  123. if (!((GSR | gsr_bits) & (GSR_PCR | GSR_SCR)))
  124. printk(KERN_INFO "%s: warm reset timeout (GSR=%#lx)\n",
  125. __FUNCTION__, gsr_bits);
  126. }
  127. GCR &= ~(GCR_PRIRDY_IEN|GCR_SECRDY_IEN);
  128. GCR |= GCR_SDONE_IE|GCR_CDONE_IE;
  129. }
  130. static irqreturn_t pxa2xx_ac97_irq(int irq, void *dev_id)
  131. {
  132. long status;
  133. status = GSR;
  134. if (status) {
  135. GSR = status;
  136. gsr_bits |= status;
  137. wake_up(&gsr_wq);
  138. #ifdef CONFIG_PXA27x
  139. /* Although we don't use those we still need to clear them
  140. since they tend to spuriously trigger when MMC is used
  141. (hardware bug? go figure)... */
  142. MISR = MISR_EOC;
  143. PISR = PISR_EOC;
  144. MCSR = MCSR_EOC;
  145. #endif
  146. return IRQ_HANDLED;
  147. }
  148. return IRQ_NONE;
  149. }
  150. static struct snd_ac97_bus_ops pxa2xx_ac97_ops = {
  151. .read = pxa2xx_ac97_read,
  152. .write = pxa2xx_ac97_write,
  153. .reset = pxa2xx_ac97_reset,
  154. };
  155. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_out = {
  156. .name = "AC97 PCM out",
  157. .dev_addr = __PREG(PCDR),
  158. .drcmr = &DRCMRTXPCDR,
  159. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  160. DCMD_BURST32 | DCMD_WIDTH4,
  161. };
  162. static struct pxa2xx_pcm_dma_params pxa2xx_ac97_pcm_in = {
  163. .name = "AC97 PCM in",
  164. .dev_addr = __PREG(PCDR),
  165. .drcmr = &DRCMRRXPCDR,
  166. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  167. DCMD_BURST32 | DCMD_WIDTH4,
  168. };
  169. static struct snd_pcm *pxa2xx_ac97_pcm;
  170. static struct snd_ac97 *pxa2xx_ac97_ac97;
  171. static int pxa2xx_ac97_pcm_startup(struct snd_pcm_substream *substream)
  172. {
  173. struct snd_pcm_runtime *runtime = substream->runtime;
  174. pxa2xx_audio_ops_t *platform_ops;
  175. int r;
  176. runtime->hw.channels_min = 2;
  177. runtime->hw.channels_max = 2;
  178. r = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
  179. AC97_RATES_FRONT_DAC : AC97_RATES_ADC;
  180. runtime->hw.rates = pxa2xx_ac97_ac97->rates[r];
  181. snd_pcm_limit_hw_rates(runtime);
  182. platform_ops = substream->pcm->card->dev->platform_data;
  183. if (platform_ops && platform_ops->startup)
  184. return platform_ops->startup(substream, platform_ops->priv);
  185. else
  186. return 0;
  187. }
  188. static void pxa2xx_ac97_pcm_shutdown(struct snd_pcm_substream *substream)
  189. {
  190. pxa2xx_audio_ops_t *platform_ops;
  191. platform_ops = substream->pcm->card->dev->platform_data;
  192. if (platform_ops && platform_ops->shutdown)
  193. platform_ops->shutdown(substream, platform_ops->priv);
  194. }
  195. static int pxa2xx_ac97_pcm_prepare(struct snd_pcm_substream *substream)
  196. {
  197. struct snd_pcm_runtime *runtime = substream->runtime;
  198. int reg = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
  199. AC97_PCM_FRONT_DAC_RATE : AC97_PCM_LR_ADC_RATE;
  200. return snd_ac97_set_rate(pxa2xx_ac97_ac97, reg, runtime->rate);
  201. }
  202. static struct pxa2xx_pcm_client pxa2xx_ac97_pcm_client = {
  203. .playback_params = &pxa2xx_ac97_pcm_out,
  204. .capture_params = &pxa2xx_ac97_pcm_in,
  205. .startup = pxa2xx_ac97_pcm_startup,
  206. .shutdown = pxa2xx_ac97_pcm_shutdown,
  207. .prepare = pxa2xx_ac97_pcm_prepare,
  208. };
  209. #ifdef CONFIG_PM
  210. static int pxa2xx_ac97_do_suspend(struct snd_card *card, pm_message_t state)
  211. {
  212. pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
  213. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  214. snd_pcm_suspend_all(pxa2xx_ac97_pcm);
  215. snd_ac97_suspend(pxa2xx_ac97_ac97);
  216. if (platform_ops && platform_ops->suspend)
  217. platform_ops->suspend(platform_ops->priv);
  218. GCR |= GCR_ACLINK_OFF;
  219. pxa_set_cken(CKEN2_AC97, 0);
  220. return 0;
  221. }
  222. static int pxa2xx_ac97_do_resume(struct snd_card *card)
  223. {
  224. pxa2xx_audio_ops_t *platform_ops = card->dev->platform_data;
  225. pxa_set_cken(CKEN2_AC97, 1);
  226. if (platform_ops && platform_ops->resume)
  227. platform_ops->resume(platform_ops->priv);
  228. snd_ac97_resume(pxa2xx_ac97_ac97);
  229. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  230. return 0;
  231. }
  232. static int pxa2xx_ac97_suspend(struct platform_device *dev, pm_message_t state)
  233. {
  234. struct snd_card *card = platform_get_drvdata(dev);
  235. int ret = 0;
  236. if (card)
  237. ret = pxa2xx_ac97_do_suspend(card, PMSG_SUSPEND);
  238. return ret;
  239. }
  240. static int pxa2xx_ac97_resume(struct platform_device *dev)
  241. {
  242. struct snd_card *card = platform_get_drvdata(dev);
  243. int ret = 0;
  244. if (card)
  245. ret = pxa2xx_ac97_do_resume(card);
  246. return ret;
  247. }
  248. #else
  249. #define pxa2xx_ac97_suspend NULL
  250. #define pxa2xx_ac97_resume NULL
  251. #endif
  252. static int __devinit pxa2xx_ac97_probe(struct platform_device *dev)
  253. {
  254. struct snd_card *card;
  255. struct snd_ac97_bus *ac97_bus;
  256. struct snd_ac97_template ac97_template;
  257. int ret;
  258. ret = -ENOMEM;
  259. card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  260. THIS_MODULE, 0);
  261. if (!card)
  262. goto err;
  263. card->dev = &dev->dev;
  264. strncpy(card->driver, dev->dev.driver->name, sizeof(card->driver));
  265. ret = pxa2xx_pcm_new(card, &pxa2xx_ac97_pcm_client, &pxa2xx_ac97_pcm);
  266. if (ret)
  267. goto err;
  268. ret = request_irq(IRQ_AC97, pxa2xx_ac97_irq, 0, "AC97", NULL);
  269. if (ret < 0)
  270. goto err;
  271. pxa_gpio_mode(GPIO31_SYNC_AC97_MD);
  272. pxa_gpio_mode(GPIO30_SDATA_OUT_AC97_MD);
  273. pxa_gpio_mode(GPIO28_BITCLK_AC97_MD);
  274. pxa_gpio_mode(GPIO29_SDATA_IN_AC97_MD);
  275. #ifdef CONFIG_PXA27x
  276. /* Use GPIO 113 as AC97 Reset on Bulverde */
  277. pxa_gpio_mode(113 | GPIO_ALT_FN_2_OUT);
  278. #endif
  279. pxa_set_cken(CKEN2_AC97, 1);
  280. ret = snd_ac97_bus(card, 0, &pxa2xx_ac97_ops, NULL, &ac97_bus);
  281. if (ret)
  282. goto err;
  283. memset(&ac97_template, 0, sizeof(ac97_template));
  284. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &pxa2xx_ac97_ac97);
  285. if (ret)
  286. goto err;
  287. snprintf(card->shortname, sizeof(card->shortname),
  288. "%s", snd_ac97_get_short_name(pxa2xx_ac97_ac97));
  289. snprintf(card->longname, sizeof(card->longname),
  290. "%s (%s)", dev->dev.driver->name, card->mixername);
  291. ret = snd_card_register(card);
  292. if (ret == 0) {
  293. platform_set_drvdata(dev, card);
  294. return 0;
  295. }
  296. err:
  297. if (card)
  298. snd_card_free(card);
  299. if (CKEN & CKEN2_AC97) {
  300. GCR |= GCR_ACLINK_OFF;
  301. free_irq(IRQ_AC97, NULL);
  302. pxa_set_cken(CKEN2_AC97, 0);
  303. }
  304. return ret;
  305. }
  306. static int __devexit pxa2xx_ac97_remove(struct platform_device *dev)
  307. {
  308. struct snd_card *card = platform_get_drvdata(dev);
  309. if (card) {
  310. snd_card_free(card);
  311. platform_set_drvdata(dev, NULL);
  312. GCR |= GCR_ACLINK_OFF;
  313. free_irq(IRQ_AC97, NULL);
  314. pxa_set_cken(CKEN2_AC97, 0);
  315. }
  316. return 0;
  317. }
  318. static struct platform_driver pxa2xx_ac97_driver = {
  319. .probe = pxa2xx_ac97_probe,
  320. .remove = __devexit_p(pxa2xx_ac97_remove),
  321. .suspend = pxa2xx_ac97_suspend,
  322. .resume = pxa2xx_ac97_resume,
  323. .driver = {
  324. .name = "pxa2xx-ac97",
  325. },
  326. };
  327. static int __init pxa2xx_ac97_init(void)
  328. {
  329. return platform_driver_register(&pxa2xx_ac97_driver);
  330. }
  331. static void __exit pxa2xx_ac97_exit(void)
  332. {
  333. platform_driver_unregister(&pxa2xx_ac97_driver);
  334. }
  335. module_init(pxa2xx_ac97_init);
  336. module_exit(pxa2xx_ac97_exit);
  337. MODULE_AUTHOR("Nicolas Pitre");
  338. MODULE_DESCRIPTION("AC97 driver for the Intel PXA2xx chip");
  339. MODULE_LICENSE("GPL");