aaci.c 27 KB

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  1. /*
  2. * linux/sound/arm/aaci.c - ARM PrimeCell AACI PL041 driver
  3. *
  4. * Copyright (C) 2003 Deep Blue Solutions Ltd, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * Documentation: ARM DDI 0173B
  11. */
  12. #include <linux/module.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/ioport.h>
  16. #include <linux/device.h>
  17. #include <linux/spinlock.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/err.h>
  20. #include <linux/amba/bus.h>
  21. #include <asm/io.h>
  22. #include <asm/irq.h>
  23. #include <asm/sizes.h>
  24. #include <sound/driver.h>
  25. #include <sound/core.h>
  26. #include <sound/initval.h>
  27. #include <sound/ac97_codec.h>
  28. #include <sound/pcm.h>
  29. #include <sound/pcm_params.h>
  30. #include "aaci.h"
  31. #include "devdma.h"
  32. #define DRIVER_NAME "aaci-pl041"
  33. /*
  34. * PM support is not complete. Turn it off.
  35. */
  36. #undef CONFIG_PM
  37. static void aaci_ac97_select_codec(struct aaci *aaci, struct snd_ac97 *ac97)
  38. {
  39. u32 v, maincr = aaci->maincr | MAINCR_SCRA(ac97->num);
  40. /*
  41. * Ensure that the slot 1/2 RX registers are empty.
  42. */
  43. v = readl(aaci->base + AACI_SLFR);
  44. if (v & SLFR_2RXV)
  45. readl(aaci->base + AACI_SL2RX);
  46. if (v & SLFR_1RXV)
  47. readl(aaci->base + AACI_SL1RX);
  48. writel(maincr, aaci->base + AACI_MAINCR);
  49. }
  50. /*
  51. * P29:
  52. * The recommended use of programming the external codec through slot 1
  53. * and slot 2 data is to use the channels during setup routines and the
  54. * slot register at any other time. The data written into slot 1, slot 2
  55. * and slot 12 registers is transmitted only when their corresponding
  56. * SI1TxEn, SI2TxEn and SI12TxEn bits are set in the AACI_MAINCR
  57. * register.
  58. */
  59. static void aaci_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
  60. unsigned short val)
  61. {
  62. struct aaci *aaci = ac97->private_data;
  63. u32 v;
  64. int timeout = 5000;
  65. if (ac97->num >= 4)
  66. return;
  67. mutex_lock(&aaci->ac97_sem);
  68. aaci_ac97_select_codec(aaci, ac97);
  69. /*
  70. * P54: You must ensure that AACI_SL2TX is always written
  71. * to, if required, before data is written to AACI_SL1TX.
  72. */
  73. writel(val << 4, aaci->base + AACI_SL2TX);
  74. writel(reg << 12, aaci->base + AACI_SL1TX);
  75. /*
  76. * Wait for the transmission of both slots to complete.
  77. */
  78. do {
  79. v = readl(aaci->base + AACI_SLFR);
  80. } while ((v & (SLFR_1TXB|SLFR_2TXB)) && timeout--);
  81. if (!timeout)
  82. dev_err(&aaci->dev->dev,
  83. "timeout waiting for write to complete\n");
  84. mutex_unlock(&aaci->ac97_sem);
  85. }
  86. /*
  87. * Read an AC'97 register.
  88. */
  89. static unsigned short aaci_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
  90. {
  91. struct aaci *aaci = ac97->private_data;
  92. u32 v;
  93. int timeout = 5000;
  94. int retries = 10;
  95. if (ac97->num >= 4)
  96. return ~0;
  97. mutex_lock(&aaci->ac97_sem);
  98. aaci_ac97_select_codec(aaci, ac97);
  99. /*
  100. * Write the register address to slot 1.
  101. */
  102. writel((reg << 12) | (1 << 19), aaci->base + AACI_SL1TX);
  103. /*
  104. * Wait for the transmission to complete.
  105. */
  106. do {
  107. v = readl(aaci->base + AACI_SLFR);
  108. } while ((v & SLFR_1TXB) && timeout--);
  109. if (!timeout) {
  110. dev_err(&aaci->dev->dev, "timeout on slot 1 TX busy\n");
  111. v = ~0;
  112. goto out;
  113. }
  114. /*
  115. * Give the AC'97 codec more than enough time
  116. * to respond. (42us = ~2 frames at 48kHz.)
  117. */
  118. udelay(42);
  119. /*
  120. * Wait for slot 2 to indicate data.
  121. */
  122. timeout = 5000;
  123. do {
  124. cond_resched();
  125. v = readl(aaci->base + AACI_SLFR) & (SLFR_1RXV|SLFR_2RXV);
  126. } while ((v != (SLFR_1RXV|SLFR_2RXV)) && timeout--);
  127. if (!timeout) {
  128. dev_err(&aaci->dev->dev, "timeout on RX valid\n");
  129. v = ~0;
  130. goto out;
  131. }
  132. do {
  133. v = readl(aaci->base + AACI_SL1RX) >> 12;
  134. if (v == reg) {
  135. v = readl(aaci->base + AACI_SL2RX) >> 4;
  136. break;
  137. } else if (--retries) {
  138. dev_warn(&aaci->dev->dev,
  139. "ac97 read back fail. retry\n");
  140. continue;
  141. } else {
  142. dev_warn(&aaci->dev->dev,
  143. "wrong ac97 register read back (%x != %x)\n",
  144. v, reg);
  145. v = ~0;
  146. }
  147. } while (retries);
  148. out:
  149. mutex_unlock(&aaci->ac97_sem);
  150. return v;
  151. }
  152. static inline void aaci_chan_wait_ready(struct aaci_runtime *aacirun)
  153. {
  154. u32 val;
  155. int timeout = 5000;
  156. do {
  157. val = readl(aacirun->base + AACI_SR);
  158. } while (val & (SR_TXB|SR_RXB) && timeout--);
  159. }
  160. /*
  161. * Interrupt support.
  162. */
  163. static void aaci_fifo_irq(struct aaci *aaci, int channel, u32 mask)
  164. {
  165. if (mask & ISR_ORINTR) {
  166. dev_warn(&aaci->dev->dev, "RX overrun on chan %d\n", channel);
  167. writel(ICLR_RXOEC1 << channel, aaci->base + AACI_INTCLR);
  168. }
  169. if (mask & ISR_RXTOINTR) {
  170. dev_warn(&aaci->dev->dev, "RX timeout on chan %d\n", channel);
  171. writel(ICLR_RXTOFEC1 << channel, aaci->base + AACI_INTCLR);
  172. }
  173. if (mask & ISR_RXINTR) {
  174. struct aaci_runtime *aacirun = &aaci->capture;
  175. void *ptr;
  176. if (!aacirun->substream || !aacirun->start) {
  177. dev_warn(&aaci->dev->dev, "RX interrupt???");
  178. writel(0, aacirun->base + AACI_IE);
  179. return;
  180. }
  181. ptr = aacirun->ptr;
  182. do {
  183. unsigned int len = aacirun->fifosz;
  184. u32 val;
  185. if (aacirun->bytes <= 0) {
  186. aacirun->bytes += aacirun->period;
  187. aacirun->ptr = ptr;
  188. spin_unlock(&aaci->lock);
  189. snd_pcm_period_elapsed(aacirun->substream);
  190. spin_lock(&aaci->lock);
  191. }
  192. if (!(aacirun->cr & CR_EN))
  193. break;
  194. val = readl(aacirun->base + AACI_SR);
  195. if (!(val & SR_RXHF))
  196. break;
  197. if (!(val & SR_RXFF))
  198. len >>= 1;
  199. aacirun->bytes -= len;
  200. /* reading 16 bytes at a time */
  201. for( ; len > 0; len -= 16) {
  202. asm(
  203. "ldmia %1, {r0, r1, r2, r3}\n\t"
  204. "stmia %0!, {r0, r1, r2, r3}"
  205. : "+r" (ptr)
  206. : "r" (aacirun->fifo)
  207. : "r0", "r1", "r2", "r3", "cc");
  208. if (ptr >= aacirun->end)
  209. ptr = aacirun->start;
  210. }
  211. } while(1);
  212. aacirun->ptr = ptr;
  213. }
  214. if (mask & ISR_URINTR) {
  215. dev_dbg(&aaci->dev->dev, "TX underrun on chan %d\n", channel);
  216. writel(ICLR_TXUEC1 << channel, aaci->base + AACI_INTCLR);
  217. }
  218. if (mask & ISR_TXINTR) {
  219. struct aaci_runtime *aacirun = &aaci->playback;
  220. void *ptr;
  221. if (!aacirun->substream || !aacirun->start) {
  222. dev_warn(&aaci->dev->dev, "TX interrupt???");
  223. writel(0, aacirun->base + AACI_IE);
  224. return;
  225. }
  226. ptr = aacirun->ptr;
  227. do {
  228. unsigned int len = aacirun->fifosz;
  229. u32 val;
  230. if (aacirun->bytes <= 0) {
  231. aacirun->bytes += aacirun->period;
  232. aacirun->ptr = ptr;
  233. spin_unlock(&aaci->lock);
  234. snd_pcm_period_elapsed(aacirun->substream);
  235. spin_lock(&aaci->lock);
  236. }
  237. if (!(aacirun->cr & CR_EN))
  238. break;
  239. val = readl(aacirun->base + AACI_SR);
  240. if (!(val & SR_TXHE))
  241. break;
  242. if (!(val & SR_TXFE))
  243. len >>= 1;
  244. aacirun->bytes -= len;
  245. /* writing 16 bytes at a time */
  246. for ( ; len > 0; len -= 16) {
  247. asm(
  248. "ldmia %0!, {r0, r1, r2, r3}\n\t"
  249. "stmia %1, {r0, r1, r2, r3}"
  250. : "+r" (ptr)
  251. : "r" (aacirun->fifo)
  252. : "r0", "r1", "r2", "r3", "cc");
  253. if (ptr >= aacirun->end)
  254. ptr = aacirun->start;
  255. }
  256. } while (1);
  257. aacirun->ptr = ptr;
  258. }
  259. }
  260. static irqreturn_t aaci_irq(int irq, void *devid)
  261. {
  262. struct aaci *aaci = devid;
  263. u32 mask;
  264. int i;
  265. spin_lock(&aaci->lock);
  266. mask = readl(aaci->base + AACI_ALLINTS);
  267. if (mask) {
  268. u32 m = mask;
  269. for (i = 0; i < 4; i++, m >>= 7) {
  270. if (m & 0x7f) {
  271. aaci_fifo_irq(aaci, i, m);
  272. }
  273. }
  274. }
  275. spin_unlock(&aaci->lock);
  276. return mask ? IRQ_HANDLED : IRQ_NONE;
  277. }
  278. /*
  279. * ALSA support.
  280. */
  281. struct aaci_stream {
  282. unsigned char codec_idx;
  283. unsigned char rate_idx;
  284. };
  285. static struct aaci_stream aaci_streams[] = {
  286. [ACSTREAM_FRONT] = {
  287. .codec_idx = 0,
  288. .rate_idx = AC97_RATES_FRONT_DAC,
  289. },
  290. [ACSTREAM_SURROUND] = {
  291. .codec_idx = 0,
  292. .rate_idx = AC97_RATES_SURR_DAC,
  293. },
  294. [ACSTREAM_LFE] = {
  295. .codec_idx = 0,
  296. .rate_idx = AC97_RATES_LFE_DAC,
  297. },
  298. };
  299. static inline unsigned int aaci_rate_mask(struct aaci *aaci, int streamid)
  300. {
  301. struct aaci_stream *s = aaci_streams + streamid;
  302. return aaci->ac97_bus->codec[s->codec_idx]->rates[s->rate_idx];
  303. }
  304. static unsigned int rate_list[] = {
  305. 5512, 8000, 11025, 16000, 22050, 32000, 44100,
  306. 48000, 64000, 88200, 96000, 176400, 192000
  307. };
  308. /*
  309. * Double-rate rule: we can support double rate iff channels == 2
  310. * (unimplemented)
  311. */
  312. static int
  313. aaci_rule_rate_by_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  314. {
  315. struct aaci *aaci = rule->private;
  316. unsigned int rate_mask = SNDRV_PCM_RATE_8000_48000|SNDRV_PCM_RATE_5512;
  317. struct snd_interval *c = hw_param_interval(p, SNDRV_PCM_HW_PARAM_CHANNELS);
  318. switch (c->max) {
  319. case 6:
  320. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_LFE);
  321. case 4:
  322. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_SURROUND);
  323. case 2:
  324. rate_mask &= aaci_rate_mask(aaci, ACSTREAM_FRONT);
  325. }
  326. return snd_interval_list(hw_param_interval(p, rule->var),
  327. ARRAY_SIZE(rate_list), rate_list,
  328. rate_mask);
  329. }
  330. static struct snd_pcm_hardware aaci_hw_info = {
  331. .info = SNDRV_PCM_INFO_MMAP |
  332. SNDRV_PCM_INFO_MMAP_VALID |
  333. SNDRV_PCM_INFO_INTERLEAVED |
  334. SNDRV_PCM_INFO_BLOCK_TRANSFER |
  335. SNDRV_PCM_INFO_RESUME,
  336. /*
  337. * ALSA doesn't support 18-bit or 20-bit packed into 32-bit
  338. * words. It also doesn't support 12-bit at all.
  339. */
  340. .formats = SNDRV_PCM_FMTBIT_S16_LE,
  341. /* should this be continuous or knot? */
  342. .rates = SNDRV_PCM_RATE_CONTINUOUS,
  343. .rate_max = 48000,
  344. .rate_min = 4000,
  345. .channels_min = 2,
  346. .channels_max = 6,
  347. .buffer_bytes_max = 64 * 1024,
  348. .period_bytes_min = 256,
  349. .period_bytes_max = PAGE_SIZE,
  350. .periods_min = 4,
  351. .periods_max = PAGE_SIZE / 16,
  352. };
  353. static int __aaci_pcm_open(struct aaci *aaci,
  354. struct snd_pcm_substream *substream,
  355. struct aaci_runtime *aacirun)
  356. {
  357. struct snd_pcm_runtime *runtime = substream->runtime;
  358. int ret;
  359. aacirun->substream = substream;
  360. runtime->private_data = aacirun;
  361. runtime->hw = aaci_hw_info;
  362. /*
  363. * FIXME: ALSA specifies fifo_size in bytes. If we're in normal
  364. * mode, each 32-bit word contains one sample. If we're in
  365. * compact mode, each 32-bit word contains two samples, effectively
  366. * halving the FIFO size. However, we don't know for sure which
  367. * we'll be using at this point. We set this to the lower limit.
  368. */
  369. runtime->hw.fifo_size = aaci->fifosize * 2;
  370. /*
  371. * Add rule describing hardware rate dependency
  372. * on the number of channels.
  373. */
  374. ret = snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
  375. aaci_rule_rate_by_channels, aaci,
  376. SNDRV_PCM_HW_PARAM_CHANNELS,
  377. SNDRV_PCM_HW_PARAM_RATE, -1);
  378. if (ret)
  379. goto out;
  380. ret = request_irq(aaci->dev->irq[0], aaci_irq, IRQF_SHARED|IRQF_DISABLED,
  381. DRIVER_NAME, aaci);
  382. if (ret)
  383. goto out;
  384. return 0;
  385. out:
  386. return ret;
  387. }
  388. /*
  389. * Common ALSA stuff
  390. */
  391. static int aaci_pcm_close(struct snd_pcm_substream *substream)
  392. {
  393. struct aaci *aaci = substream->private_data;
  394. struct aaci_runtime *aacirun = substream->runtime->private_data;
  395. WARN_ON(aacirun->cr & CR_EN);
  396. aacirun->substream = NULL;
  397. free_irq(aaci->dev->irq[0], aaci);
  398. return 0;
  399. }
  400. static int aaci_pcm_hw_free(struct snd_pcm_substream *substream)
  401. {
  402. struct aaci_runtime *aacirun = substream->runtime->private_data;
  403. /*
  404. * This must not be called with the device enabled.
  405. */
  406. WARN_ON(aacirun->cr & CR_EN);
  407. if (aacirun->pcm_open)
  408. snd_ac97_pcm_close(aacirun->pcm);
  409. aacirun->pcm_open = 0;
  410. /*
  411. * Clear out the DMA and any allocated buffers.
  412. */
  413. devdma_hw_free(NULL, substream);
  414. return 0;
  415. }
  416. static int aaci_pcm_hw_params(struct snd_pcm_substream *substream,
  417. struct aaci_runtime *aacirun,
  418. struct snd_pcm_hw_params *params)
  419. {
  420. int err;
  421. aaci_pcm_hw_free(substream);
  422. err = devdma_hw_alloc(NULL, substream,
  423. params_buffer_bytes(params));
  424. if (err < 0)
  425. goto out;
  426. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  427. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  428. params_channels(params),
  429. aacirun->pcm->r[0].slots);
  430. else
  431. err = snd_ac97_pcm_open(aacirun->pcm, params_rate(params),
  432. params_channels(params),
  433. aacirun->pcm->r[1].slots);
  434. if (err)
  435. goto out;
  436. aacirun->pcm_open = 1;
  437. out:
  438. return err;
  439. }
  440. static int aaci_pcm_prepare(struct snd_pcm_substream *substream)
  441. {
  442. struct snd_pcm_runtime *runtime = substream->runtime;
  443. struct aaci_runtime *aacirun = runtime->private_data;
  444. aacirun->start = (void *)runtime->dma_area;
  445. aacirun->end = aacirun->start + runtime->dma_bytes;
  446. aacirun->ptr = aacirun->start;
  447. aacirun->period =
  448. aacirun->bytes = frames_to_bytes(runtime, runtime->period_size);
  449. return 0;
  450. }
  451. static snd_pcm_uframes_t aaci_pcm_pointer(struct snd_pcm_substream *substream)
  452. {
  453. struct snd_pcm_runtime *runtime = substream->runtime;
  454. struct aaci_runtime *aacirun = runtime->private_data;
  455. ssize_t bytes = aacirun->ptr - aacirun->start;
  456. return bytes_to_frames(runtime, bytes);
  457. }
  458. static int aaci_pcm_mmap(struct snd_pcm_substream *substream, struct vm_area_struct *vma)
  459. {
  460. return devdma_mmap(NULL, substream, vma);
  461. }
  462. /*
  463. * Playback specific ALSA stuff
  464. */
  465. static const u32 channels_to_txmask[] = {
  466. [2] = CR_SL3 | CR_SL4,
  467. [4] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8,
  468. [6] = CR_SL3 | CR_SL4 | CR_SL7 | CR_SL8 | CR_SL6 | CR_SL9,
  469. };
  470. /*
  471. * We can support two and four channel audio. Unfortunately
  472. * six channel audio requires a non-standard channel ordering:
  473. * 2 -> FL(3), FR(4)
  474. * 4 -> FL(3), FR(4), SL(7), SR(8)
  475. * 6 -> FL(3), FR(4), SL(7), SR(8), C(6), LFE(9) (required)
  476. * FL(3), FR(4), C(6), SL(7), SR(8), LFE(9) (actual)
  477. * This requires an ALSA configuration file to correct.
  478. */
  479. static unsigned int channel_list[] = { 2, 4, 6 };
  480. static int
  481. aaci_rule_channels(struct snd_pcm_hw_params *p, struct snd_pcm_hw_rule *rule)
  482. {
  483. struct aaci *aaci = rule->private;
  484. unsigned int chan_mask = 1 << 0, slots;
  485. /*
  486. * pcms[0] is the our 5.1 PCM instance.
  487. */
  488. slots = aaci->ac97_bus->pcms[0].r[0].slots;
  489. if (slots & (1 << AC97_SLOT_PCM_SLEFT)) {
  490. chan_mask |= 1 << 1;
  491. if (slots & (1 << AC97_SLOT_LFE))
  492. chan_mask |= 1 << 2;
  493. }
  494. return snd_interval_list(hw_param_interval(p, rule->var),
  495. ARRAY_SIZE(channel_list), channel_list,
  496. chan_mask);
  497. }
  498. static int aaci_pcm_open(struct snd_pcm_substream *substream)
  499. {
  500. struct aaci *aaci = substream->private_data;
  501. int ret;
  502. /*
  503. * Add rule describing channel dependency.
  504. */
  505. ret = snd_pcm_hw_rule_add(substream->runtime, 0,
  506. SNDRV_PCM_HW_PARAM_CHANNELS,
  507. aaci_rule_channels, aaci,
  508. SNDRV_PCM_HW_PARAM_CHANNELS, -1);
  509. if (ret)
  510. return ret;
  511. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  512. ret = __aaci_pcm_open(aaci, substream, &aaci->playback);
  513. } else {
  514. ret = __aaci_pcm_open(aaci, substream, &aaci->capture);
  515. }
  516. return ret;
  517. }
  518. static int aaci_pcm_playback_hw_params(struct snd_pcm_substream *substream,
  519. struct snd_pcm_hw_params *params)
  520. {
  521. struct aaci *aaci = substream->private_data;
  522. struct aaci_runtime *aacirun = substream->runtime->private_data;
  523. unsigned int channels = params_channels(params);
  524. int ret;
  525. WARN_ON(channels >= ARRAY_SIZE(channels_to_txmask) ||
  526. !channels_to_txmask[channels]);
  527. ret = aaci_pcm_hw_params(substream, aacirun, params);
  528. /*
  529. * Enable FIFO, compact mode, 16 bits per sample.
  530. * FIXME: double rate slots?
  531. */
  532. if (ret >= 0) {
  533. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  534. aacirun->cr |= channels_to_txmask[channels];
  535. aacirun->fifosz = aaci->fifosize * 4;
  536. if (aacirun->cr & CR_COMPACT)
  537. aacirun->fifosz >>= 1;
  538. }
  539. return ret;
  540. }
  541. static void aaci_pcm_playback_stop(struct aaci_runtime *aacirun)
  542. {
  543. u32 ie;
  544. ie = readl(aacirun->base + AACI_IE);
  545. ie &= ~(IE_URIE|IE_TXIE);
  546. writel(ie, aacirun->base + AACI_IE);
  547. aacirun->cr &= ~CR_EN;
  548. aaci_chan_wait_ready(aacirun);
  549. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  550. }
  551. static void aaci_pcm_playback_start(struct aaci_runtime *aacirun)
  552. {
  553. u32 ie;
  554. aaci_chan_wait_ready(aacirun);
  555. aacirun->cr |= CR_EN;
  556. ie = readl(aacirun->base + AACI_IE);
  557. ie |= IE_URIE | IE_TXIE;
  558. writel(ie, aacirun->base + AACI_IE);
  559. writel(aacirun->cr, aacirun->base + AACI_TXCR);
  560. }
  561. static int aaci_pcm_playback_trigger(struct snd_pcm_substream *substream, int cmd)
  562. {
  563. struct aaci *aaci = substream->private_data;
  564. struct aaci_runtime *aacirun = substream->runtime->private_data;
  565. unsigned long flags;
  566. int ret = 0;
  567. spin_lock_irqsave(&aaci->lock, flags);
  568. switch (cmd) {
  569. case SNDRV_PCM_TRIGGER_START:
  570. aaci_pcm_playback_start(aacirun);
  571. break;
  572. case SNDRV_PCM_TRIGGER_RESUME:
  573. aaci_pcm_playback_start(aacirun);
  574. break;
  575. case SNDRV_PCM_TRIGGER_STOP:
  576. aaci_pcm_playback_stop(aacirun);
  577. break;
  578. case SNDRV_PCM_TRIGGER_SUSPEND:
  579. aaci_pcm_playback_stop(aacirun);
  580. break;
  581. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  582. break;
  583. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  584. break;
  585. default:
  586. ret = -EINVAL;
  587. }
  588. spin_unlock_irqrestore(&aaci->lock, flags);
  589. return ret;
  590. }
  591. static struct snd_pcm_ops aaci_playback_ops = {
  592. .open = aaci_pcm_open,
  593. .close = aaci_pcm_close,
  594. .ioctl = snd_pcm_lib_ioctl,
  595. .hw_params = aaci_pcm_playback_hw_params,
  596. .hw_free = aaci_pcm_hw_free,
  597. .prepare = aaci_pcm_prepare,
  598. .trigger = aaci_pcm_playback_trigger,
  599. .pointer = aaci_pcm_pointer,
  600. .mmap = aaci_pcm_mmap,
  601. };
  602. static int aaci_pcm_capture_hw_params(struct snd_pcm_substream *substream,
  603. struct snd_pcm_hw_params *params)
  604. {
  605. struct aaci *aaci = substream->private_data;
  606. struct aaci_runtime *aacirun = substream->runtime->private_data;
  607. int ret;
  608. ret = aaci_pcm_hw_params(substream, aacirun, params);
  609. if (ret >= 0) {
  610. aacirun->cr = CR_FEN | CR_COMPACT | CR_SZ16;
  611. /* Line in record: slot 3 and 4 */
  612. aacirun->cr |= CR_SL3 | CR_SL4;
  613. aacirun->fifosz = aaci->fifosize * 4;
  614. if (aacirun->cr & CR_COMPACT)
  615. aacirun->fifosz >>= 1;
  616. }
  617. return ret;
  618. }
  619. static void aaci_pcm_capture_stop(struct aaci_runtime *aacirun)
  620. {
  621. u32 ie;
  622. aaci_chan_wait_ready(aacirun);
  623. ie = readl(aacirun->base + AACI_IE);
  624. ie &= ~(IE_ORIE | IE_RXIE);
  625. writel(ie, aacirun->base+AACI_IE);
  626. aacirun->cr &= ~CR_EN;
  627. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  628. }
  629. static void aaci_pcm_capture_start(struct aaci_runtime *aacirun)
  630. {
  631. u32 ie;
  632. aaci_chan_wait_ready(aacirun);
  633. #ifdef DEBUG
  634. /* RX Timeout value: bits 28:17 in RXCR */
  635. aacirun->cr |= 0xf << 17;
  636. #endif
  637. aacirun->cr |= CR_EN;
  638. writel(aacirun->cr, aacirun->base + AACI_RXCR);
  639. ie = readl(aacirun->base + AACI_IE);
  640. ie |= IE_ORIE |IE_RXIE; // overrun and rx interrupt -- half full
  641. writel(ie, aacirun->base + AACI_IE);
  642. }
  643. static int aaci_pcm_capture_trigger(struct snd_pcm_substream *substream, int cmd)
  644. {
  645. struct aaci *aaci = substream->private_data;
  646. struct aaci_runtime *aacirun = substream->runtime->private_data;
  647. unsigned long flags;
  648. int ret = 0;
  649. spin_lock_irqsave(&aaci->lock, flags);
  650. switch (cmd) {
  651. case SNDRV_PCM_TRIGGER_START:
  652. aaci_pcm_capture_start(aacirun);
  653. break;
  654. case SNDRV_PCM_TRIGGER_RESUME:
  655. aaci_pcm_capture_start(aacirun);
  656. break;
  657. case SNDRV_PCM_TRIGGER_STOP:
  658. aaci_pcm_capture_stop(aacirun);
  659. break;
  660. case SNDRV_PCM_TRIGGER_SUSPEND:
  661. aaci_pcm_capture_stop(aacirun);
  662. break;
  663. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  664. break;
  665. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  666. break;
  667. default:
  668. ret = -EINVAL;
  669. }
  670. spin_unlock_irqrestore(&aaci->lock, flags);
  671. return ret;
  672. }
  673. static int aaci_pcm_capture_prepare(struct snd_pcm_substream *substream)
  674. {
  675. struct snd_pcm_runtime *runtime = substream->runtime;
  676. struct aaci *aaci = substream->private_data;
  677. aaci_pcm_prepare(substream);
  678. /* allow changing of sample rate */
  679. aaci_ac97_write(aaci->ac97, AC97_EXTENDED_STATUS, 0x0001); /* VRA */
  680. aaci_ac97_write(aaci->ac97, AC97_PCM_LR_ADC_RATE, runtime->rate);
  681. aaci_ac97_write(aaci->ac97, AC97_PCM_MIC_ADC_RATE, runtime->rate);
  682. /* Record select: Mic: 0, Aux: 3, Line: 4 */
  683. aaci_ac97_write(aaci->ac97, AC97_REC_SEL, 0x0404);
  684. return 0;
  685. }
  686. static struct snd_pcm_ops aaci_capture_ops = {
  687. .open = aaci_pcm_open,
  688. .close = aaci_pcm_close,
  689. .ioctl = snd_pcm_lib_ioctl,
  690. .hw_params = aaci_pcm_capture_hw_params,
  691. .hw_free = aaci_pcm_hw_free,
  692. .prepare = aaci_pcm_capture_prepare,
  693. .trigger = aaci_pcm_capture_trigger,
  694. .pointer = aaci_pcm_pointer,
  695. .mmap = aaci_pcm_mmap,
  696. };
  697. /*
  698. * Power Management.
  699. */
  700. #ifdef CONFIG_PM
  701. static int aaci_do_suspend(struct snd_card *card, unsigned int state)
  702. {
  703. struct aaci *aaci = card->private_data;
  704. snd_power_change_state(card, SNDRV_CTL_POWER_D3cold);
  705. snd_pcm_suspend_all(aaci->pcm);
  706. return 0;
  707. }
  708. static int aaci_do_resume(struct snd_card *card, unsigned int state)
  709. {
  710. snd_power_change_state(card, SNDRV_CTL_POWER_D0);
  711. return 0;
  712. }
  713. static int aaci_suspend(struct amba_device *dev, pm_message_t state)
  714. {
  715. struct snd_card *card = amba_get_drvdata(dev);
  716. return card ? aaci_do_suspend(card) : 0;
  717. }
  718. static int aaci_resume(struct amba_device *dev)
  719. {
  720. struct snd_card *card = amba_get_drvdata(dev);
  721. return card ? aaci_do_resume(card) : 0;
  722. }
  723. #else
  724. #define aaci_do_suspend NULL
  725. #define aaci_do_resume NULL
  726. #define aaci_suspend NULL
  727. #define aaci_resume NULL
  728. #endif
  729. static struct ac97_pcm ac97_defs[] __devinitdata = {
  730. [0] = { /* Front PCM */
  731. .exclusive = 1,
  732. .r = {
  733. [0] = {
  734. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  735. (1 << AC97_SLOT_PCM_RIGHT) |
  736. (1 << AC97_SLOT_PCM_CENTER) |
  737. (1 << AC97_SLOT_PCM_SLEFT) |
  738. (1 << AC97_SLOT_PCM_SRIGHT) |
  739. (1 << AC97_SLOT_LFE),
  740. },
  741. },
  742. },
  743. [1] = { /* PCM in */
  744. .stream = 1,
  745. .exclusive = 1,
  746. .r = {
  747. [0] = {
  748. .slots = (1 << AC97_SLOT_PCM_LEFT) |
  749. (1 << AC97_SLOT_PCM_RIGHT),
  750. },
  751. },
  752. },
  753. [2] = { /* Mic in */
  754. .stream = 1,
  755. .exclusive = 1,
  756. .r = {
  757. [0] = {
  758. .slots = (1 << AC97_SLOT_MIC),
  759. },
  760. },
  761. }
  762. };
  763. static struct snd_ac97_bus_ops aaci_bus_ops = {
  764. .write = aaci_ac97_write,
  765. .read = aaci_ac97_read,
  766. };
  767. static int __devinit aaci_probe_ac97(struct aaci *aaci)
  768. {
  769. struct snd_ac97_template ac97_template;
  770. struct snd_ac97_bus *ac97_bus;
  771. struct snd_ac97 *ac97;
  772. int ret;
  773. /*
  774. * Assert AACIRESET for 2us
  775. */
  776. writel(0, aaci->base + AACI_RESET);
  777. udelay(2);
  778. writel(RESET_NRST, aaci->base + AACI_RESET);
  779. /*
  780. * Give the AC'97 codec more than enough time
  781. * to wake up. (42us = ~2 frames at 48kHz.)
  782. */
  783. udelay(42);
  784. ret = snd_ac97_bus(aaci->card, 0, &aaci_bus_ops, aaci, &ac97_bus);
  785. if (ret)
  786. goto out;
  787. ac97_bus->clock = 48000;
  788. aaci->ac97_bus = ac97_bus;
  789. memset(&ac97_template, 0, sizeof(struct snd_ac97_template));
  790. ac97_template.private_data = aaci;
  791. ac97_template.num = 0;
  792. ac97_template.scaps = AC97_SCAP_SKIP_MODEM;
  793. ret = snd_ac97_mixer(ac97_bus, &ac97_template, &ac97);
  794. if (ret)
  795. goto out;
  796. aaci->ac97 = ac97;
  797. /*
  798. * Disable AC97 PC Beep input on audio codecs.
  799. */
  800. if (ac97_is_audio(ac97))
  801. snd_ac97_write_cache(ac97, AC97_PC_BEEP, 0x801e);
  802. ret = snd_ac97_pcm_assign(ac97_bus, ARRAY_SIZE(ac97_defs), ac97_defs);
  803. if (ret)
  804. goto out;
  805. aaci->playback.pcm = &ac97_bus->pcms[0];
  806. aaci->capture.pcm = &ac97_bus->pcms[1];
  807. out:
  808. return ret;
  809. }
  810. static void aaci_free_card(struct snd_card *card)
  811. {
  812. struct aaci *aaci = card->private_data;
  813. if (aaci->base)
  814. iounmap(aaci->base);
  815. }
  816. static struct aaci * __devinit aaci_init_card(struct amba_device *dev)
  817. {
  818. struct aaci *aaci;
  819. struct snd_card *card;
  820. card = snd_card_new(SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1,
  821. THIS_MODULE, sizeof(struct aaci));
  822. if (card == NULL)
  823. return ERR_PTR(-ENOMEM);
  824. card->private_free = aaci_free_card;
  825. strlcpy(card->driver, DRIVER_NAME, sizeof(card->driver));
  826. strlcpy(card->shortname, "ARM AC'97 Interface", sizeof(card->shortname));
  827. snprintf(card->longname, sizeof(card->longname),
  828. "%s at 0x%016llx, irq %d",
  829. card->shortname, (unsigned long long)dev->res.start,
  830. dev->irq[0]);
  831. aaci = card->private_data;
  832. mutex_init(&aaci->ac97_sem);
  833. spin_lock_init(&aaci->lock);
  834. aaci->card = card;
  835. aaci->dev = dev;
  836. /* Set MAINCR to allow slot 1 and 2 data IO */
  837. aaci->maincr = MAINCR_IE | MAINCR_SL1RXEN | MAINCR_SL1TXEN |
  838. MAINCR_SL2RXEN | MAINCR_SL2TXEN;
  839. return aaci;
  840. }
  841. static int __devinit aaci_init_pcm(struct aaci *aaci)
  842. {
  843. struct snd_pcm *pcm;
  844. int ret;
  845. ret = snd_pcm_new(aaci->card, "AACI AC'97", 0, 1, 1, &pcm);
  846. if (ret == 0) {
  847. aaci->pcm = pcm;
  848. pcm->private_data = aaci;
  849. pcm->info_flags = 0;
  850. strlcpy(pcm->name, DRIVER_NAME, sizeof(pcm->name));
  851. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &aaci_playback_ops);
  852. snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &aaci_capture_ops);
  853. }
  854. return ret;
  855. }
  856. static unsigned int __devinit aaci_size_fifo(struct aaci *aaci)
  857. {
  858. struct aaci_runtime *aacirun = &aaci->playback;
  859. int i;
  860. writel(CR_FEN | CR_SZ16 | CR_EN, aacirun->base + AACI_TXCR);
  861. for (i = 0; !(readl(aacirun->base + AACI_SR) & SR_TXFF) && i < 4096; i++)
  862. writel(0, aacirun->fifo);
  863. writel(0, aacirun->base + AACI_TXCR);
  864. /*
  865. * Re-initialise the AACI after the FIFO depth test, to
  866. * ensure that the FIFOs are empty. Unfortunately, merely
  867. * disabling the channel doesn't clear the FIFO.
  868. */
  869. writel(aaci->maincr & ~MAINCR_IE, aaci->base + AACI_MAINCR);
  870. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  871. /*
  872. * If we hit 4096, we failed. Go back to the specified
  873. * fifo depth.
  874. */
  875. if (i == 4096)
  876. i = 8;
  877. return i;
  878. }
  879. static int __devinit aaci_probe(struct amba_device *dev, void *id)
  880. {
  881. struct aaci *aaci;
  882. int ret, i;
  883. ret = amba_request_regions(dev, NULL);
  884. if (ret)
  885. return ret;
  886. aaci = aaci_init_card(dev);
  887. if (IS_ERR(aaci)) {
  888. ret = PTR_ERR(aaci);
  889. goto out;
  890. }
  891. aaci->base = ioremap(dev->res.start, SZ_4K);
  892. if (!aaci->base) {
  893. ret = -ENOMEM;
  894. goto out;
  895. }
  896. /*
  897. * Playback uses AACI channel 0
  898. */
  899. aaci->playback.base = aaci->base + AACI_CSCH1;
  900. aaci->playback.fifo = aaci->base + AACI_DR1;
  901. /*
  902. * Capture uses AACI channel 0
  903. */
  904. aaci->capture.base = aaci->base + AACI_CSCH1;
  905. aaci->capture.fifo = aaci->base + AACI_DR1;
  906. for (i = 0; i < 4; i++) {
  907. void __iomem *base = aaci->base + i * 0x14;
  908. writel(0, base + AACI_IE);
  909. writel(0, base + AACI_TXCR);
  910. writel(0, base + AACI_RXCR);
  911. }
  912. writel(0x1fff, aaci->base + AACI_INTCLR);
  913. writel(aaci->maincr, aaci->base + AACI_MAINCR);
  914. ret = aaci_probe_ac97(aaci);
  915. if (ret)
  916. goto out;
  917. /*
  918. * Size the FIFOs (must be multiple of 16).
  919. */
  920. aaci->fifosize = aaci_size_fifo(aaci);
  921. if (aaci->fifosize & 15) {
  922. printk(KERN_WARNING "AACI: fifosize = %d not supported\n",
  923. aaci->fifosize);
  924. ret = -ENODEV;
  925. goto out;
  926. }
  927. ret = aaci_init_pcm(aaci);
  928. if (ret)
  929. goto out;
  930. snd_card_set_dev(aaci->card, &dev->dev);
  931. ret = snd_card_register(aaci->card);
  932. if (ret == 0) {
  933. dev_info(&dev->dev, "%s, fifo %d\n", aaci->card->longname,
  934. aaci->fifosize);
  935. amba_set_drvdata(dev, aaci->card);
  936. return ret;
  937. }
  938. out:
  939. if (aaci)
  940. snd_card_free(aaci->card);
  941. amba_release_regions(dev);
  942. return ret;
  943. }
  944. static int __devexit aaci_remove(struct amba_device *dev)
  945. {
  946. struct snd_card *card = amba_get_drvdata(dev);
  947. amba_set_drvdata(dev, NULL);
  948. if (card) {
  949. struct aaci *aaci = card->private_data;
  950. writel(0, aaci->base + AACI_MAINCR);
  951. snd_card_free(card);
  952. amba_release_regions(dev);
  953. }
  954. return 0;
  955. }
  956. static struct amba_id aaci_ids[] = {
  957. {
  958. .id = 0x00041041,
  959. .mask = 0x000fffff,
  960. },
  961. { 0, 0 },
  962. };
  963. static struct amba_driver aaci_driver = {
  964. .drv = {
  965. .name = DRIVER_NAME,
  966. },
  967. .probe = aaci_probe,
  968. .remove = __devexit_p(aaci_remove),
  969. .suspend = aaci_suspend,
  970. .resume = aaci_resume,
  971. .id_table = aaci_ids,
  972. };
  973. static int __init aaci_init(void)
  974. {
  975. return amba_driver_register(&aaci_driver);
  976. }
  977. static void __exit aaci_exit(void)
  978. {
  979. amba_driver_unregister(&aaci_driver);
  980. }
  981. module_init(aaci_init);
  982. module_exit(aaci_exit);
  983. MODULE_LICENSE("GPL");
  984. MODULE_DESCRIPTION("ARM PrimeCell PL041 Advanced Audio CODEC Interface driver");