tgafb.h 6.0 KB

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  1. /*
  2. * linux/drivers/video/tgafb.h -- DEC 21030 TGA frame buffer device
  3. *
  4. * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
  5. *
  6. * $Id: tgafb.h,v 1.1.1.1 2007/06/12 07:27:16 eyryu Exp $
  7. *
  8. * This file is subject to the terms and conditions of the GNU General Public
  9. * License. See the file COPYING in the main directory of this archive for
  10. * more details.
  11. */
  12. #ifndef TGAFB_H
  13. #define TGAFB_H
  14. /*
  15. * TGA hardware description (minimal)
  16. */
  17. #define TGA_TYPE_8PLANE 0
  18. #define TGA_TYPE_24PLANE 1
  19. #define TGA_TYPE_24PLUSZ 3
  20. /*
  21. * Offsets within Memory Space
  22. */
  23. #define TGA_ROM_OFFSET 0x0000000
  24. #define TGA_REGS_OFFSET 0x0100000
  25. #define TGA_8PLANE_FB_OFFSET 0x0200000
  26. #define TGA_24PLANE_FB_OFFSET 0x0804000
  27. #define TGA_24PLUSZ_FB_OFFSET 0x1004000
  28. #define TGA_FOREGROUND_REG 0x0020
  29. #define TGA_BACKGROUND_REG 0x0024
  30. #define TGA_PLANEMASK_REG 0x0028
  31. #define TGA_PIXELMASK_ONESHOT_REG 0x002c
  32. #define TGA_MODE_REG 0x0030
  33. #define TGA_RASTEROP_REG 0x0034
  34. #define TGA_PIXELSHIFT_REG 0x0038
  35. #define TGA_DEEP_REG 0x0050
  36. #define TGA_PIXELMASK_REG 0x005c
  37. #define TGA_CURSOR_BASE_REG 0x0060
  38. #define TGA_HORIZ_REG 0x0064
  39. #define TGA_VERT_REG 0x0068
  40. #define TGA_BASE_ADDR_REG 0x006c
  41. #define TGA_VALID_REG 0x0070
  42. #define TGA_CURSOR_XY_REG 0x0074
  43. #define TGA_INTR_STAT_REG 0x007c
  44. #define TGA_DATA_REG 0x0080
  45. #define TGA_RAMDAC_SETUP_REG 0x00c0
  46. #define TGA_BLOCK_COLOR0_REG 0x0140
  47. #define TGA_BLOCK_COLOR1_REG 0x0144
  48. #define TGA_BLOCK_COLOR2_REG 0x0148
  49. #define TGA_BLOCK_COLOR3_REG 0x014c
  50. #define TGA_BLOCK_COLOR4_REG 0x0150
  51. #define TGA_BLOCK_COLOR5_REG 0x0154
  52. #define TGA_BLOCK_COLOR6_REG 0x0158
  53. #define TGA_BLOCK_COLOR7_REG 0x015c
  54. #define TGA_COPY64_SRC 0x0160
  55. #define TGA_COPY64_DST 0x0164
  56. #define TGA_CLOCK_REG 0x01e8
  57. #define TGA_RAMDAC_REG 0x01f0
  58. #define TGA_CMD_STAT_REG 0x01f8
  59. /*
  60. * Useful defines for managing the registers
  61. */
  62. #define TGA_HORIZ_ODD 0x80000000
  63. #define TGA_HORIZ_POLARITY 0x40000000
  64. #define TGA_HORIZ_ACT_MSB 0x30000000
  65. #define TGA_HORIZ_BP 0x0fe00000
  66. #define TGA_HORIZ_SYNC 0x001fc000
  67. #define TGA_HORIZ_FP 0x00007c00
  68. #define TGA_HORIZ_ACT_LSB 0x000001ff
  69. #define TGA_VERT_SE 0x80000000
  70. #define TGA_VERT_POLARITY 0x40000000
  71. #define TGA_VERT_RESERVED 0x30000000
  72. #define TGA_VERT_BP 0x0fc00000
  73. #define TGA_VERT_SYNC 0x003f0000
  74. #define TGA_VERT_FP 0x0000f800
  75. #define TGA_VERT_ACTIVE 0x000007ff
  76. #define TGA_VALID_VIDEO 0x01
  77. #define TGA_VALID_BLANK 0x02
  78. #define TGA_VALID_CURSOR 0x04
  79. #define TGA_MODE_SBM_8BPP 0x000
  80. #define TGA_MODE_SBM_24BPP 0x300
  81. #define TGA_MODE_SIMPLE 0x00
  82. #define TGA_MODE_SIMPLEZ 0x10
  83. #define TGA_MODE_OPAQUE_STIPPLE 0x01
  84. #define TGA_MODE_OPAQUE_FILL 0x21
  85. #define TGA_MODE_TRANSPARENT_STIPPLE 0x03
  86. #define TGA_MODE_TRANSPARENT_FILL 0x23
  87. #define TGA_MODE_BLOCK_STIPPLE 0x0d
  88. #define TGA_MODE_BLOCK_FILL 0x2d
  89. #define TGA_MODE_COPY 0x07
  90. #define TGA_MODE_DMA_READ_COPY_ND 0x17
  91. #define TGA_MODE_DMA_READ_COPY_D 0x37
  92. #define TGA_MODE_DMA_WRITE_COPY 0x1f
  93. /*
  94. * Useful defines for managing the ICS1562 PLL clock
  95. */
  96. #define TGA_PLL_BASE_FREQ 14318 /* .18 */
  97. #define TGA_PLL_MAX_FREQ 230000
  98. /*
  99. * Useful defines for managing the BT485 on the 8-plane TGA
  100. */
  101. #define BT485_READ_BIT 0x01
  102. #define BT485_WRITE_BIT 0x00
  103. #define BT485_ADDR_PAL_WRITE 0x00
  104. #define BT485_DATA_PAL 0x02
  105. #define BT485_PIXEL_MASK 0x04
  106. #define BT485_ADDR_PAL_READ 0x06
  107. #define BT485_ADDR_CUR_WRITE 0x08
  108. #define BT485_DATA_CUR 0x0a
  109. #define BT485_CMD_0 0x0c
  110. #define BT485_ADDR_CUR_READ 0x0e
  111. #define BT485_CMD_1 0x10
  112. #define BT485_CMD_2 0x12
  113. #define BT485_STATUS 0x14
  114. #define BT485_CMD_3 0x14
  115. #define BT485_CUR_RAM 0x16
  116. #define BT485_CUR_LOW_X 0x18
  117. #define BT485_CUR_HIGH_X 0x1a
  118. #define BT485_CUR_LOW_Y 0x1c
  119. #define BT485_CUR_HIGH_Y 0x1e
  120. /*
  121. * Useful defines for managing the BT463 on the 24-plane TGAs
  122. */
  123. #define BT463_ADDR_LO 0x0
  124. #define BT463_ADDR_HI 0x1
  125. #define BT463_REG_ACC 0x2
  126. #define BT463_PALETTE 0x3
  127. #define BT463_CUR_CLR_0 0x0100
  128. #define BT463_CUR_CLR_1 0x0101
  129. #define BT463_CMD_REG_0 0x0201
  130. #define BT463_CMD_REG_1 0x0202
  131. #define BT463_CMD_REG_2 0x0203
  132. #define BT463_READ_MASK_0 0x0205
  133. #define BT463_READ_MASK_1 0x0206
  134. #define BT463_READ_MASK_2 0x0207
  135. #define BT463_READ_MASK_3 0x0208
  136. #define BT463_BLINK_MASK_0 0x0209
  137. #define BT463_BLINK_MASK_1 0x020a
  138. #define BT463_BLINK_MASK_2 0x020b
  139. #define BT463_BLINK_MASK_3 0x020c
  140. #define BT463_WINDOW_TYPE_BASE 0x0300
  141. /*
  142. * The framebuffer driver private data.
  143. */
  144. struct tga_par {
  145. /* PCI device. */
  146. struct pci_dev *pdev;
  147. /* Device dependent information. */
  148. void __iomem *tga_mem_base;
  149. void __iomem *tga_fb_base;
  150. void __iomem *tga_regs_base;
  151. u8 tga_type; /* TGA_TYPE_XXX */
  152. u8 tga_chip_rev; /* dc21030 revision */
  153. /* Remember blank mode. */
  154. u8 vesa_blanked;
  155. /* Define the video mode. */
  156. u32 xres, yres; /* resolution in pixels */
  157. u32 htimings; /* horizontal timing register */
  158. u32 vtimings; /* vertical timing register */
  159. u32 pll_freq; /* pixclock in mhz */
  160. u32 bits_per_pixel; /* bits per pixel */
  161. u32 sync_on_green; /* set if sync is on green */
  162. };
  163. /*
  164. * Macros for reading/writing TGA and RAMDAC registers
  165. */
  166. static inline void
  167. TGA_WRITE_REG(struct tga_par *par, u32 v, u32 r)
  168. {
  169. writel(v, par->tga_regs_base +r);
  170. }
  171. static inline u32
  172. TGA_READ_REG(struct tga_par *par, u32 r)
  173. {
  174. return readl(par->tga_regs_base +r);
  175. }
  176. static inline void
  177. BT485_WRITE(struct tga_par *par, u8 v, u8 r)
  178. {
  179. TGA_WRITE_REG(par, r, TGA_RAMDAC_SETUP_REG);
  180. TGA_WRITE_REG(par, v | (r << 8), TGA_RAMDAC_REG);
  181. }
  182. static inline void
  183. BT463_LOAD_ADDR(struct tga_par *par, u16 a)
  184. {
  185. TGA_WRITE_REG(par, BT463_ADDR_LO<<2, TGA_RAMDAC_SETUP_REG);
  186. TGA_WRITE_REG(par, (BT463_ADDR_LO<<10) | (a & 0xff), TGA_RAMDAC_REG);
  187. TGA_WRITE_REG(par, BT463_ADDR_HI<<2, TGA_RAMDAC_SETUP_REG);
  188. TGA_WRITE_REG(par, (BT463_ADDR_HI<<10) | (a >> 8), TGA_RAMDAC_REG);
  189. }
  190. static inline void
  191. BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
  192. {
  193. BT463_LOAD_ADDR(par, a);
  194. TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
  195. TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
  196. }
  197. #endif /* TGAFB_H */