newport.h 19 KB

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  1. /* $Id: newport.h,v 1.1.1.1 2007/06/12 07:27:16 eyryu Exp $
  2. *
  3. * newport.h: Defines and register layout for NEWPORT graphics
  4. * hardware.
  5. *
  6. * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
  7. *
  8. * Ulf Carlsson - Compability with the IRIX structures added
  9. */
  10. #ifndef _SGI_NEWPORT_H
  11. #define _SGI_NEWPORT_H
  12. typedef volatile unsigned int npireg_t;
  13. union npfloat {
  14. volatile float flt;
  15. npireg_t word;
  16. };
  17. typedef union npfloat npfreg_t;
  18. union np_dcb {
  19. npireg_t byword;
  20. struct { volatile unsigned short s0, s1; } byshort;
  21. struct { volatile unsigned char b0, b1, b2, b3; } bybytes;
  22. };
  23. struct newport_rexregs {
  24. npireg_t drawmode1; /* GL extra mode bits */
  25. #define DM1_PLANES 0x00000007
  26. #define DM1_NOPLANES 0x00000000
  27. #define DM1_RGBPLANES 0x00000001
  28. #define DM1_RGBAPLANES 0x00000002
  29. #define DM1_OLAYPLANES 0x00000004
  30. #define DM1_PUPPLANES 0x00000005
  31. #define DM1_CIDPLANES 0x00000006
  32. #define NPORT_DMODE1_DDMASK 0x00000018
  33. #define NPORT_DMODE1_DD4 0x00000000
  34. #define NPORT_DMODE1_DD8 0x00000008
  35. #define NPORT_DMODE1_DD12 0x00000010
  36. #define NPORT_DMODE1_DD24 0x00000018
  37. #define NPORT_DMODE1_DSRC 0x00000020
  38. #define NPORT_DMODE1_YFLIP 0x00000040
  39. #define NPORT_DMODE1_RWPCKD 0x00000080
  40. #define NPORT_DMODE1_HDMASK 0x00000300
  41. #define NPORT_DMODE1_HD4 0x00000000
  42. #define NPORT_DMODE1_HD8 0x00000100
  43. #define NPORT_DMODE1_HD12 0x00000200
  44. #define NPORT_DMODE1_HD32 0x00000300
  45. #define NPORT_DMODE1_RWDBL 0x00000400
  46. #define NPORT_DMODE1_ESWAP 0x00000800 /* Endian swap */
  47. #define NPORT_DMODE1_CCMASK 0x00007000
  48. #define NPORT_DMODE1_CCLT 0x00001000
  49. #define NPORT_DMODE1_CCEQ 0x00002000
  50. #define NPORT_DMODE1_CCGT 0x00004000
  51. #define NPORT_DMODE1_RGBMD 0x00008000
  52. #define NPORT_DMODE1_DENAB 0x00010000 /* Dither enable */
  53. #define NPORT_DMODE1_FCLR 0x00020000 /* Fast clear */
  54. #define NPORT_DMODE1_BENAB 0x00040000 /* Blend enable */
  55. #define NPORT_DMODE1_SFMASK 0x00380000
  56. #define NPORT_DMODE1_SF0 0x00000000
  57. #define NPORT_DMODE1_SF1 0x00080000
  58. #define NPORT_DMODE1_SFDC 0x00100000
  59. #define NPORT_DMODE1_SFMDC 0x00180000
  60. #define NPORT_DMODE1_SFSA 0x00200000
  61. #define NPORT_DMODE1_SFMSA 0x00280000
  62. #define NPORT_DMODE1_DFMASK 0x01c00000
  63. #define NPORT_DMODE1_DF0 0x00000000
  64. #define NPORT_DMODE1_DF1 0x00400000
  65. #define NPORT_DMODE1_DFSC 0x00800000
  66. #define NPORT_DMODE1_DFMSC 0x00c00000
  67. #define NPORT_DMODE1_DFSA 0x01000000
  68. #define NPORT_DMODE1_DFMSA 0x01400000
  69. #define NPORT_DMODE1_BBENAB 0x02000000 /* Back blend enable */
  70. #define NPORT_DMODE1_PFENAB 0x04000000 /* Pre-fetch enable */
  71. #define NPORT_DMODE1_ABLEND 0x08000000 /* Alpha blend */
  72. #define NPORT_DMODE1_LOMASK 0xf0000000
  73. #define NPORT_DMODE1_LOZERO 0x00000000
  74. #define NPORT_DMODE1_LOAND 0x10000000
  75. #define NPORT_DMODE1_LOANDR 0x20000000
  76. #define NPORT_DMODE1_LOSRC 0x30000000
  77. #define NPORT_DMODE1_LOANDI 0x40000000
  78. #define NPORT_DMODE1_LODST 0x50000000
  79. #define NPORT_DMODE1_LOXOR 0x60000000
  80. #define NPORT_DMODE1_LOOR 0x70000000
  81. #define NPORT_DMODE1_LONOR 0x80000000
  82. #define NPORT_DMODE1_LOXNOR 0x90000000
  83. #define NPORT_DMODE1_LONDST 0xa0000000
  84. #define NPORT_DMODE1_LOORR 0xb0000000
  85. #define NPORT_DMODE1_LONSRC 0xc0000000
  86. #define NPORT_DMODE1_LOORI 0xd0000000
  87. #define NPORT_DMODE1_LONAND 0xe0000000
  88. #define NPORT_DMODE1_LOONE 0xf0000000
  89. npireg_t drawmode0; /* REX command register */
  90. /* These bits define the graphics opcode being performed. */
  91. #define NPORT_DMODE0_OPMASK 0x00000003 /* Opcode mask */
  92. #define NPORT_DMODE0_NOP 0x00000000 /* No operation */
  93. #define NPORT_DMODE0_RD 0x00000001 /* Read operation */
  94. #define NPORT_DMODE0_DRAW 0x00000002 /* Draw operation */
  95. #define NPORT_DMODE0_S2S 0x00000003 /* Screen to screen operation */
  96. /* The following decide what addressing mode(s) are to be used */
  97. #define NPORT_DMODE0_AMMASK 0x0000001c /* Address mode mask */
  98. #define NPORT_DMODE0_SPAN 0x00000000 /* Spanning address mode */
  99. #define NPORT_DMODE0_BLOCK 0x00000004 /* Block address mode */
  100. #define NPORT_DMODE0_ILINE 0x00000008 /* Iline address mode */
  101. #define NPORT_DMODE0_FLINE 0x0000000c /* Fline address mode */
  102. #define NPORT_DMODE0_ALINE 0x00000010 /* Aline address mode */
  103. #define NPORT_DMODE0_TLINE 0x00000014 /* Tline address mode */
  104. #define NPORT_DMODE0_BLINE 0x00000018 /* Bline address mode */
  105. /* And now some misc. operation control bits. */
  106. #define NPORT_DMODE0_DOSETUP 0x00000020
  107. #define NPORT_DMODE0_CHOST 0x00000040
  108. #define NPORT_DMODE0_AHOST 0x00000080
  109. #define NPORT_DMODE0_STOPX 0x00000100
  110. #define NPORT_DMODE0_STOPY 0x00000200
  111. #define NPORT_DMODE0_SK1ST 0x00000400
  112. #define NPORT_DMODE0_SKLST 0x00000800
  113. #define NPORT_DMODE0_ZPENAB 0x00001000
  114. #define NPORT_DMODE0_LISPENAB 0x00002000
  115. #define NPORT_DMODE0_LISLST 0x00004000
  116. #define NPORT_DMODE0_L32 0x00008000
  117. #define NPORT_DMODE0_ZOPQ 0x00010000
  118. #define NPORT_DMODE0_LISOPQ 0x00020000
  119. #define NPORT_DMODE0_SHADE 0x00040000
  120. #define NPORT_DMODE0_LRONLY 0x00080000
  121. #define NPORT_DMODE0_XYOFF 0x00100000
  122. #define NPORT_DMODE0_CLAMP 0x00200000
  123. #define NPORT_DMODE0_ENDPF 0x00400000
  124. #define NPORT_DMODE0_YSTR 0x00800000
  125. npireg_t lsmode; /* Mode for line stipple ops */
  126. npireg_t lspattern; /* Pattern for line stipple ops */
  127. npireg_t lspatsave; /* Backup save pattern */
  128. npireg_t zpattern; /* Pixel zpattern */
  129. npireg_t colorback; /* Background color */
  130. npireg_t colorvram; /* Clear color for fast vram */
  131. npireg_t alpharef; /* Reference value for afunctions */
  132. unsigned int pad0;
  133. npireg_t smask0x; /* Window GL relative screen mask 0 */
  134. npireg_t smask0y; /* Window GL relative screen mask 0 */
  135. npireg_t _setup;
  136. npireg_t _stepz;
  137. npireg_t _lsrestore;
  138. npireg_t _lssave;
  139. unsigned int _pad1[0x30];
  140. /* Iterators, full state for context switch */
  141. npfreg_t _xstart; /* X-start point (current) */
  142. npfreg_t _ystart; /* Y-start point (current) */
  143. npfreg_t _xend; /* x-end point */
  144. npfreg_t _yend; /* y-end point */
  145. npireg_t xsave; /* copy of xstart integer value for BLOCk addressing MODE */
  146. npireg_t xymove; /* x.y offset from xstart, ystart for relative operations */
  147. npfreg_t bresd;
  148. npfreg_t bress1;
  149. npireg_t bresoctinc1;
  150. volatile int bresrndinc2;
  151. npireg_t brese1;
  152. npireg_t bress2;
  153. npireg_t aweight0;
  154. npireg_t aweight1;
  155. npfreg_t xstartf;
  156. npfreg_t ystartf;
  157. npfreg_t xendf;
  158. npfreg_t yendf;
  159. npireg_t xstarti;
  160. npfreg_t xendf1;
  161. npireg_t xystarti;
  162. npireg_t xyendi;
  163. npireg_t xstartendi;
  164. unsigned int _unused2[0x29];
  165. npfreg_t colorred;
  166. npfreg_t coloralpha;
  167. npfreg_t colorgrn;
  168. npfreg_t colorblue;
  169. npfreg_t slopered;
  170. npfreg_t slopealpha;
  171. npfreg_t slopegrn;
  172. npfreg_t slopeblue;
  173. npireg_t wrmask;
  174. npireg_t colori;
  175. npfreg_t colorx;
  176. npfreg_t slopered1;
  177. npireg_t hostrw0;
  178. npireg_t hostrw1;
  179. npireg_t dcbmode;
  180. #define NPORT_DMODE_WMASK 0x00000003
  181. #define NPORT_DMODE_W4 0x00000000
  182. #define NPORT_DMODE_W1 0x00000001
  183. #define NPORT_DMODE_W2 0x00000002
  184. #define NPORT_DMODE_W3 0x00000003
  185. #define NPORT_DMODE_EDPACK 0x00000004
  186. #define NPORT_DMODE_ECINC 0x00000008
  187. #define NPORT_DMODE_CMASK 0x00000070
  188. #define NPORT_DMODE_AMASK 0x00000780
  189. #define NPORT_DMODE_AVC2 0x00000000
  190. #define NPORT_DMODE_ACMALL 0x00000080
  191. #define NPORT_DMODE_ACM0 0x00000100
  192. #define NPORT_DMODE_ACM1 0x00000180
  193. #define NPORT_DMODE_AXMALL 0x00000200
  194. #define NPORT_DMODE_AXM0 0x00000280
  195. #define NPORT_DMODE_AXM1 0x00000300
  196. #define NPORT_DMODE_ABT 0x00000380
  197. #define NPORT_DMODE_AVCC1 0x00000400
  198. #define NPORT_DMODE_AVAB1 0x00000480
  199. #define NPORT_DMODE_ALG3V0 0x00000500
  200. #define NPORT_DMODE_A1562 0x00000580
  201. #define NPORT_DMODE_ESACK 0x00000800
  202. #define NPORT_DMODE_EASACK 0x00001000
  203. #define NPORT_DMODE_CWMASK 0x0003e000
  204. #define NPORT_DMODE_CHMASK 0x007c0000
  205. #define NPORT_DMODE_CSMASK 0x0f800000
  206. #define NPORT_DMODE_SENDIAN 0x10000000
  207. unsigned int _unused3;
  208. union np_dcb dcbdata0;
  209. npireg_t dcbdata1;
  210. };
  211. struct newport_cregs {
  212. npireg_t smask1x;
  213. npireg_t smask1y;
  214. npireg_t smask2x;
  215. npireg_t smask2y;
  216. npireg_t smask3x;
  217. npireg_t smask3y;
  218. npireg_t smask4x;
  219. npireg_t smask4y;
  220. npireg_t topscan;
  221. npireg_t xywin;
  222. npireg_t clipmode;
  223. #define NPORT_CMODE_SM0 0x00000001
  224. #define NPORT_CMODE_SM1 0x00000002
  225. #define NPORT_CMODE_SM2 0x00000004
  226. #define NPORT_CMODE_SM3 0x00000008
  227. #define NPORT_CMODE_SM4 0x00000010
  228. #define NPORT_CMODE_CMSK 0x00001e00
  229. unsigned int _unused0;
  230. unsigned int config;
  231. #define NPORT_CFG_G32MD 0x00000001
  232. #define NPORT_CFG_BWIDTH 0x00000002
  233. #define NPORT_CFG_ERCVR 0x00000004
  234. #define NPORT_CFG_BDMSK 0x00000078
  235. #define NPORT_CFG_BFAINT 0x00000080
  236. #define NPORT_CFG_GDMSK 0x00001f80
  237. #define NPORT_CFG_GD0 0x00000100
  238. #define NPORT_CFG_GD1 0x00000200
  239. #define NPORT_CFG_GD2 0x00000400
  240. #define NPORT_CFG_GD3 0x00000800
  241. #define NPORT_CFG_GD4 0x00001000
  242. #define NPORT_CFG_GFAINT 0x00002000
  243. #define NPORT_CFG_TOMSK 0x0001c000
  244. #define NPORT_CFG_VRMSK 0x000e0000
  245. #define NPORT_CFG_FBTYP 0x00100000
  246. npireg_t _unused1;
  247. npireg_t status;
  248. #define NPORT_STAT_VERS 0x00000007
  249. #define NPORT_STAT_GBUSY 0x00000008
  250. #define NPORT_STAT_BBUSY 0x00000010
  251. #define NPORT_STAT_VRINT 0x00000020
  252. #define NPORT_STAT_VIDINT 0x00000040
  253. #define NPORT_STAT_GLMSK 0x00001f80
  254. #define NPORT_STAT_BLMSK 0x0007e000
  255. #define NPORT_STAT_BFIRQ 0x00080000
  256. #define NPORT_STAT_GFIRQ 0x00100000
  257. npireg_t ustatus;
  258. npireg_t dcbreset;
  259. };
  260. struct newport_regs {
  261. struct newport_rexregs set;
  262. unsigned int _unused0[0x16e];
  263. struct newport_rexregs go;
  264. unsigned int _unused1[0x22e];
  265. struct newport_cregs cset;
  266. unsigned int _unused2[0x1ef];
  267. struct newport_cregs cgo;
  268. };
  269. typedef struct {
  270. unsigned int drawmode1;
  271. unsigned int drawmode0;
  272. unsigned int lsmode;
  273. unsigned int lspattern;
  274. unsigned int lspatsave;
  275. unsigned int zpattern;
  276. unsigned int colorback;
  277. unsigned int colorvram;
  278. unsigned int alpharef;
  279. unsigned int smask0x;
  280. unsigned int smask0y;
  281. unsigned int _xstart;
  282. unsigned int _ystart;
  283. unsigned int _xend;
  284. unsigned int _yend;
  285. unsigned int xsave;
  286. unsigned int xymove;
  287. unsigned int bresd;
  288. unsigned int bress1;
  289. unsigned int bresoctinc1;
  290. unsigned int bresrndinc2;
  291. unsigned int brese1;
  292. unsigned int bress2;
  293. unsigned int aweight0;
  294. unsigned int aweight1;
  295. unsigned int colorred;
  296. unsigned int coloralpha;
  297. unsigned int colorgrn;
  298. unsigned int colorblue;
  299. unsigned int slopered;
  300. unsigned int slopealpha;
  301. unsigned int slopegrn;
  302. unsigned int slopeblue;
  303. unsigned int wrmask;
  304. unsigned int hostrw0;
  305. unsigned int hostrw1;
  306. /* configregs */
  307. unsigned int smask1x;
  308. unsigned int smask1y;
  309. unsigned int smask2x;
  310. unsigned int smask2y;
  311. unsigned int smask3x;
  312. unsigned int smask3y;
  313. unsigned int smask4x;
  314. unsigned int smask4y;
  315. unsigned int topscan;
  316. unsigned int xywin;
  317. unsigned int clipmode;
  318. unsigned int config;
  319. /* dcb registers */
  320. unsigned int dcbmode;
  321. unsigned int dcbdata0;
  322. unsigned int dcbdata1;
  323. } newport_ctx;
  324. /* Reading/writing VC2 registers. */
  325. #define VC2_REGADDR_INDEX 0x00000000
  326. #define VC2_REGADDR_IREG 0x00000010
  327. #define VC2_REGADDR_RAM 0x00000030
  328. #define VC2_PROTOCOL (NPORT_DMODE_EASACK | 0x00800000 | 0x00040000)
  329. #define VC2_VLINET_ADDR 0x000
  330. #define VC2_VFRAMET_ADDR 0x400
  331. #define VC2_CGLYPH_ADDR 0x500
  332. /* Now the Indexed registers of the VC2. */
  333. #define VC2_IREG_VENTRY 0x00
  334. #define VC2_IREG_CENTRY 0x01
  335. #define VC2_IREG_CURSX 0x02
  336. #define VC2_IREG_CURSY 0x03
  337. #define VC2_IREG_CCURSX 0x04
  338. #define VC2_IREG_DENTRY 0x05
  339. #define VC2_IREG_SLEN 0x06
  340. #define VC2_IREG_RADDR 0x07
  341. #define VC2_IREG_VFPTR 0x08
  342. #define VC2_IREG_VLSPTR 0x09
  343. #define VC2_IREG_VLIR 0x0a
  344. #define VC2_IREG_VLCTR 0x0b
  345. #define VC2_IREG_CTPTR 0x0c
  346. #define VC2_IREG_WCURSY 0x0d
  347. #define VC2_IREG_DFPTR 0x0e
  348. #define VC2_IREG_DLTPTR 0x0f
  349. #define VC2_IREG_CONTROL 0x10
  350. #define VC2_IREG_CONFIG 0x20
  351. static inline void newport_vc2_set(struct newport_regs *regs,
  352. unsigned char vc2ireg,
  353. unsigned short val)
  354. {
  355. regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W3 |
  356. NPORT_DMODE_ECINC | VC2_PROTOCOL);
  357. regs->set.dcbdata0.byword = (vc2ireg << 24) | (val << 8);
  358. }
  359. static inline unsigned short newport_vc2_get(struct newport_regs *regs,
  360. unsigned char vc2ireg)
  361. {
  362. regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_INDEX | NPORT_DMODE_W1 |
  363. NPORT_DMODE_ECINC | VC2_PROTOCOL);
  364. regs->set.dcbdata0.bybytes.b3 = vc2ireg;
  365. regs->set.dcbmode = (NPORT_DMODE_AVC2 | VC2_REGADDR_IREG | NPORT_DMODE_W2 |
  366. NPORT_DMODE_ECINC | VC2_PROTOCOL);
  367. return regs->set.dcbdata0.byshort.s1;
  368. }
  369. /* VC2 Control register bits */
  370. #define VC2_CTRL_EVIRQ 0x0001
  371. #define VC2_CTRL_EDISP 0x0002
  372. #define VC2_CTRL_EVIDEO 0x0004
  373. #define VC2_CTRL_EDIDS 0x0008
  374. #define VC2_CTRL_ECURS 0x0010
  375. #define VC2_CTRL_EGSYNC 0x0020
  376. #define VC2_CTRL_EILACE 0x0040
  377. #define VC2_CTRL_ECDISP 0x0080
  378. #define VC2_CTRL_ECCURS 0x0100
  379. #define VC2_CTRL_ECG64 0x0200
  380. #define VC2_CTRL_GLSEL 0x0400
  381. /* Controlling the color map on NEWPORT. */
  382. #define NCMAP_REGADDR_AREG 0x00000000
  383. #define NCMAP_REGADDR_ALO 0x00000000
  384. #define NCMAP_REGADDR_AHI 0x00000010
  385. #define NCMAP_REGADDR_PBUF 0x00000020
  386. #define NCMAP_REGADDR_CREG 0x00000030
  387. #define NCMAP_REGADDR_SREG 0x00000040
  388. #define NCMAP_REGADDR_RREG 0x00000060
  389. #define NCMAP_PROTOCOL (0x00008000 | 0x00040000 | 0x00800000)
  390. static __inline__ void newport_cmap_setaddr(struct newport_regs *regs,
  391. unsigned short addr)
  392. {
  393. regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
  394. NPORT_DMODE_SENDIAN | NPORT_DMODE_ECINC |
  395. NCMAP_REGADDR_AREG | NPORT_DMODE_W2);
  396. regs->set.dcbdata0.byshort.s1 = addr;
  397. regs->set.dcbmode = (NPORT_DMODE_ACMALL | NCMAP_PROTOCOL |
  398. NCMAP_REGADDR_PBUF | NPORT_DMODE_W3);
  399. }
  400. static __inline__ void newport_cmap_setrgb(struct newport_regs *regs,
  401. unsigned char red,
  402. unsigned char green,
  403. unsigned char blue)
  404. {
  405. regs->set.dcbdata0.byword =
  406. (red << 24) |
  407. (green << 16) |
  408. (blue << 8);
  409. }
  410. /* Miscellaneous NEWPORT routines. */
  411. #define BUSY_TIMEOUT 100000
  412. static __inline__ int newport_wait(struct newport_regs *regs)
  413. {
  414. int t = BUSY_TIMEOUT;
  415. while (t--)
  416. if (!(regs->cset.status & NPORT_STAT_GBUSY))
  417. break;
  418. return !t;
  419. }
  420. static __inline__ int newport_bfwait(struct newport_regs *regs)
  421. {
  422. int t = BUSY_TIMEOUT;
  423. while (t--)
  424. if(!(regs->cset.status & NPORT_STAT_BBUSY))
  425. break;
  426. return !t;
  427. }
  428. /*
  429. * DCBMODE register defines:
  430. */
  431. /* Width of the data being transferred for each DCBDATA[01] word */
  432. #define DCB_DATAWIDTH_4 0x0
  433. #define DCB_DATAWIDTH_1 0x1
  434. #define DCB_DATAWIDTH_2 0x2
  435. #define DCB_DATAWIDTH_3 0x3
  436. /* If set, all of DCBDATA will be moved, otherwise only DATAWIDTH bytes */
  437. #define DCB_ENDATAPACK (1 << 2)
  438. /* Enables DCBCRS auto increment after each DCB transfer */
  439. #define DCB_ENCRSINC (1 << 3)
  440. /* shift for accessing the control register select address (DBCCRS, 3 bits) */
  441. #define DCB_CRS_SHIFT 4
  442. /* DCBADDR (4 bits): display bus slave address */
  443. #define DCB_ADDR_SHIFT 7
  444. #define DCB_VC2 (0 << DCB_ADDR_SHIFT)
  445. #define DCB_CMAP_ALL (1 << DCB_ADDR_SHIFT)
  446. #define DCB_CMAP0 (2 << DCB_ADDR_SHIFT)
  447. #define DCB_CMAP1 (3 << DCB_ADDR_SHIFT)
  448. #define DCB_XMAP_ALL (4 << DCB_ADDR_SHIFT)
  449. #define DCB_XMAP0 (5 << DCB_ADDR_SHIFT)
  450. #define DCB_XMAP1 (6 << DCB_ADDR_SHIFT)
  451. #define DCB_BT445 (7 << DCB_ADDR_SHIFT)
  452. #define DCB_VCC1 (8 << DCB_ADDR_SHIFT)
  453. #define DCB_VAB1 (9 << DCB_ADDR_SHIFT)
  454. #define DCB_LG3_BDVERS0 (10 << DCB_ADDR_SHIFT)
  455. #define DCB_LG3_ICS1562 (11 << DCB_ADDR_SHIFT)
  456. #define DCB_RESERVED (15 << DCB_ADDR_SHIFT)
  457. /* DCB protocol ack types */
  458. #define DCB_ENSYNCACK (1 << 11)
  459. #define DCB_ENASYNCACK (1 << 12)
  460. #define DCB_CSWIDTH_SHIFT 13
  461. #define DCB_CSHOLD_SHIFT 18
  462. #define DCB_CSSETUP_SHIFT 23
  463. /* XMAP9 specific defines */
  464. /* XMAP9 -- registers as seen on the DCBMODE register*/
  465. # define XM9_CRS_CONFIG (0 << DCB_CRS_SHIFT)
  466. # define XM9_PUPMODE (1 << 0)
  467. # define XM9_ODD_PIXEL (1 << 1)
  468. # define XM9_8_BITPLANES (1 << 2)
  469. # define XM9_SLOW_DCB (1 << 3)
  470. # define XM9_VIDEO_RGBMAP_MASK (3 << 4)
  471. # define XM9_EXPRESS_VIDEO (1 << 6)
  472. # define XM9_VIDEO_OPTION (1 << 7)
  473. # define XM9_CRS_REVISION (1 << DCB_CRS_SHIFT)
  474. # define XM9_CRS_FIFO_AVAIL (2 << DCB_CRS_SHIFT)
  475. # define XM9_FIFO_0_AVAIL 0
  476. # define XM9_FIFO_1_AVAIL 1
  477. # define XM9_FIFO_2_AVAIL 3
  478. # define XM9_FIFO_3_AVAIL 2
  479. # define XM9_FIFO_FULL XM9_FIFO_0_AVAIL
  480. # define XM9_FIFO_EMPTY XM9_FIFO_3_AVAIL
  481. # define XM9_CRS_CURS_CMAP_MSB (3 << DCB_CRS_SHIFT)
  482. # define XM9_CRS_PUP_CMAP_MSB (4 << DCB_CRS_SHIFT)
  483. # define XM9_CRS_MODE_REG_DATA (5 << DCB_CRS_SHIFT)
  484. # define XM9_CRS_MODE_REG_INDEX (7 << DCB_CRS_SHIFT)
  485. #define DCB_CYCLES(setup,hold,width) \
  486. ((hold << DCB_CSHOLD_SHIFT) | \
  487. (setup << DCB_CSSETUP_SHIFT)| \
  488. (width << DCB_CSWIDTH_SHIFT))
  489. #define W_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 0)
  490. #define WSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (5, 5, 0)
  491. #define WAYSLOW_DCB_XMAP9_PROTOCOL DCB_CYCLES (12, 12, 0)
  492. #define R_DCB_XMAP9_PROTOCOL DCB_CYCLES (2, 1, 3)
  493. static __inline__ void
  494. xmap9FIFOWait (struct newport_regs *rex)
  495. {
  496. rex->set.dcbmode = DCB_XMAP0 | XM9_CRS_FIFO_AVAIL |
  497. DCB_DATAWIDTH_1 | R_DCB_XMAP9_PROTOCOL;
  498. newport_bfwait (rex);
  499. while ((rex->set.dcbdata0.bybytes.b3 & 3) != XM9_FIFO_EMPTY)
  500. ;
  501. }
  502. static __inline__ void
  503. xmap9SetModeReg (struct newport_regs *rex, unsigned int modereg, unsigned int data24, int cfreq)
  504. {
  505. if (cfreq > 119)
  506. rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
  507. DCB_DATAWIDTH_4 | W_DCB_XMAP9_PROTOCOL;
  508. else if (cfreq > 59)
  509. rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
  510. DCB_DATAWIDTH_4 | WSLOW_DCB_XMAP9_PROTOCOL;
  511. else
  512. rex->set.dcbmode = DCB_XMAP_ALL | XM9_CRS_MODE_REG_DATA |
  513. DCB_DATAWIDTH_4 | WAYSLOW_DCB_XMAP9_PROTOCOL;
  514. rex->set.dcbdata0.byword = ((modereg) << 24) | (data24 & 0xffffff);
  515. }
  516. #define BT445_PROTOCOL DCB_CYCLES(1,1,3)
  517. #define BT445_CSR_ADDR_REG (0 << DCB_CRS_SHIFT)
  518. #define BT445_CSR_REVISION (2 << DCB_CRS_SHIFT)
  519. #define BT445_REVISION_REG 0x01
  520. #endif /* !(_SGI_NEWPORT_H) */