mach64.h 47 KB

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  1. /*
  2. * ATI Mach64 Register Definitions
  3. *
  4. * Copyright (C) 1997 Michael AK Tesch
  5. * written with much help from Jon Howell
  6. *
  7. * Updated for 3D RAGE PRO and 3D RAGE Mobility by Geert Uytterhoeven
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. /*
  15. * most of the rest of this file comes from ATI sample code
  16. */
  17. #ifndef REGMACH64_H
  18. #define REGMACH64_H
  19. /* NON-GUI MEMORY MAPPED Registers - expressed in BYTE offsets */
  20. /* Accelerator CRTC */
  21. #define CRTC_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
  22. #define CRTC2_H_TOTAL_DISP 0x0000 /* Dword offset 0_00 */
  23. #define CRTC_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
  24. #define CRTC2_H_SYNC_STRT_WID 0x0004 /* Dword offset 0_01 */
  25. #define CRTC_H_SYNC_STRT 0x0004
  26. #define CRTC2_H_SYNC_STRT 0x0004
  27. #define CRTC_H_SYNC_DLY 0x0005
  28. #define CRTC2_H_SYNC_DLY 0x0005
  29. #define CRTC_H_SYNC_WID 0x0006
  30. #define CRTC2_H_SYNC_WID 0x0006
  31. #define CRTC_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
  32. #define CRTC2_V_TOTAL_DISP 0x0008 /* Dword offset 0_02 */
  33. #define CRTC_V_TOTAL 0x0008
  34. #define CRTC2_V_TOTAL 0x0008
  35. #define CRTC_V_DISP 0x000A
  36. #define CRTC2_V_DISP 0x000A
  37. #define CRTC_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
  38. #define CRTC2_V_SYNC_STRT_WID 0x000C /* Dword offset 0_03 */
  39. #define CRTC_V_SYNC_STRT 0x000C
  40. #define CRTC2_V_SYNC_STRT 0x000C
  41. #define CRTC_V_SYNC_WID 0x000E
  42. #define CRTC2_V_SYNC_WID 0x000E
  43. #define CRTC_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
  44. #define CRTC2_VLINE_CRNT_VLINE 0x0010 /* Dword offset 0_04 */
  45. #define CRTC_OFF_PITCH 0x0014 /* Dword offset 0_05 */
  46. #define CRTC_OFFSET 0x0014
  47. #define CRTC_PITCH 0x0016
  48. #define CRTC_INT_CNTL 0x0018 /* Dword offset 0_06 */
  49. #define CRTC_GEN_CNTL 0x001C /* Dword offset 0_07 */
  50. #define CRTC_PIX_WIDTH 0x001D
  51. #define CRTC_FIFO 0x001E
  52. #define CRTC_EXT_DISP 0x001F
  53. /* Memory Buffer Control */
  54. #define DSP_CONFIG 0x0020 /* Dword offset 0_08 */
  55. #define PM_DSP_CONFIG 0x0020 /* Dword offset 0_08 (Mobility Only) */
  56. #define DSP_ON_OFF 0x0024 /* Dword offset 0_09 */
  57. #define PM_DSP_ON_OFF 0x0024 /* Dword offset 0_09 (Mobility Only) */
  58. #define TIMER_CONFIG 0x0028 /* Dword offset 0_0A */
  59. #define MEM_BUF_CNTL 0x002C /* Dword offset 0_0B */
  60. #define MEM_ADDR_CONFIG 0x0034 /* Dword offset 0_0D */
  61. /* Accelerator CRTC */
  62. #define CRT_TRAP 0x0038 /* Dword offset 0_0E */
  63. #define I2C_CNTL_0 0x003C /* Dword offset 0_0F */
  64. #define DSTN_CONTROL_LG 0x003C /* Dword offset 0_0F (LG) */
  65. /* Overscan */
  66. #define OVR_CLR 0x0040 /* Dword offset 0_10 */
  67. #define OVR2_CLR 0x0040 /* Dword offset 0_10 */
  68. #define OVR_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
  69. #define OVR2_WID_LEFT_RIGHT 0x0044 /* Dword offset 0_11 */
  70. #define OVR_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
  71. #define OVR2_WID_TOP_BOTTOM 0x0048 /* Dword offset 0_12 */
  72. /* Memory Buffer Control */
  73. #define VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 */
  74. #define PM_VGA_DSP_CONFIG 0x004C /* Dword offset 0_13 (Mobility Only) */
  75. #define VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 */
  76. #define PM_VGA_DSP_ON_OFF 0x0050 /* Dword offset 0_14 (Mobility Only) */
  77. #define DSP2_CONFIG 0x0054 /* Dword offset 0_15 */
  78. #define PM_DSP2_CONFIG 0x0054 /* Dword offset 0_15 (Mobility Only) */
  79. #define DSP2_ON_OFF 0x0058 /* Dword offset 0_16 */
  80. #define PM_DSP2_ON_OFF 0x0058 /* Dword offset 0_16 (Mobility Only) */
  81. /* Accelerator CRTC */
  82. #define CRTC2_OFF_PITCH 0x005C /* Dword offset 0_17 */
  83. /* Hardware Cursor */
  84. #define CUR_CLR0 0x0060 /* Dword offset 0_18 */
  85. #define CUR2_CLR0 0x0060 /* Dword offset 0_18 */
  86. #define CUR_CLR1 0x0064 /* Dword offset 0_19 */
  87. #define CUR2_CLR1 0x0064 /* Dword offset 0_19 */
  88. #define CUR_OFFSET 0x0068 /* Dword offset 0_1A */
  89. #define CUR2_OFFSET 0x0068 /* Dword offset 0_1A */
  90. #define CUR_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
  91. #define CUR2_HORZ_VERT_POSN 0x006C /* Dword offset 0_1B */
  92. #define CUR_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
  93. #define CUR2_HORZ_VERT_OFF 0x0070 /* Dword offset 0_1C */
  94. #define CONFIG_PANEL_LG 0x0074 /* Dword offset 0_1D (LG) */
  95. /* General I/O Control */
  96. #define GP_IO 0x0078 /* Dword offset 0_1E */
  97. /* Test and Debug */
  98. #define HW_DEBUG 0x007C /* Dword offset 0_1F */
  99. /* Scratch Pad and Test */
  100. #define SCRATCH_REG0 0x0080 /* Dword offset 0_20 */
  101. #define SCRATCH_REG1 0x0084 /* Dword offset 0_21 */
  102. #define SCRATCH_REG2 0x0088 /* Dword offset 0_22 */
  103. #define SCRATCH_REG3 0x008C /* Dword offset 0_23 */
  104. /* Clock Control */
  105. #define CLOCK_CNTL 0x0090 /* Dword offset 0_24 */
  106. /* CLOCK_CNTL register constants CT LAYOUT */
  107. #define CLOCK_SEL 0x0f
  108. #define CLOCK_SEL_INTERNAL 0x03
  109. #define CLOCK_SEL_EXTERNAL 0x0c
  110. #define CLOCK_DIV 0x30
  111. #define CLOCK_DIV1 0x00
  112. #define CLOCK_DIV2 0x10
  113. #define CLOCK_DIV4 0x20
  114. #define CLOCK_STROBE 0x40
  115. /* ? 0x80 */
  116. /* CLOCK_CNTL register constants GX LAYOUT */
  117. #define CLOCK_BIT 0x04 /* For ICS2595 */
  118. #define CLOCK_PULSE 0x08 /* For ICS2595 */
  119. /*#define CLOCK_STROBE 0x40 dito as CT */
  120. #define CLOCK_DATA 0x80
  121. /* For internal PLL(CT) start */
  122. #define CLOCK_CNTL_ADDR CLOCK_CNTL + 1
  123. #define PLL_WR_EN 0x02
  124. #define PLL_ADDR 0xfc
  125. #define CLOCK_CNTL_DATA CLOCK_CNTL + 2
  126. #define PLL_DATA 0xff
  127. /* For internal PLL(CT) end */
  128. #define CLOCK_SEL_CNTL 0x0090 /* Dword offset 0_24 */
  129. /* Configuration */
  130. #define CONFIG_STAT1 0x0094 /* Dword offset 0_25 */
  131. #define CONFIG_STAT2 0x0098 /* Dword offset 0_26 */
  132. /* Bus Control */
  133. #define BUS_CNTL 0x00A0 /* Dword offset 0_28 */
  134. #define LCD_INDEX 0x00A4 /* Dword offset 0_29 */
  135. #define LCD_DATA 0x00A8 /* Dword offset 0_2A */
  136. #define HFB_PITCH_ADDR_LG 0x00A8 /* Dword offset 0_2A (LG) */
  137. /* Memory Control */
  138. #define EXT_MEM_CNTL 0x00AC /* Dword offset 0_2B */
  139. #define MEM_CNTL 0x00B0 /* Dword offset 0_2C */
  140. #define MEM_VGA_WP_SEL 0x00B4 /* Dword offset 0_2D */
  141. #define MEM_VGA_RP_SEL 0x00B8 /* Dword offset 0_2E */
  142. #define I2C_CNTL_1 0x00BC /* Dword offset 0_2F */
  143. #define LT_GIO_LG 0x00BC /* Dword offset 0_2F (LG) */
  144. /* DAC Control */
  145. #define DAC_REGS 0x00C0 /* Dword offset 0_30 */
  146. #define DAC_W_INDEX 0x00C0 /* Dword offset 0_30 */
  147. #define DAC_DATA 0x00C1 /* Dword offset 0_30 */
  148. #define DAC_MASK 0x00C2 /* Dword offset 0_30 */
  149. #define DAC_R_INDEX 0x00C3 /* Dword offset 0_30 */
  150. #define DAC_CNTL 0x00C4 /* Dword offset 0_31 */
  151. #define EXT_DAC_REGS 0x00C8 /* Dword offset 0_32 */
  152. #define HORZ_STRETCHING_LG 0x00C8 /* Dword offset 0_32 (LG) */
  153. #define VERT_STRETCHING_LG 0x00CC /* Dword offset 0_33 (LG) */
  154. /* Test and Debug */
  155. #define GEN_TEST_CNTL 0x00D0 /* Dword offset 0_34 */
  156. /* Custom Macros */
  157. #define CUSTOM_MACRO_CNTL 0x00D4 /* Dword offset 0_35 */
  158. #define LCD_GEN_CNTL_LG 0x00D4 /* Dword offset 0_35 (LG) */
  159. #define POWER_MANAGEMENT_LG 0x00D8 /* Dword offset 0_36 (LG) */
  160. /* Configuration */
  161. #define CONFIG_CNTL 0x00DC /* Dword offset 0_37 (CT, ET, VT) */
  162. #define CONFIG_CHIP_ID 0x00E0 /* Dword offset 0_38 */
  163. #define CONFIG_STAT0 0x00E4 /* Dword offset 0_39 */
  164. /* Test and Debug */
  165. #define CRC_SIG 0x00E8 /* Dword offset 0_3A */
  166. #define CRC2_SIG 0x00E8 /* Dword offset 0_3A */
  167. /* GUI MEMORY MAPPED Registers */
  168. /* Draw Engine Destination Trajectory */
  169. #define DST_OFF_PITCH 0x0100 /* Dword offset 0_40 */
  170. #define DST_X 0x0104 /* Dword offset 0_41 */
  171. #define DST_Y 0x0108 /* Dword offset 0_42 */
  172. #define DST_Y_X 0x010C /* Dword offset 0_43 */
  173. #define DST_WIDTH 0x0110 /* Dword offset 0_44 */
  174. #define DST_HEIGHT 0x0114 /* Dword offset 0_45 */
  175. #define DST_HEIGHT_WIDTH 0x0118 /* Dword offset 0_46 */
  176. #define DST_X_WIDTH 0x011C /* Dword offset 0_47 */
  177. #define DST_BRES_LNTH 0x0120 /* Dword offset 0_48 */
  178. #define DST_BRES_ERR 0x0124 /* Dword offset 0_49 */
  179. #define DST_BRES_INC 0x0128 /* Dword offset 0_4A */
  180. #define DST_BRES_DEC 0x012C /* Dword offset 0_4B */
  181. #define DST_CNTL 0x0130 /* Dword offset 0_4C */
  182. #define DST_Y_X__ALIAS__ 0x0134 /* Dword offset 0_4D */
  183. #define TRAIL_BRES_ERR 0x0138 /* Dword offset 0_4E */
  184. #define TRAIL_BRES_INC 0x013C /* Dword offset 0_4F */
  185. #define TRAIL_BRES_DEC 0x0140 /* Dword offset 0_50 */
  186. #define LEAD_BRES_LNTH 0x0144 /* Dword offset 0_51 */
  187. #define Z_OFF_PITCH 0x0148 /* Dword offset 0_52 */
  188. #define Z_CNTL 0x014C /* Dword offset 0_53 */
  189. #define ALPHA_TST_CNTL 0x0150 /* Dword offset 0_54 */
  190. #define SECONDARY_STW_EXP 0x0158 /* Dword offset 0_56 */
  191. #define SECONDARY_S_X_INC 0x015C /* Dword offset 0_57 */
  192. #define SECONDARY_S_Y_INC 0x0160 /* Dword offset 0_58 */
  193. #define SECONDARY_S_START 0x0164 /* Dword offset 0_59 */
  194. #define SECONDARY_W_X_INC 0x0168 /* Dword offset 0_5A */
  195. #define SECONDARY_W_Y_INC 0x016C /* Dword offset 0_5B */
  196. #define SECONDARY_W_START 0x0170 /* Dword offset 0_5C */
  197. #define SECONDARY_T_X_INC 0x0174 /* Dword offset 0_5D */
  198. #define SECONDARY_T_Y_INC 0x0178 /* Dword offset 0_5E */
  199. #define SECONDARY_T_START 0x017C /* Dword offset 0_5F */
  200. /* Draw Engine Source Trajectory */
  201. #define SRC_OFF_PITCH 0x0180 /* Dword offset 0_60 */
  202. #define SRC_X 0x0184 /* Dword offset 0_61 */
  203. #define SRC_Y 0x0188 /* Dword offset 0_62 */
  204. #define SRC_Y_X 0x018C /* Dword offset 0_63 */
  205. #define SRC_WIDTH1 0x0190 /* Dword offset 0_64 */
  206. #define SRC_HEIGHT1 0x0194 /* Dword offset 0_65 */
  207. #define SRC_HEIGHT1_WIDTH1 0x0198 /* Dword offset 0_66 */
  208. #define SRC_X_START 0x019C /* Dword offset 0_67 */
  209. #define SRC_Y_START 0x01A0 /* Dword offset 0_68 */
  210. #define SRC_Y_X_START 0x01A4 /* Dword offset 0_69 */
  211. #define SRC_WIDTH2 0x01A8 /* Dword offset 0_6A */
  212. #define SRC_HEIGHT2 0x01AC /* Dword offset 0_6B */
  213. #define SRC_HEIGHT2_WIDTH2 0x01B0 /* Dword offset 0_6C */
  214. #define SRC_CNTL 0x01B4 /* Dword offset 0_6D */
  215. #define SCALE_OFF 0x01C0 /* Dword offset 0_70 */
  216. #define SECONDARY_SCALE_OFF 0x01C4 /* Dword offset 0_71 */
  217. #define TEX_0_OFF 0x01C0 /* Dword offset 0_70 */
  218. #define TEX_1_OFF 0x01C4 /* Dword offset 0_71 */
  219. #define TEX_2_OFF 0x01C8 /* Dword offset 0_72 */
  220. #define TEX_3_OFF 0x01CC /* Dword offset 0_73 */
  221. #define TEX_4_OFF 0x01D0 /* Dword offset 0_74 */
  222. #define TEX_5_OFF 0x01D4 /* Dword offset 0_75 */
  223. #define TEX_6_OFF 0x01D8 /* Dword offset 0_76 */
  224. #define TEX_7_OFF 0x01DC /* Dword offset 0_77 */
  225. #define SCALE_WIDTH 0x01DC /* Dword offset 0_77 */
  226. #define SCALE_HEIGHT 0x01E0 /* Dword offset 0_78 */
  227. #define TEX_8_OFF 0x01E0 /* Dword offset 0_78 */
  228. #define TEX_9_OFF 0x01E4 /* Dword offset 0_79 */
  229. #define TEX_10_OFF 0x01E8 /* Dword offset 0_7A */
  230. #define S_Y_INC 0x01EC /* Dword offset 0_7B */
  231. #define SCALE_PITCH 0x01EC /* Dword offset 0_7B */
  232. #define SCALE_X_INC 0x01F0 /* Dword offset 0_7C */
  233. #define RED_X_INC 0x01F0 /* Dword offset 0_7C */
  234. #define GREEN_X_INC 0x01F4 /* Dword offset 0_7D */
  235. #define SCALE_Y_INC 0x01F4 /* Dword offset 0_7D */
  236. #define SCALE_VACC 0x01F8 /* Dword offset 0_7E */
  237. #define SCALE_3D_CNTL 0x01FC /* Dword offset 0_7F */
  238. /* Host Data */
  239. #define HOST_DATA0 0x0200 /* Dword offset 0_80 */
  240. #define HOST_DATA1 0x0204 /* Dword offset 0_81 */
  241. #define HOST_DATA2 0x0208 /* Dword offset 0_82 */
  242. #define HOST_DATA3 0x020C /* Dword offset 0_83 */
  243. #define HOST_DATA4 0x0210 /* Dword offset 0_84 */
  244. #define HOST_DATA5 0x0214 /* Dword offset 0_85 */
  245. #define HOST_DATA6 0x0218 /* Dword offset 0_86 */
  246. #define HOST_DATA7 0x021C /* Dword offset 0_87 */
  247. #define HOST_DATA8 0x0220 /* Dword offset 0_88 */
  248. #define HOST_DATA9 0x0224 /* Dword offset 0_89 */
  249. #define HOST_DATAA 0x0228 /* Dword offset 0_8A */
  250. #define HOST_DATAB 0x022C /* Dword offset 0_8B */
  251. #define HOST_DATAC 0x0230 /* Dword offset 0_8C */
  252. #define HOST_DATAD 0x0234 /* Dword offset 0_8D */
  253. #define HOST_DATAE 0x0238 /* Dword offset 0_8E */
  254. #define HOST_DATAF 0x023C /* Dword offset 0_8F */
  255. #define HOST_CNTL 0x0240 /* Dword offset 0_90 */
  256. /* GUI Bus Mastering */
  257. #define BM_HOSTDATA 0x0244 /* Dword offset 0_91 */
  258. #define BM_ADDR 0x0248 /* Dword offset 0_92 */
  259. #define BM_DATA 0x0248 /* Dword offset 0_92 */
  260. #define BM_GUI_TABLE_CMD 0x024C /* Dword offset 0_93 */
  261. /* Pattern */
  262. #define PAT_REG0 0x0280 /* Dword offset 0_A0 */
  263. #define PAT_REG1 0x0284 /* Dword offset 0_A1 */
  264. #define PAT_CNTL 0x0288 /* Dword offset 0_A2 */
  265. /* Scissors */
  266. #define SC_LEFT 0x02A0 /* Dword offset 0_A8 */
  267. #define SC_RIGHT 0x02A4 /* Dword offset 0_A9 */
  268. #define SC_LEFT_RIGHT 0x02A8 /* Dword offset 0_AA */
  269. #define SC_TOP 0x02AC /* Dword offset 0_AB */
  270. #define SC_BOTTOM 0x02B0 /* Dword offset 0_AC */
  271. #define SC_TOP_BOTTOM 0x02B4 /* Dword offset 0_AD */
  272. /* Data Path */
  273. #define USR1_DST_OFF_PITCH 0x02B8 /* Dword offset 0_AE */
  274. #define USR2_DST_OFF_PITCH 0x02BC /* Dword offset 0_AF */
  275. #define DP_BKGD_CLR 0x02C0 /* Dword offset 0_B0 */
  276. #define DP_FOG_CLR 0x02C4 /* Dword offset 0_B1 */
  277. #define DP_FRGD_CLR 0x02C4 /* Dword offset 0_B1 */
  278. #define DP_WRITE_MASK 0x02C8 /* Dword offset 0_B2 */
  279. #define DP_CHAIN_MASK 0x02CC /* Dword offset 0_B3 */
  280. #define DP_PIX_WIDTH 0x02D0 /* Dword offset 0_B4 */
  281. #define DP_MIX 0x02D4 /* Dword offset 0_B5 */
  282. #define DP_SRC 0x02D8 /* Dword offset 0_B6 */
  283. #define DP_FRGD_CLR_MIX 0x02DC /* Dword offset 0_B7 */
  284. #define DP_FRGD_BKGD_CLR 0x02E0 /* Dword offset 0_B8 */
  285. /* Draw Engine Destination Trajectory */
  286. #define DST_X_Y 0x02E8 /* Dword offset 0_BA */
  287. #define DST_WIDTH_HEIGHT 0x02EC /* Dword offset 0_BB */
  288. /* Data Path */
  289. #define USR_DST_PICTH 0x02F0 /* Dword offset 0_BC */
  290. #define DP_SET_GUI_ENGINE2 0x02F8 /* Dword offset 0_BE */
  291. #define DP_SET_GUI_ENGINE 0x02FC /* Dword offset 0_BF */
  292. /* Color Compare */
  293. #define CLR_CMP_CLR 0x0300 /* Dword offset 0_C0 */
  294. #define CLR_CMP_MASK 0x0304 /* Dword offset 0_C1 */
  295. #define CLR_CMP_CNTL 0x0308 /* Dword offset 0_C2 */
  296. /* Command FIFO */
  297. #define FIFO_STAT 0x0310 /* Dword offset 0_C4 */
  298. #define CONTEXT_MASK 0x0320 /* Dword offset 0_C8 */
  299. #define CONTEXT_LOAD_CNTL 0x032C /* Dword offset 0_CB */
  300. /* Engine Control */
  301. #define GUI_TRAJ_CNTL 0x0330 /* Dword offset 0_CC */
  302. /* Engine Status/FIFO */
  303. #define GUI_STAT 0x0338 /* Dword offset 0_CE */
  304. #define TEX_PALETTE_INDEX 0x0340 /* Dword offset 0_D0 */
  305. #define STW_EXP 0x0344 /* Dword offset 0_D1 */
  306. #define LOG_MAX_INC 0x0348 /* Dword offset 0_D2 */
  307. #define S_X_INC 0x034C /* Dword offset 0_D3 */
  308. #define S_Y_INC__ALIAS__ 0x0350 /* Dword offset 0_D4 */
  309. #define SCALE_PITCH__ALIAS__ 0x0350 /* Dword offset 0_D4 */
  310. #define S_START 0x0354 /* Dword offset 0_D5 */
  311. #define W_X_INC 0x0358 /* Dword offset 0_D6 */
  312. #define W_Y_INC 0x035C /* Dword offset 0_D7 */
  313. #define W_START 0x0360 /* Dword offset 0_D8 */
  314. #define T_X_INC 0x0364 /* Dword offset 0_D9 */
  315. #define T_Y_INC 0x0368 /* Dword offset 0_DA */
  316. #define SECONDARY_SCALE_PITCH 0x0368 /* Dword offset 0_DA */
  317. #define T_START 0x036C /* Dword offset 0_DB */
  318. #define TEX_SIZE_PITCH 0x0370 /* Dword offset 0_DC */
  319. #define TEX_CNTL 0x0374 /* Dword offset 0_DD */
  320. #define SECONDARY_TEX_OFFSET 0x0378 /* Dword offset 0_DE */
  321. #define TEX_PALETTE 0x037C /* Dword offset 0_DF */
  322. #define SCALE_PITCH_BOTH 0x0380 /* Dword offset 0_E0 */
  323. #define SECONDARY_SCALE_OFF_ACC 0x0384 /* Dword offset 0_E1 */
  324. #define SCALE_OFF_ACC 0x0388 /* Dword offset 0_E2 */
  325. #define SCALE_DST_Y_X 0x038C /* Dword offset 0_E3 */
  326. /* Draw Engine Destination Trajectory */
  327. #define COMPOSITE_SHADOW_ID 0x0398 /* Dword offset 0_E6 */
  328. #define SECONDARY_SCALE_X_INC 0x039C /* Dword offset 0_E7 */
  329. #define SPECULAR_RED_X_INC 0x039C /* Dword offset 0_E7 */
  330. #define SPECULAR_RED_Y_INC 0x03A0 /* Dword offset 0_E8 */
  331. #define SPECULAR_RED_START 0x03A4 /* Dword offset 0_E9 */
  332. #define SECONDARY_SCALE_HACC 0x03A4 /* Dword offset 0_E9 */
  333. #define SPECULAR_GREEN_X_INC 0x03A8 /* Dword offset 0_EA */
  334. #define SPECULAR_GREEN_Y_INC 0x03AC /* Dword offset 0_EB */
  335. #define SPECULAR_GREEN_START 0x03B0 /* Dword offset 0_EC */
  336. #define SPECULAR_BLUE_X_INC 0x03B4 /* Dword offset 0_ED */
  337. #define SPECULAR_BLUE_Y_INC 0x03B8 /* Dword offset 0_EE */
  338. #define SPECULAR_BLUE_START 0x03BC /* Dword offset 0_EF */
  339. #define SCALE_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
  340. #define RED_X_INC__ALIAS__ 0x03C0 /* Dword offset 0_F0 */
  341. #define RED_Y_INC 0x03C4 /* Dword offset 0_F1 */
  342. #define RED_START 0x03C8 /* Dword offset 0_F2 */
  343. #define SCALE_HACC 0x03C8 /* Dword offset 0_F2 */
  344. #define SCALE_Y_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
  345. #define GREEN_X_INC__ALIAS__ 0x03CC /* Dword offset 0_F3 */
  346. #define GREEN_Y_INC 0x03D0 /* Dword offset 0_F4 */
  347. #define SECONDARY_SCALE_Y_INC 0x03D0 /* Dword offset 0_F4 */
  348. #define SECONDARY_SCALE_VACC 0x03D4 /* Dword offset 0_F5 */
  349. #define GREEN_START 0x03D4 /* Dword offset 0_F5 */
  350. #define BLUE_X_INC 0x03D8 /* Dword offset 0_F6 */
  351. #define BLUE_Y_INC 0x03DC /* Dword offset 0_F7 */
  352. #define BLUE_START 0x03E0 /* Dword offset 0_F8 */
  353. #define Z_X_INC 0x03E4 /* Dword offset 0_F9 */
  354. #define Z_Y_INC 0x03E8 /* Dword offset 0_FA */
  355. #define Z_START 0x03EC /* Dword offset 0_FB */
  356. #define ALPHA_X_INC 0x03F0 /* Dword offset 0_FC */
  357. #define FOG_X_INC 0x03F0 /* Dword offset 0_FC */
  358. #define ALPHA_Y_INC 0x03F4 /* Dword offset 0_FD */
  359. #define FOG_Y_INC 0x03F4 /* Dword offset 0_FD */
  360. #define ALPHA_START 0x03F8 /* Dword offset 0_FE */
  361. #define FOG_START 0x03F8 /* Dword offset 0_FE */
  362. #define OVERLAY_Y_X_START 0x0400 /* Dword offset 1_00 */
  363. #define OVERLAY_Y_X_END 0x0404 /* Dword offset 1_01 */
  364. #define OVERLAY_VIDEO_KEY_CLR 0x0408 /* Dword offset 1_02 */
  365. #define OVERLAY_VIDEO_KEY_MSK 0x040C /* Dword offset 1_03 */
  366. #define OVERLAY_GRAPHICS_KEY_CLR 0x0410 /* Dword offset 1_04 */
  367. #define OVERLAY_GRAPHICS_KEY_MSK 0x0414 /* Dword offset 1_05 */
  368. #define OVERLAY_KEY_CNTL 0x0418 /* Dword offset 1_06 */
  369. #define OVERLAY_SCALE_INC 0x0420 /* Dword offset 1_08 */
  370. #define OVERLAY_SCALE_CNTL 0x0424 /* Dword offset 1_09 */
  371. #define SCALER_HEIGHT_WIDTH 0x0428 /* Dword offset 1_0A */
  372. #define SCALER_TEST 0x042C /* Dword offset 1_0B */
  373. #define SCALER_BUF0_OFFSET 0x0434 /* Dword offset 1_0D */
  374. #define SCALER_BUF1_OFFSET 0x0438 /* Dword offset 1_0E */
  375. #define SCALE_BUF_PITCH 0x043C /* Dword offset 1_0F */
  376. #define CAPTURE_START_END 0x0440 /* Dword offset 1_10 */
  377. #define CAPTURE_X_WIDTH 0x0444 /* Dword offset 1_11 */
  378. #define VIDEO_FORMAT 0x0448 /* Dword offset 1_12 */
  379. #define VBI_START_END 0x044C /* Dword offset 1_13 */
  380. #define CAPTURE_CONFIG 0x0450 /* Dword offset 1_14 */
  381. #define TRIG_CNTL 0x0454 /* Dword offset 1_15 */
  382. #define OVERLAY_EXCLUSIVE_HORZ 0x0458 /* Dword offset 1_16 */
  383. #define OVERLAY_EXCLUSIVE_VERT 0x045C /* Dword offset 1_17 */
  384. #define VAL_WIDTH 0x0460 /* Dword offset 1_18 */
  385. #define CAPTURE_DEBUG 0x0464 /* Dword offset 1_19 */
  386. #define VIDEO_SYNC_TEST 0x0468 /* Dword offset 1_1A */
  387. /* GenLocking */
  388. #define SNAPSHOT_VH_COUNTS 0x0470 /* Dword offset 1_1C */
  389. #define SNAPSHOT_F_COUNT 0x0474 /* Dword offset 1_1D */
  390. #define N_VIF_COUNT 0x0478 /* Dword offset 1_1E */
  391. #define SNAPSHOT_VIF_COUNT 0x047C /* Dword offset 1_1F */
  392. #define CAPTURE_BUF0_OFFSET 0x0480 /* Dword offset 1_20 */
  393. #define CAPTURE_BUF1_OFFSET 0x0484 /* Dword offset 1_21 */
  394. #define CAPTURE_BUF_PITCH 0x0488 /* Dword offset 1_22 */
  395. /* GenLocking */
  396. #define SNAPSHOT2_VH_COUNTS 0x04B0 /* Dword offset 1_2C */
  397. #define SNAPSHOT2_F_COUNT 0x04B4 /* Dword offset 1_2D */
  398. #define N_VIF2_COUNT 0x04B8 /* Dword offset 1_2E */
  399. #define SNAPSHOT2_VIF_COUNT 0x04BC /* Dword offset 1_2F */
  400. #define MPP_CONFIG 0x04C0 /* Dword offset 1_30 */
  401. #define MPP_STROBE_SEQ 0x04C4 /* Dword offset 1_31 */
  402. #define MPP_ADDR 0x04C8 /* Dword offset 1_32 */
  403. #define MPP_DATA 0x04CC /* Dword offset 1_33 */
  404. #define TVO_CNTL 0x0500 /* Dword offset 1_40 */
  405. /* Test and Debug */
  406. #define CRT_HORZ_VERT_LOAD 0x0544 /* Dword offset 1_51 */
  407. /* AGP */
  408. #define AGP_BASE 0x0548 /* Dword offset 1_52 */
  409. #define AGP_CNTL 0x054C /* Dword offset 1_53 */
  410. #define SCALER_COLOUR_CNTL 0x0550 /* Dword offset 1_54 */
  411. #define SCALER_H_COEFF0 0x0554 /* Dword offset 1_55 */
  412. #define SCALER_H_COEFF1 0x0558 /* Dword offset 1_56 */
  413. #define SCALER_H_COEFF2 0x055C /* Dword offset 1_57 */
  414. #define SCALER_H_COEFF3 0x0560 /* Dword offset 1_58 */
  415. #define SCALER_H_COEFF4 0x0564 /* Dword offset 1_59 */
  416. /* Command FIFO */
  417. #define GUI_CMDFIFO_DEBUG 0x0570 /* Dword offset 1_5C */
  418. #define GUI_CMDFIFO_DATA 0x0574 /* Dword offset 1_5D */
  419. #define GUI_CNTL 0x0578 /* Dword offset 1_5E */
  420. /* Bus Mastering */
  421. #define BM_FRAME_BUF_OFFSET 0x0580 /* Dword offset 1_60 */
  422. #define BM_SYSTEM_MEM_ADDR 0x0584 /* Dword offset 1_61 */
  423. #define BM_COMMAND 0x0588 /* Dword offset 1_62 */
  424. #define BM_STATUS 0x058C /* Dword offset 1_63 */
  425. #define BM_GUI_TABLE 0x05B8 /* Dword offset 1_6E */
  426. #define BM_SYSTEM_TABLE 0x05BC /* Dword offset 1_6F */
  427. #define SCALER_BUF0_OFFSET_U 0x05D4 /* Dword offset 1_75 */
  428. #define SCALER_BUF0_OFFSET_V 0x05D8 /* Dword offset 1_76 */
  429. #define SCALER_BUF1_OFFSET_U 0x05DC /* Dword offset 1_77 */
  430. #define SCALER_BUF1_OFFSET_V 0x05E0 /* Dword offset 1_78 */
  431. /* Setup Engine */
  432. #define VERTEX_1_S 0x0640 /* Dword offset 1_90 */
  433. #define VERTEX_1_T 0x0644 /* Dword offset 1_91 */
  434. #define VERTEX_1_W 0x0648 /* Dword offset 1_92 */
  435. #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_93 */
  436. #define VERTEX_1_Z 0x0650 /* Dword offset 1_94 */
  437. #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_95 */
  438. #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_96 */
  439. #define ONE_OVER_AREA 0x065C /* Dword offset 1_97 */
  440. #define VERTEX_2_S 0x0660 /* Dword offset 1_98 */
  441. #define VERTEX_2_T 0x0664 /* Dword offset 1_99 */
  442. #define VERTEX_2_W 0x0668 /* Dword offset 1_9A */
  443. #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_9B */
  444. #define VERTEX_2_Z 0x0670 /* Dword offset 1_9C */
  445. #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_9D */
  446. #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_9E */
  447. #define ONE_OVER_AREA 0x065C /* Dword offset 1_9F */
  448. #define VERTEX_3_S 0x0680 /* Dword offset 1_A0 */
  449. #define VERTEX_3_T 0x0684 /* Dword offset 1_A1 */
  450. #define VERTEX_3_W 0x0688 /* Dword offset 1_A2 */
  451. #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_A3 */
  452. #define VERTEX_3_Z 0x0690 /* Dword offset 1_A4 */
  453. #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_A5 */
  454. #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_A6 */
  455. #define ONE_OVER_AREA 0x065C /* Dword offset 1_A7 */
  456. #define VERTEX_1_S 0x0640 /* Dword offset 1_AB */
  457. #define VERTEX_1_T 0x0644 /* Dword offset 1_AC */
  458. #define VERTEX_1_W 0x0648 /* Dword offset 1_AD */
  459. #define VERTEX_2_S 0x0660 /* Dword offset 1_AE */
  460. #define VERTEX_2_T 0x0664 /* Dword offset 1_AF */
  461. #define VERTEX_2_W 0x0668 /* Dword offset 1_B0 */
  462. #define VERTEX_3_SECONDARY_S 0x06C0 /* Dword offset 1_B0 */
  463. #define VERTEX_3_S 0x0680 /* Dword offset 1_B1 */
  464. #define VERTEX_3_SECONDARY_T 0x06C4 /* Dword offset 1_B1 */
  465. #define VERTEX_3_T 0x0684 /* Dword offset 1_B2 */
  466. #define VERTEX_3_SECONDARY_W 0x06C8 /* Dword offset 1_B2 */
  467. #define VERTEX_3_W 0x0688 /* Dword offset 1_B3 */
  468. #define VERTEX_1_SPEC_ARGB 0x064C /* Dword offset 1_B4 */
  469. #define VERTEX_2_SPEC_ARGB 0x066C /* Dword offset 1_B5 */
  470. #define VERTEX_3_SPEC_ARGB 0x068C /* Dword offset 1_B6 */
  471. #define VERTEX_1_Z 0x0650 /* Dword offset 1_B7 */
  472. #define VERTEX_2_Z 0x0670 /* Dword offset 1_B8 */
  473. #define VERTEX_3_Z 0x0690 /* Dword offset 1_B9 */
  474. #define VERTEX_1_ARGB 0x0654 /* Dword offset 1_BA */
  475. #define VERTEX_2_ARGB 0x0674 /* Dword offset 1_BB */
  476. #define VERTEX_3_ARGB 0x0694 /* Dword offset 1_BC */
  477. #define VERTEX_1_X_Y 0x0658 /* Dword offset 1_BD */
  478. #define VERTEX_2_X_Y 0x0678 /* Dword offset 1_BE */
  479. #define VERTEX_3_X_Y 0x0698 /* Dword offset 1_BF */
  480. #define ONE_OVER_AREA_UC 0x0700 /* Dword offset 1_C0 */
  481. #define SETUP_CNTL 0x0704 /* Dword offset 1_C1 */
  482. #define VERTEX_1_SECONDARY_S 0x0728 /* Dword offset 1_CA */
  483. #define VERTEX_1_SECONDARY_T 0x072C /* Dword offset 1_CB */
  484. #define VERTEX_1_SECONDARY_W 0x0730 /* Dword offset 1_CC */
  485. #define VERTEX_2_SECONDARY_S 0x0734 /* Dword offset 1_CD */
  486. #define VERTEX_2_SECONDARY_T 0x0738 /* Dword offset 1_CE */
  487. #define VERTEX_2_SECONDARY_W 0x073C /* Dword offset 1_CF */
  488. #define GTC_3D_RESET_DELAY 3 /* 3D engine reset delay in ms */
  489. /* CRTC control values (mostly CRTC_GEN_CNTL) */
  490. #define CRTC_H_SYNC_NEG 0x00200000
  491. #define CRTC_V_SYNC_NEG 0x00200000
  492. #define CRTC_DBL_SCAN_EN 0x00000001
  493. #define CRTC_INTERLACE_EN 0x00000002
  494. #define CRTC_HSYNC_DIS 0x00000004
  495. #define CRTC_VSYNC_DIS 0x00000008
  496. #define CRTC_CSYNC_EN 0x00000010
  497. #define CRTC_PIX_BY_2_EN 0x00000020 /* unused on RAGE */
  498. #define CRTC_DISPLAY_DIS 0x00000040
  499. #define CRTC_VGA_XOVERSCAN 0x00000080
  500. #define CRTC_PIX_WIDTH_MASK 0x00000700
  501. #define CRTC_PIX_WIDTH_4BPP 0x00000100
  502. #define CRTC_PIX_WIDTH_8BPP 0x00000200
  503. #define CRTC_PIX_WIDTH_15BPP 0x00000300
  504. #define CRTC_PIX_WIDTH_16BPP 0x00000400
  505. #define CRTC_PIX_WIDTH_24BPP 0x00000500
  506. #define CRTC_PIX_WIDTH_32BPP 0x00000600
  507. #define CRTC_BYTE_PIX_ORDER 0x00000800
  508. #define CRTC_PIX_ORDER_MSN_LSN 0x00000000
  509. #define CRTC_PIX_ORDER_LSN_MSN 0x00000800
  510. #define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */
  511. #define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */
  512. #define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */
  513. #define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */
  514. #define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */
  515. #define CRTC_FIFO_LWM 0x000f0000
  516. #define CRTC_HVSYNC_IO_DRIVE 0x00010000 /* XC/XL */
  517. #define CRTC2_PIX_WIDTH 0x000e0000 /* LTPro */
  518. #define CRTC_VGA_128KAP_PAGING 0x00100000
  519. #define CRTC_VFC_SYNC_TRISTATE 0x00200000 /* VTB/GTB/LT */
  520. #define CRTC2_EN 0x00200000 /* LTPro */
  521. #define CRTC_LOCK_REGS 0x00400000
  522. #define CRTC_SYNC_TRISTATE 0x00800000
  523. #define CRTC_EXT_DISP_EN 0x01000000
  524. #define CRTC_EN 0x02000000
  525. #define CRTC_DISP_REQ_EN 0x04000000
  526. #define CRTC_VGA_LINEAR 0x08000000
  527. #define CRTC_VSYNC_FALL_EDGE 0x10000000
  528. #define CRTC_VGA_TEXT_132 0x20000000
  529. #define CRTC_CNT_EN 0x40000000
  530. #define CRTC_CUR_B_TEST 0x80000000
  531. #define CRTC_CRNT_VLINE 0x07f00000
  532. #define CRTC_PRESERVED_MASK 0x0001f000
  533. #define CRTC_VBLANK 0x00000001
  534. #define CRTC_VBLANK_INT_EN 0x00000002
  535. #define CRTC_VBLANK_INT 0x00000004
  536. #define CRTC_VBLANK_INT_AK CRTC_VBLANK_INT
  537. #define CRTC_VLINE_INT_EN 0x00000008
  538. #define CRTC_VLINE_INT 0x00000010
  539. #define CRTC_VLINE_INT_AK CRTC_VLINE_INT
  540. #define CRTC_VLINE_SYNC 0x00000020
  541. #define CRTC_FRAME 0x00000040
  542. #define SNAPSHOT_INT_EN 0x00000080
  543. #define SNAPSHOT_INT 0x00000100
  544. #define SNAPSHOT_INT_AK SNAPSHOT_INT
  545. #define I2C_INT_EN 0x00000200
  546. #define I2C_INT 0x00000400
  547. #define I2C_INT_AK I2C_INT
  548. #define CRTC2_VBLANK 0x00000800
  549. #define CRTC2_VBLANK_INT_EN 0x00001000
  550. #define CRTC2_VBLANK_INT 0x00002000
  551. #define CRTC2_VBLANK_INT_AK CRTC2_VBLANK_INT
  552. #define CRTC2_VLINE_INT_EN 0x00004000
  553. #define CRTC2_VLINE_INT 0x00008000
  554. #define CRTC2_VLINE_INT_AK CRTC2_VLINE_INT
  555. #define CAPBUF0_INT_EN 0x00010000
  556. #define CAPBUF0_INT 0x00020000
  557. #define CAPBUF0_INT_AK CAPBUF0_INT
  558. #define CAPBUF1_INT_EN 0x00040000
  559. #define CAPBUF1_INT 0x00080000
  560. #define CAPBUF1_INT_AK CAPBUF1_INT
  561. #define OVERLAY_EOF_INT_EN 0x00100000
  562. #define OVERLAY_EOF_INT 0x00200000
  563. #define OVERLAY_EOF_INT_AK OVERLAY_EOF_INT
  564. #define ONESHOT_CAP_INT_EN 0x00400000
  565. #define ONESHOT_CAP_INT 0x00800000
  566. #define ONESHOT_CAP_INT_AK ONESHOT_CAP_INT
  567. #define BUSMASTER_EOL_INT_EN 0x01000000
  568. #define BUSMASTER_EOL_INT 0x02000000
  569. #define BUSMASTER_EOL_INT_AK BUSMASTER_EOL_INT
  570. #define GP_INT_EN 0x04000000
  571. #define GP_INT 0x08000000
  572. #define GP_INT_AK GP_INT
  573. #define CRTC2_VLINE_SYNC 0x10000000
  574. #define SNAPSHOT2_INT_EN 0x20000000
  575. #define SNAPSHOT2_INT 0x40000000
  576. #define SNAPSHOT2_INT_AK SNAPSHOT2_INT
  577. #define VBLANK_BIT2_INT 0x80000000
  578. #define VBLANK_BIT2_INT_AK VBLANK_BIT2_INT
  579. #define CRTC_INT_EN_MASK (CRTC_VBLANK_INT_EN | \
  580. CRTC_VLINE_INT_EN | \
  581. SNAPSHOT_INT_EN | \
  582. I2C_INT_EN | \
  583. CRTC2_VBLANK_INT_EN | \
  584. CRTC2_VLINE_INT_EN | \
  585. CAPBUF0_INT_EN | \
  586. CAPBUF1_INT_EN | \
  587. OVERLAY_EOF_INT_EN | \
  588. ONESHOT_CAP_INT_EN | \
  589. BUSMASTER_EOL_INT_EN | \
  590. GP_INT_EN | \
  591. SNAPSHOT2_INT_EN)
  592. /* DAC control values */
  593. #define DAC_EXT_SEL_RS2 0x01
  594. #define DAC_EXT_SEL_RS3 0x02
  595. #define DAC_8BIT_EN 0x00000100
  596. #define DAC_PIX_DLY_MASK 0x00000600
  597. #define DAC_PIX_DLY_0NS 0x00000000
  598. #define DAC_PIX_DLY_2NS 0x00000200
  599. #define DAC_PIX_DLY_4NS 0x00000400
  600. #define DAC_BLANK_ADJ_MASK 0x00001800
  601. #define DAC_BLANK_ADJ_0 0x00000000
  602. #define DAC_BLANK_ADJ_1 0x00000800
  603. #define DAC_BLANK_ADJ_2 0x00001000
  604. /* DAC control values (my source XL/XC Register reference) */
  605. #define DAC_OUTPUT_MASK 0x00000001 /* 0 - PAL, 1 - NTSC */
  606. #define DAC_MISTERY_BIT 0x00000002 /* PS2 ? RS343 ?, EXTRA_BRIGHT for GT */
  607. #define DAC_BLANKING 0x00000004
  608. #define DAC_CMP_DISABLE 0x00000008
  609. #define DAC1_CLK_SEL 0x00000010
  610. #define PALETTE_ACCESS_CNTL 0x00000020
  611. #define PALETTE2_SNOOP_EN 0x00000040
  612. #define DAC_CMP_OUTPUT 0x00000080 /* read only */
  613. /* #define DAC_8BIT_EN is ok */
  614. #define CRT_SENSE 0x00000800 /* read only */
  615. #define CRT_DETECTION_ON 0x00001000
  616. #define DAC_VGA_ADR_EN 0x00002000
  617. #define DAC_FEA_CON_EN 0x00004000
  618. #define DAC_PDWN 0x00008000
  619. #define DAC_TYPE_MASK 0x00070000 /* read only */
  620. /* Mix control values */
  621. #define MIX_NOT_DST 0x0000
  622. #define MIX_0 0x0001
  623. #define MIX_1 0x0002
  624. #define MIX_DST 0x0003
  625. #define MIX_NOT_SRC 0x0004
  626. #define MIX_XOR 0x0005
  627. #define MIX_XNOR 0x0006
  628. #define MIX_SRC 0x0007
  629. #define MIX_NAND 0x0008
  630. #define MIX_NOT_SRC_OR_DST 0x0009
  631. #define MIX_SRC_OR_NOT_DST 0x000a
  632. #define MIX_OR 0x000b
  633. #define MIX_AND 0x000c
  634. #define MIX_SRC_AND_NOT_DST 0x000d
  635. #define MIX_NOT_SRC_AND_DST 0x000e
  636. #define MIX_NOR 0x000f
  637. /* Maximum engine dimensions */
  638. #define ENGINE_MIN_X 0
  639. #define ENGINE_MIN_Y 0
  640. #define ENGINE_MAX_X 4095
  641. #define ENGINE_MAX_Y 16383
  642. /* Mach64 engine bit constants - these are typically ORed together */
  643. /* BUS_CNTL register constants */
  644. #define BUS_APER_REG_DIS 0x00000010
  645. #define BUS_FIFO_ERR_ACK 0x00200000
  646. #define BUS_HOST_ERR_ACK 0x00800000
  647. /* GEN_TEST_CNTL register constants */
  648. #define GEN_OVR_OUTPUT_EN 0x20
  649. #define HWCURSOR_ENABLE 0x80
  650. #define GUI_ENGINE_ENABLE 0x100
  651. #define BLOCK_WRITE_ENABLE 0x200
  652. /* DSP_CONFIG register constants */
  653. #define DSP_XCLKS_PER_QW 0x00003fff
  654. #define DSP_LOOP_LATENCY 0x000f0000
  655. #define DSP_PRECISION 0x00700000
  656. /* DSP_ON_OFF register constants */
  657. #define DSP_OFF 0x000007ff
  658. #define DSP_ON 0x07ff0000
  659. #define VGA_DSP_OFF DSP_OFF
  660. #define VGA_DSP_ON DSP_ON
  661. #define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW
  662. /* PLL register indices and fields */
  663. #define MPLL_CNTL 0x00
  664. #define PLL_PC_GAIN 0x07
  665. #define PLL_VC_GAIN 0x18
  666. #define PLL_DUTY_CYC 0xE0
  667. #define VPLL_CNTL 0x01
  668. #define PLL_REF_DIV 0x02
  669. #define PLL_GEN_CNTL 0x03
  670. #define PLL_OVERRIDE 0x01 /* PLL_SLEEP */
  671. #define PLL_MCLK_RST 0x02 /* PLL_MRESET */
  672. #define OSC_EN 0x04
  673. #define EXT_CLK_EN 0x08
  674. #define FORCE_DCLK_TRI_STATE 0x08 /* VT4 -> */
  675. #define MCLK_SRC_SEL 0x70
  676. #define EXT_CLK_CNTL 0x80
  677. #define DLL_PWDN 0x80 /* VT4 -> */
  678. #define MCLK_FB_DIV 0x04
  679. #define PLL_VCLK_CNTL 0x05
  680. #define PLL_VCLK_SRC_SEL 0x03
  681. #define PLL_VCLK_RST 0x04
  682. #define PLL_VCLK_INVERT 0x08
  683. #define VCLK_POST_DIV 0x06
  684. #define VCLK0_POST 0x03
  685. #define VCLK1_POST 0x0C
  686. #define VCLK2_POST 0x30
  687. #define VCLK3_POST 0xC0
  688. #define VCLK0_FB_DIV 0x07
  689. #define VCLK1_FB_DIV 0x08
  690. #define VCLK2_FB_DIV 0x09
  691. #define VCLK3_FB_DIV 0x0A
  692. #define PLL_EXT_CNTL 0x0B
  693. #define PLL_XCLK_MCLK_RATIO 0x03
  694. #define PLL_XCLK_SRC_SEL 0x07
  695. #define PLL_MFB_TIMES_4_2B 0x08
  696. #define PLL_VCLK0_XDIV 0x10
  697. #define PLL_VCLK1_XDIV 0x20
  698. #define PLL_VCLK2_XDIV 0x40
  699. #define PLL_VCLK3_XDIV 0x80
  700. #define DLL_CNTL 0x0C
  701. #define DLL1_CNTL 0x0C
  702. #define VFC_CNTL 0x0D
  703. #define PLL_TEST_CNTL 0x0E
  704. #define PLL_TEST_COUNT 0x0F
  705. #define LVDS_CNTL0 0x10
  706. #define LVDS_CNTL1 0x11
  707. #define AGP1_CNTL 0x12
  708. #define AGP2_CNTL 0x13
  709. #define DLL2_CNTL 0x14
  710. #define SCLK_FB_DIV 0x15
  711. #define SPLL_CNTL1 0x16
  712. #define SPLL_CNTL2 0x17
  713. #define APLL_STRAPS 0x18
  714. #define EXT_VPLL_CNTL 0x19
  715. #define EXT_VPLL_EN 0x04
  716. #define EXT_VPLL_VGA_EN 0x08
  717. #define EXT_VPLL_INSYNC 0x10
  718. #define EXT_VPLL_REF_DIV 0x1A
  719. #define EXT_VPLL_FB_DIV 0x1B
  720. #define EXT_VPLL_MSB 0x1C
  721. #define HTOTAL_CNTL 0x1D
  722. #define BYTE_CLK_CNTL 0x1E
  723. #define TV_PLL_CNTL1 0x1F
  724. #define TV_PLL_CNTL2 0x20
  725. #define TV_PLL_CNTL 0x21
  726. #define EXT_TV_PLL 0x22
  727. #define V2PLL_CNTL 0x23
  728. #define PLL_V2CLK_CNTL 0x24
  729. #define EXT_V2PLL_REF_DIV 0x25
  730. #define EXT_V2PLL_FB_DIV 0x26
  731. #define EXT_V2PLL_MSB 0x27
  732. #define HTOTAL2_CNTL 0x28
  733. #define PLL_YCLK_CNTL 0x29
  734. #define PM_DYN_CLK_CNTL 0x2A
  735. /* CONFIG_CNTL register constants */
  736. #define APERTURE_4M_ENABLE 1
  737. #define APERTURE_8M_ENABLE 2
  738. #define VGA_APERTURE_ENABLE 4
  739. /* CONFIG_STAT0 register constants (GX, CX) */
  740. #define CFG_BUS_TYPE 0x00000007
  741. #define CFG_MEM_TYPE 0x00000038
  742. #define CFG_INIT_DAC_TYPE 0x00000e00
  743. /* CONFIG_STAT0 register constants (CT, ET, VT) */
  744. #define CFG_MEM_TYPE_xT 0x00000007
  745. #define ISA 0
  746. #define EISA 1
  747. #define LOCAL_BUS 6
  748. #define PCI 7
  749. /* Memory types for GX, CX */
  750. #define DRAMx4 0
  751. #define VRAMx16 1
  752. #define VRAMx16ssr 2
  753. #define DRAMx16 3
  754. #define GraphicsDRAMx16 4
  755. #define EnhancedVRAMx16 5
  756. #define EnhancedVRAMx16ssr 6
  757. /* Memory types for CT, ET, VT, GT */
  758. #define DRAM 1
  759. #define EDO 2
  760. #define PSEUDO_EDO 3
  761. #define SDRAM 4
  762. #define SGRAM 5
  763. #define WRAM 6
  764. #define DAC_INTERNAL 0x00
  765. #define DAC_IBMRGB514 0x01
  766. #define DAC_ATI68875 0x02
  767. #define DAC_TVP3026_A 0x72
  768. #define DAC_BT476 0x03
  769. #define DAC_BT481 0x04
  770. #define DAC_ATT20C491 0x14
  771. #define DAC_SC15026 0x24
  772. #define DAC_MU9C1880 0x34
  773. #define DAC_IMSG174 0x44
  774. #define DAC_ATI68860_B 0x05
  775. #define DAC_ATI68860_C 0x15
  776. #define DAC_TVP3026_B 0x75
  777. #define DAC_STG1700 0x06
  778. #define DAC_ATT498 0x16
  779. #define DAC_STG1702 0x07
  780. #define DAC_SC15021 0x17
  781. #define DAC_ATT21C498 0x27
  782. #define DAC_STG1703 0x37
  783. #define DAC_CH8398 0x47
  784. #define DAC_ATT20C408 0x57
  785. #define CLK_ATI18818_0 0
  786. #define CLK_ATI18818_1 1
  787. #define CLK_STG1703 2
  788. #define CLK_CH8398 3
  789. #define CLK_INTERNAL 4
  790. #define CLK_ATT20C408 5
  791. #define CLK_IBMRGB514 6
  792. /* MEM_CNTL register constants */
  793. #define MEM_SIZE_ALIAS 0x00000007
  794. #define MEM_SIZE_512K 0x00000000
  795. #define MEM_SIZE_1M 0x00000001
  796. #define MEM_SIZE_2M 0x00000002
  797. #define MEM_SIZE_4M 0x00000003
  798. #define MEM_SIZE_6M 0x00000004
  799. #define MEM_SIZE_8M 0x00000005
  800. #define MEM_SIZE_ALIAS_GTB 0x0000000F
  801. #define MEM_SIZE_2M_GTB 0x00000003
  802. #define MEM_SIZE_4M_GTB 0x00000007
  803. #define MEM_SIZE_6M_GTB 0x00000009
  804. #define MEM_SIZE_8M_GTB 0x0000000B
  805. #define MEM_BNDRY 0x00030000
  806. #define MEM_BNDRY_0K 0x00000000
  807. #define MEM_BNDRY_256K 0x00010000
  808. #define MEM_BNDRY_512K 0x00020000
  809. #define MEM_BNDRY_1M 0x00030000
  810. #define MEM_BNDRY_EN 0x00040000
  811. #define ONE_MB 0x100000
  812. /* ATI PCI constants */
  813. #define PCI_ATI_VENDOR_ID 0x1002
  814. /* CONFIG_CHIP_ID register constants */
  815. #define CFG_CHIP_TYPE 0x0000FFFF
  816. #define CFG_CHIP_CLASS 0x00FF0000
  817. #define CFG_CHIP_REV 0xFF000000
  818. #define CFG_CHIP_MAJOR 0x07000000
  819. #define CFG_CHIP_FND_ID 0x38000000
  820. #define CFG_CHIP_MINOR 0xC0000000
  821. /* Chip IDs read from CONFIG_CHIP_ID */
  822. /* mach64GX family */
  823. #define GX_CHIP_ID 0xD7 /* mach64GX (ATI888GX00) */
  824. #define CX_CHIP_ID 0x57 /* mach64CX (ATI888CX00) */
  825. #define GX_PCI_ID 0x4758 /* mach64GX (ATI888GX00) */
  826. #define CX_PCI_ID 0x4358 /* mach64CX (ATI888CX00) */
  827. /* mach64CT family */
  828. #define CT_CHIP_ID 0x4354 /* mach64CT (ATI264CT) */
  829. #define ET_CHIP_ID 0x4554 /* mach64ET (ATI264ET) */
  830. /* mach64CT family / mach64VT class */
  831. #define VT_CHIP_ID 0x5654 /* mach64VT (ATI264VT) */
  832. #define VU_CHIP_ID 0x5655 /* mach64VTB (ATI264VTB) */
  833. #define VV_CHIP_ID 0x5656 /* mach64VT4 (ATI264VT4) */
  834. /* mach64CT family / mach64GT (3D RAGE) class */
  835. #define LB_CHIP_ID 0x4c42 /* RAGE LT PRO, AGP */
  836. #define LD_CHIP_ID 0x4c44 /* RAGE LT PRO */
  837. #define LG_CHIP_ID 0x4c47 /* RAGE LT */
  838. #define LI_CHIP_ID 0x4c49 /* RAGE LT PRO */
  839. #define LP_CHIP_ID 0x4c50 /* RAGE LT PRO */
  840. #define LT_CHIP_ID 0x4c54 /* RAGE LT */
  841. /* mach64CT family / (Rage XL) class */
  842. #define GR_CHIP_ID 0x4752 /* RAGE XL, BGA, PCI33 */
  843. #define GS_CHIP_ID 0x4753 /* RAGE XL, PQFP, PCI33 */
  844. #define GM_CHIP_ID 0x474d /* RAGE XL, BGA, AGP 1x,2x */
  845. #define GN_CHIP_ID 0x474e /* RAGE XL, PQFP,AGP 1x,2x */
  846. #define GO_CHIP_ID 0x474f /* RAGE XL, BGA, PCI66 */
  847. #define GL_CHIP_ID 0x474c /* RAGE XL, PQFP, PCI66 */
  848. #define IS_XL(id) ((id)==GR_CHIP_ID || (id)==GS_CHIP_ID || \
  849. (id)==GM_CHIP_ID || (id)==GN_CHIP_ID || \
  850. (id)==GO_CHIP_ID || (id)==GL_CHIP_ID)
  851. #define GT_CHIP_ID 0x4754 /* RAGE (GT) */
  852. #define GU_CHIP_ID 0x4755 /* RAGE II/II+ (GTB) */
  853. #define GV_CHIP_ID 0x4756 /* RAGE IIC, PCI */
  854. #define GW_CHIP_ID 0x4757 /* RAGE IIC, AGP */
  855. #define GZ_CHIP_ID 0x475a /* RAGE IIC, AGP */
  856. #define GB_CHIP_ID 0x4742 /* RAGE PRO, BGA, AGP 1x and 2x */
  857. #define GD_CHIP_ID 0x4744 /* RAGE PRO, BGA, AGP 1x only */
  858. #define GI_CHIP_ID 0x4749 /* RAGE PRO, BGA, PCI33 only */
  859. #define GP_CHIP_ID 0x4750 /* RAGE PRO, PQFP, PCI33, full 3D */
  860. #define GQ_CHIP_ID 0x4751 /* RAGE PRO, PQFP, PCI33, limited 3D */
  861. #define LM_CHIP_ID 0x4c4d /* RAGE Mobility AGP, full function */
  862. #define LN_CHIP_ID 0x4c4e /* RAGE Mobility AGP */
  863. #define LR_CHIP_ID 0x4c52 /* RAGE Mobility PCI, full function */
  864. #define LS_CHIP_ID 0x4c53 /* RAGE Mobility PCI */
  865. #define IS_MOBILITY(id) ((id)==LM_CHIP_ID || (id)==LN_CHIP_ID || \
  866. (id)==LR_CHIP_ID || (id)==LS_CHIP_ID)
  867. /* Mach64 major ASIC revisions */
  868. #define MACH64_ASIC_NEC_VT_A3 0x08
  869. #define MACH64_ASIC_NEC_VT_A4 0x48
  870. #define MACH64_ASIC_SGS_VT_A4 0x40
  871. #define MACH64_ASIC_SGS_VT_B1S1 0x01
  872. #define MACH64_ASIC_SGS_GT_B1S1 0x01
  873. #define MACH64_ASIC_SGS_GT_B1S2 0x41
  874. #define MACH64_ASIC_UMC_GT_B2U1 0x1a
  875. #define MACH64_ASIC_UMC_GT_B2U2 0x5a
  876. #define MACH64_ASIC_UMC_VT_B2U3 0x9a
  877. #define MACH64_ASIC_UMC_GT_B2U3 0x9a
  878. #define MACH64_ASIC_UMC_R3B_D_P_A1 0x1b
  879. #define MACH64_ASIC_UMC_R3B_D_P_A2 0x5b
  880. #define MACH64_ASIC_UMC_R3B_D_P_A3 0x1c
  881. #define MACH64_ASIC_UMC_R3B_D_P_A4 0x5c
  882. /* Mach64 foundries */
  883. #define MACH64_FND_SGS 0
  884. #define MACH64_FND_NEC 1
  885. #define MACH64_FND_UMC 3
  886. /* Mach64 chip types */
  887. #define MACH64_UNKNOWN 0
  888. #define MACH64_GX 1
  889. #define MACH64_CX 2
  890. #define MACH64_CT 3Restore
  891. #define MACH64_ET 4
  892. #define MACH64_VT 5
  893. #define MACH64_GT 6
  894. /* DST_CNTL register constants */
  895. #define DST_X_RIGHT_TO_LEFT 0
  896. #define DST_X_LEFT_TO_RIGHT 1
  897. #define DST_Y_BOTTOM_TO_TOP 0
  898. #define DST_Y_TOP_TO_BOTTOM 2
  899. #define DST_X_MAJOR 0
  900. #define DST_Y_MAJOR 4
  901. #define DST_X_TILE 8
  902. #define DST_Y_TILE 0x10
  903. #define DST_LAST_PEL 0x20
  904. #define DST_POLYGON_ENABLE 0x40
  905. #define DST_24_ROTATION_ENABLE 0x80
  906. /* SRC_CNTL register constants */
  907. #define SRC_PATTERN_ENABLE 1
  908. #define SRC_ROTATION_ENABLE 2
  909. #define SRC_LINEAR_ENABLE 4
  910. #define SRC_BYTE_ALIGN 8
  911. #define SRC_LINE_X_RIGHT_TO_LEFT 0
  912. #define SRC_LINE_X_LEFT_TO_RIGHT 0x10
  913. /* HOST_CNTL register constants */
  914. #define HOST_BYTE_ALIGN 1
  915. /* GUI_TRAJ_CNTL register constants */
  916. #define PAT_MONO_8x8_ENABLE 0x01000000
  917. #define PAT_CLR_4x2_ENABLE 0x02000000
  918. #define PAT_CLR_8x1_ENABLE 0x04000000
  919. /* DP_CHAIN_MASK register constants */
  920. #define DP_CHAIN_4BPP 0x8888
  921. #define DP_CHAIN_7BPP 0xD2D2
  922. #define DP_CHAIN_8BPP 0x8080
  923. #define DP_CHAIN_8BPP_RGB 0x9292
  924. #define DP_CHAIN_15BPP 0x4210
  925. #define DP_CHAIN_16BPP 0x8410
  926. #define DP_CHAIN_24BPP 0x8080
  927. #define DP_CHAIN_32BPP 0x8080
  928. /* DP_PIX_WIDTH register constants */
  929. #define DST_1BPP 0x0
  930. #define DST_4BPP 0x1
  931. #define DST_8BPP 0x2
  932. #define DST_15BPP 0x3
  933. #define DST_16BPP 0x4
  934. #define DST_24BPP 0x5
  935. #define DST_32BPP 0x6
  936. #define DST_MASK 0xF
  937. #define SRC_1BPP 0x000
  938. #define SRC_4BPP 0x100
  939. #define SRC_8BPP 0x200
  940. #define SRC_15BPP 0x300
  941. #define SRC_16BPP 0x400
  942. #define SRC_24BPP 0x500
  943. #define SRC_32BPP 0x600
  944. #define SRC_MASK 0xF00
  945. #define DP_HOST_TRIPLE_EN 0x2000
  946. #define HOST_1BPP 0x00000
  947. #define HOST_4BPP 0x10000
  948. #define HOST_8BPP 0x20000
  949. #define HOST_15BPP 0x30000
  950. #define HOST_16BPP 0x40000
  951. #define HOST_24BPP 0x50000
  952. #define HOST_32BPP 0x60000
  953. #define HOST_MASK 0xF0000
  954. #define BYTE_ORDER_MSB_TO_LSB 0
  955. #define BYTE_ORDER_LSB_TO_MSB 0x1000000
  956. #define BYTE_ORDER_MASK 0x1000000
  957. /* DP_MIX register constants */
  958. #define BKGD_MIX_NOT_D 0
  959. #define BKGD_MIX_ZERO 1
  960. #define BKGD_MIX_ONE 2
  961. #define BKGD_MIX_D 3
  962. #define BKGD_MIX_NOT_S 4
  963. #define BKGD_MIX_D_XOR_S 5
  964. #define BKGD_MIX_NOT_D_XOR_S 6
  965. #define BKGD_MIX_S 7
  966. #define BKGD_MIX_NOT_D_OR_NOT_S 8
  967. #define BKGD_MIX_D_OR_NOT_S 9
  968. #define BKGD_MIX_NOT_D_OR_S 10
  969. #define BKGD_MIX_D_OR_S 11
  970. #define BKGD_MIX_D_AND_S 12
  971. #define BKGD_MIX_NOT_D_AND_S 13
  972. #define BKGD_MIX_D_AND_NOT_S 14
  973. #define BKGD_MIX_NOT_D_AND_NOT_S 15
  974. #define BKGD_MIX_D_PLUS_S_DIV2 0x17
  975. #define FRGD_MIX_NOT_D 0
  976. #define FRGD_MIX_ZERO 0x10000
  977. #define FRGD_MIX_ONE 0x20000
  978. #define FRGD_MIX_D 0x30000
  979. #define FRGD_MIX_NOT_S 0x40000
  980. #define FRGD_MIX_D_XOR_S 0x50000
  981. #define FRGD_MIX_NOT_D_XOR_S 0x60000
  982. #define FRGD_MIX_S 0x70000
  983. #define FRGD_MIX_NOT_D_OR_NOT_S 0x80000
  984. #define FRGD_MIX_D_OR_NOT_S 0x90000
  985. #define FRGD_MIX_NOT_D_OR_S 0xa0000
  986. #define FRGD_MIX_D_OR_S 0xb0000
  987. #define FRGD_MIX_D_AND_S 0xc0000
  988. #define FRGD_MIX_NOT_D_AND_S 0xd0000
  989. #define FRGD_MIX_D_AND_NOT_S 0xe0000
  990. #define FRGD_MIX_NOT_D_AND_NOT_S 0xf0000
  991. #define FRGD_MIX_D_PLUS_S_DIV2 0x170000
  992. /* DP_SRC register constants */
  993. #define BKGD_SRC_BKGD_CLR 0
  994. #define BKGD_SRC_FRGD_CLR 1
  995. #define BKGD_SRC_HOST 2
  996. #define BKGD_SRC_BLIT 3
  997. #define BKGD_SRC_PATTERN 4
  998. #define FRGD_SRC_BKGD_CLR 0
  999. #define FRGD_SRC_FRGD_CLR 0x100
  1000. #define FRGD_SRC_HOST 0x200
  1001. #define FRGD_SRC_BLIT 0x300
  1002. #define FRGD_SRC_PATTERN 0x400
  1003. #define MONO_SRC_ONE 0
  1004. #define MONO_SRC_PATTERN 0x10000
  1005. #define MONO_SRC_HOST 0x20000
  1006. #define MONO_SRC_BLIT 0x30000
  1007. /* CLR_CMP_CNTL register constants */
  1008. #define COMPARE_FALSE 0
  1009. #define COMPARE_TRUE 1
  1010. #define COMPARE_NOT_EQUAL 4
  1011. #define COMPARE_EQUAL 5
  1012. #define COMPARE_DESTINATION 0
  1013. #define COMPARE_SOURCE 0x1000000
  1014. /* FIFO_STAT register constants */
  1015. #define FIFO_ERR 0x80000000
  1016. /* CONTEXT_LOAD_CNTL constants */
  1017. #define CONTEXT_NO_LOAD 0
  1018. #define CONTEXT_LOAD 0x10000
  1019. #define CONTEXT_LOAD_AND_DO_FILL 0x20000
  1020. #define CONTEXT_LOAD_AND_DO_LINE 0x30000
  1021. #define CONTEXT_EXECUTE 0
  1022. #define CONTEXT_CMD_DISABLE 0x80000000
  1023. /* GUI_STAT register constants */
  1024. #define ENGINE_IDLE 0
  1025. #define ENGINE_BUSY 1
  1026. #define SCISSOR_LEFT_FLAG 0x10
  1027. #define SCISSOR_RIGHT_FLAG 0x20
  1028. #define SCISSOR_TOP_FLAG 0x40
  1029. #define SCISSOR_BOTTOM_FLAG 0x80
  1030. /* ATI VGA Extended Regsiters */
  1031. #define sioATIEXT 0x1ce
  1032. #define bioATIEXT 0x3ce
  1033. #define ATI2E 0xae
  1034. #define ATI32 0xb2
  1035. #define ATI36 0xb6
  1036. /* VGA Graphics Controller Registers */
  1037. #define R_GENMO 0x3cc
  1038. #define VGAGRA 0x3ce
  1039. #define GRA06 0x06
  1040. /* VGA Seququencer Registers */
  1041. #define VGASEQ 0x3c4
  1042. #define SEQ02 0x02
  1043. #define SEQ04 0x04
  1044. #define MACH64_MAX_X ENGINE_MAX_X
  1045. #define MACH64_MAX_Y ENGINE_MAX_Y
  1046. #define INC_X 0x0020
  1047. #define INC_Y 0x0080
  1048. #define RGB16_555 0x0000
  1049. #define RGB16_565 0x0040
  1050. #define RGB16_655 0x0080
  1051. #define RGB16_664 0x00c0
  1052. #define POLY_TEXT_TYPE 0x0001
  1053. #define IMAGE_TEXT_TYPE 0x0002
  1054. #define TEXT_TYPE_8_BIT 0x0004
  1055. #define TEXT_TYPE_16_BIT 0x0008
  1056. #define POLY_TEXT_TYPE_8 (POLY_TEXT_TYPE | TEXT_TYPE_8_BIT)
  1057. #define IMAGE_TEXT_TYPE_8 (IMAGE_TEXT_TYPE | TEXT_TYPE_8_BIT)
  1058. #define POLY_TEXT_TYPE_16 (POLY_TEXT_TYPE | TEXT_TYPE_16_BIT)
  1059. #define IMAGE_TEXT_TYPE_16 (IMAGE_TEXT_TYPE | TEXT_TYPE_16_BIT)
  1060. #define MACH64_NUM_CLOCKS 16
  1061. #define MACH64_NUM_FREQS 50
  1062. /* Power Management register constants (LT & LT Pro) */
  1063. #define PWR_MGT_ON 0x00000001
  1064. #define PWR_MGT_MODE_MASK 0x00000006
  1065. #define AUTO_PWR_UP 0x00000008
  1066. #define USE_F32KHZ 0x00000400
  1067. #define TRISTATE_MEM_EN 0x00000800
  1068. #define SELF_REFRESH 0x00000080
  1069. #define PWR_BLON 0x02000000
  1070. #define STANDBY_NOW 0x10000000
  1071. #define SUSPEND_NOW 0x20000000
  1072. #define PWR_MGT_STATUS_MASK 0xC0000000
  1073. #define PWR_MGT_STATUS_SUSPEND 0x80000000
  1074. /* PM Mode constants */
  1075. #define PWR_MGT_MODE_PIN 0x00000000
  1076. #define PWR_MGT_MODE_REG 0x00000002
  1077. #define PWR_MGT_MODE_TIMER 0x00000004
  1078. #define PWR_MGT_MODE_PCI 0x00000006
  1079. /* LCD registers (LT Pro) */
  1080. /* LCD Index register */
  1081. #define LCD_INDEX_MASK 0x0000003F
  1082. #define LCD_DISPLAY_DIS 0x00000100
  1083. #define LCD_SRC_SEL 0x00000200
  1084. #define CRTC2_DISPLAY_DIS 0x00000400
  1085. /* LCD register indices */
  1086. #define CONFIG_PANEL 0x00
  1087. #define LCD_GEN_CNTL 0x01
  1088. #define DSTN_CONTROL 0x02
  1089. #define HFB_PITCH_ADDR 0x03
  1090. #define HORZ_STRETCHING 0x04
  1091. #define VERT_STRETCHING 0x05
  1092. #define EXT_VERT_STRETCH 0x06
  1093. #define LT_GIO 0x07
  1094. #define POWER_MANAGEMENT 0x08
  1095. #define ZVGPIO 0x09
  1096. #define ICON_CLR0 0x0A
  1097. #define ICON_CLR1 0x0B
  1098. #define ICON_OFFSET 0x0C
  1099. #define ICON_HORZ_VERT_POSN 0x0D
  1100. #define ICON_HORZ_VERT_OFF 0x0E
  1101. #define ICON2_CLR0 0x0F
  1102. #define ICON2_CLR1 0x10
  1103. #define ICON2_OFFSET 0x11
  1104. #define ICON2_HORZ_VERT_POSN 0x12
  1105. #define ICON2_HORZ_VERT_OFF 0x13
  1106. #define LCD_MISC_CNTL 0x14
  1107. #define APC_CNTL 0x1C
  1108. #define POWER_MANAGEMENT_2 0x1D
  1109. #define ALPHA_BLENDING 0x25
  1110. #define PORTRAIT_GEN_CNTL 0x26
  1111. #define APC_CTRL_IO 0x27
  1112. #define TEST_IO 0x28
  1113. #define TEST_OUTPUTS 0x29
  1114. #define DP1_MEM_ACCESS 0x2A
  1115. #define DP0_MEM_ACCESS 0x2B
  1116. #define DP0_DEBUG_A 0x2C
  1117. #define DP0_DEBUG_B 0x2D
  1118. #define DP1_DEBUG_A 0x2E
  1119. #define DP1_DEBUG_B 0x2F
  1120. #define DPCTRL_DEBUG_A 0x30
  1121. #define DPCTRL_DEBUG_B 0x31
  1122. #define MEMBLK_DEBUG 0x32
  1123. #define APC_LUT_AB 0x33
  1124. #define APC_LUT_CD 0x34
  1125. #define APC_LUT_EF 0x35
  1126. #define APC_LUT_GH 0x36
  1127. #define APC_LUT_IJ 0x37
  1128. #define APC_LUT_KL 0x38
  1129. #define APC_LUT_MN 0x39
  1130. #define APC_LUT_OP 0x3A
  1131. /* Values in LCD_GEN_CTRL */
  1132. #define CRT_ON 0x00000001ul
  1133. #define LCD_ON 0x00000002ul
  1134. #define HORZ_DIVBY2_EN 0x00000004ul
  1135. #define DONT_DS_ICON 0x00000008ul
  1136. #define LOCK_8DOT 0x00000010ul
  1137. #define ICON_ENABLE 0x00000020ul
  1138. #define DONT_SHADOW_VPAR 0x00000040ul
  1139. #define V2CLK_PM_EN 0x00000080ul
  1140. #define RST_FM 0x00000100ul
  1141. #define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */
  1142. #define DIS_HOR_CRT_DIVBY2 0x00000400ul
  1143. #define SCLK_SEL 0x00000800ul
  1144. #define SCLK_DELAY 0x0000f000ul
  1145. #define TVCLK_PM_EN 0x00010000ul
  1146. #define VCLK_DAC_PM_EN 0x00020000ul
  1147. #define VCLK_LCD_OFF 0x00040000ul
  1148. #define SELECT_WAIT_4MS 0x00080000ul
  1149. #define XTALIN_PM_EN 0x00080000ul /* XC/XL */
  1150. #define V2CLK_DAC_PM_EN 0x00100000ul
  1151. #define LVDS_EN 0x00200000ul
  1152. #define LVDS_PLL_EN 0x00400000ul
  1153. #define LVDS_PLL_RESET 0x00800000ul
  1154. #define LVDS_RESERVED_BITS 0x07000000ul
  1155. #define CRTC_RW_SELECT 0x08000000ul /* LTPro */
  1156. #define USE_SHADOWED_VEND 0x10000000ul
  1157. #define USE_SHADOWED_ROWCUR 0x20000000ul
  1158. #define SHADOW_EN 0x40000000ul
  1159. #define SHADOW_RW_EN 0x80000000ul
  1160. #define LCD_SET_PRIMARY_MASK 0x07FFFBFBul
  1161. /* Values in HORZ_STRETCHING */
  1162. #define HORZ_STRETCH_BLEND 0x00000ffful
  1163. #define HORZ_STRETCH_RATIO 0x0000fffful
  1164. #define HORZ_STRETCH_LOOP 0x00070000ul
  1165. #define HORZ_STRETCH_LOOP09 0x00000000ul
  1166. #define HORZ_STRETCH_LOOP11 0x00010000ul
  1167. #define HORZ_STRETCH_LOOP12 0x00020000ul
  1168. #define HORZ_STRETCH_LOOP14 0x00030000ul
  1169. #define HORZ_STRETCH_LOOP15 0x00040000ul
  1170. /* ? 0x00050000ul */
  1171. /* ? 0x00060000ul */
  1172. /* ? 0x00070000ul */
  1173. /* ? 0x00080000ul */
  1174. #define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */
  1175. /* ? 0x10000000ul */
  1176. #define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */
  1177. #define HORZ_STRETCH_MODE 0x40000000ul
  1178. #define HORZ_STRETCH_EN 0x80000000ul
  1179. /* Values in VERT_STRETCHING */
  1180. #define VERT_STRETCH_RATIO0 0x000003fful
  1181. #define VERT_STRETCH_RATIO1 0x000ffc00ul
  1182. #define VERT_STRETCH_RATIO2 0x3ff00000ul
  1183. #define VERT_STRETCH_USE0 0x40000000ul
  1184. #define VERT_STRETCH_EN 0x80000000ul
  1185. /* Values in EXT_VERT_STRETCH */
  1186. #define VERT_STRETCH_RATIO3 0x000003fful
  1187. #define FORCE_DAC_DATA 0x000000fful
  1188. #define FORCE_DAC_DATA_SEL 0x00000300ul
  1189. #define VERT_STRETCH_MODE 0x00000400ul
  1190. #define VERT_PANEL_SIZE 0x003ff800ul
  1191. #define AUTO_VERT_RATIO 0x00400000ul
  1192. #define USE_AUTO_FP_POS 0x00800000ul
  1193. #define USE_AUTO_LCD_VSYNC 0x01000000ul
  1194. /* ? 0xfe000000ul */
  1195. /* Values in LCD_MISC_CNTL */
  1196. #define BIAS_MOD_LEVEL_MASK 0x0000ff00
  1197. #define BIAS_MOD_LEVEL_SHIFT 8
  1198. #define BLMOD_EN 0x00010000
  1199. #define BIASMOD_EN 0x00020000
  1200. #endif /* REGMACH64_H */