cirrus.h 5.6 KB

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  1. /*
  2. * drivers/video/clgenfb.h - Cirrus Logic chipset constants
  3. *
  4. * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
  5. *
  6. * Original clgenfb author: Frank Neumann
  7. *
  8. * Based on retz3fb.c and clgen.c:
  9. * Copyright (C) 1997 Jes Sorensen
  10. * Copyright (C) 1996 Frank Neumann
  11. *
  12. ***************************************************************
  13. *
  14. * Format this code with GNU indent '-kr -i8 -pcs' options.
  15. *
  16. * This file is subject to the terms and conditions of the GNU General Public
  17. * License. See the file COPYING in the main directory of this archive
  18. * for more details.
  19. *
  20. */
  21. #ifndef __CLGENFB_H__
  22. #define __CLGENFB_H__
  23. /* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */
  24. /* OLD COMMENT: these definitions might most of the time also work */
  25. /* OLD COMMENT: for other CL-GD542x/543x based boards.. */
  26. /*** External/General Registers ***/
  27. #define CL_POS102 0x102 /* POS102 register */
  28. #define CL_VSSM 0x46e8 /* Adapter Sleep */
  29. #define CL_VSSM2 0x3c3 /* Motherboard Sleep */
  30. /*** VGA Sequencer Registers ***/
  31. #define CL_SEQR0 0x0 /* Reset */
  32. /* the following are from the "extension registers" group */
  33. #define CL_SEQR6 0x6 /* Unlock ALL Extensions */
  34. #define CL_SEQR7 0x7 /* Extended Sequencer Mode */
  35. #define CL_SEQR8 0x8 /* EEPROM Control */
  36. #define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */
  37. #define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */
  38. #define CL_SEQRB 0xb /* VCLK0 Numerator */
  39. #define CL_SEQRC 0xc /* VCLK1 Numerator */
  40. #define CL_SEQRD 0xd /* VCLK2 Numerator */
  41. #define CL_SEQRE 0xe /* VCLK3 Numerator */
  42. #define CL_SEQRF 0xf /* DRAM Control */
  43. #define CL_SEQR10 0x10 /* Graphics Cursor X Position */
  44. #define CL_SEQR11 0x11 /* Graphics Cursor Y Position */
  45. #define CL_SEQR12 0x12 /* Graphics Cursor Attributes */
  46. #define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */
  47. #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */
  48. #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */
  49. #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */
  50. #define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */
  51. #define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */
  52. #define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */
  53. #define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */
  54. #define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */
  55. #define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */
  56. #define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */
  57. #define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */
  58. #define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */
  59. /*** CRT Controller Registers ***/
  60. #define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */
  61. #define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */
  62. #define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */
  63. /* the following are from the "extension registers" group */
  64. #define CL_CRT19 0x19 /* Interlace End */
  65. #define CL_CRT1A 0x1a /* Interlace Control */
  66. #define CL_CRT1B 0x1b /* Extended Display Controls */
  67. #define CL_CRT1C 0x1c /* Sync adjust and genlock register */
  68. #define CL_CRT1D 0x1d /* Overlay Extended Control register */
  69. #define CL_CRT25 0x25 /* Part Status Register */
  70. #define CL_CRT27 0x27 /* ID Register */
  71. #define CL_CRT51 0x51 /* P4 disable "flicker fixer" */
  72. /*** Graphics Controller Registers ***/
  73. /* the following are from the "extension registers" group */
  74. #define CL_GR9 0x9 /* Offset Register 0 */
  75. #define CL_GRA 0xa /* Offset Register 1 */
  76. #define CL_GRB 0xb /* Graphics Controller Mode Extensions */
  77. #define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */
  78. #define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */
  79. #define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */
  80. #define CL_GRF 0xf /* Display Compression Control register */
  81. #define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */
  82. #define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */
  83. #define CL_GR12 0x12 /* Background Color Byte 2 Register */
  84. #define CL_GR13 0x13 /* Foreground Color Byte 2 Register */
  85. #define CL_GR14 0x14 /* Background Color Byte 3 Register */
  86. #define CL_GR15 0x15 /* Foreground Color Byte 3 Register */
  87. /* the following are CL-GD5426/'28 specific blitter registers */
  88. #define CL_GR20 0x20 /* BLT Width Low */
  89. #define CL_GR21 0x21 /* BLT Width High */
  90. #define CL_GR22 0x22 /* BLT Height Low */
  91. #define CL_GR23 0x23 /* BLT Height High */
  92. #define CL_GR24 0x24 /* BLT Destination Pitch Low */
  93. #define CL_GR25 0x25 /* BLT Destination Pitch High */
  94. #define CL_GR26 0x26 /* BLT Source Pitch Low */
  95. #define CL_GR27 0x27 /* BLT Source Pitch High */
  96. #define CL_GR28 0x28 /* BLT Destination Start Low */
  97. #define CL_GR29 0x29 /* BLT Destination Start Mid */
  98. #define CL_GR2A 0x2a /* BLT Destination Start High */
  99. #define CL_GR2C 0x2c /* BLT Source Start Low */
  100. #define CL_GR2D 0x2d /* BLT Source Start Mid */
  101. #define CL_GR2E 0x2e /* BLT Source Start High */
  102. #define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */
  103. #define CL_GR30 0x30 /* BLT Mode */
  104. #define CL_GR31 0x31 /* BLT Start/Status */
  105. #define CL_GR32 0x32 /* BLT Raster Operation */
  106. #define CL_GR33 0x33 /* another P4 "compat" register.. */
  107. #define CL_GR34 0x34 /* Transparent Color Select Low */
  108. #define CL_GR35 0x35 /* Transparent Color Select High */
  109. #define CL_GR38 0x38 /* Source Transparent Color Mask Low */
  110. #define CL_GR39 0x39 /* Source Transparent Color Mask High */
  111. /*** Attribute Controller Registers ***/
  112. #define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */
  113. #define CL_AR34 0x34 /* TEST */
  114. #endif /* __CLGENFB_H__ */