ymfpci.h 11 KB

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  1. #ifndef __SOUND_YMFPCI_H
  2. #define __SOUND_YMFPCI_H
  3. /*
  4. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
  5. * Definitions for Yahama YMF724/740/744/754 chips
  6. *
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. *
  22. */
  23. #include "pcm.h"
  24. #include "rawmidi.h"
  25. #include "ac97_codec.h"
  26. #include "timer.h"
  27. #include <linux/gameport.h>
  28. /*
  29. * Direct registers
  30. */
  31. #define YMFREG(chip, reg) (chip->port + YDSXGR_##reg)
  32. #define YDSXGR_INTFLAG 0x0004
  33. #define YDSXGR_ACTIVITY 0x0006
  34. #define YDSXGR_GLOBALCTRL 0x0008
  35. #define YDSXGR_ZVCTRL 0x000A
  36. #define YDSXGR_TIMERCTRL 0x0010
  37. #define YDSXGR_TIMERCOUNT 0x0012
  38. #define YDSXGR_SPDIFOUTCTRL 0x0018
  39. #define YDSXGR_SPDIFOUTSTATUS 0x001C
  40. #define YDSXGR_EEPROMCTRL 0x0020
  41. #define YDSXGR_SPDIFINCTRL 0x0034
  42. #define YDSXGR_SPDIFINSTATUS 0x0038
  43. #define YDSXGR_DSPPROGRAMDL 0x0048
  44. #define YDSXGR_DLCNTRL 0x004C
  45. #define YDSXGR_GPIOININTFLAG 0x0050
  46. #define YDSXGR_GPIOININTENABLE 0x0052
  47. #define YDSXGR_GPIOINSTATUS 0x0054
  48. #define YDSXGR_GPIOOUTCTRL 0x0056
  49. #define YDSXGR_GPIOFUNCENABLE 0x0058
  50. #define YDSXGR_GPIOTYPECONFIG 0x005A
  51. #define YDSXGR_AC97CMDDATA 0x0060
  52. #define YDSXGR_AC97CMDADR 0x0062
  53. #define YDSXGR_PRISTATUSDATA 0x0064
  54. #define YDSXGR_PRISTATUSADR 0x0066
  55. #define YDSXGR_SECSTATUSDATA 0x0068
  56. #define YDSXGR_SECSTATUSADR 0x006A
  57. #define YDSXGR_SECCONFIG 0x0070
  58. #define YDSXGR_LEGACYOUTVOL 0x0080
  59. #define YDSXGR_LEGACYOUTVOLL 0x0080
  60. #define YDSXGR_LEGACYOUTVOLR 0x0082
  61. #define YDSXGR_NATIVEDACOUTVOL 0x0084
  62. #define YDSXGR_NATIVEDACOUTVOLL 0x0084
  63. #define YDSXGR_NATIVEDACOUTVOLR 0x0086
  64. #define YDSXGR_ZVOUTVOL 0x0088
  65. #define YDSXGR_ZVOUTVOLL 0x0088
  66. #define YDSXGR_ZVOUTVOLR 0x008A
  67. #define YDSXGR_SECADCOUTVOL 0x008C
  68. #define YDSXGR_SECADCOUTVOLL 0x008C
  69. #define YDSXGR_SECADCOUTVOLR 0x008E
  70. #define YDSXGR_PRIADCOUTVOL 0x0090
  71. #define YDSXGR_PRIADCOUTVOLL 0x0090
  72. #define YDSXGR_PRIADCOUTVOLR 0x0092
  73. #define YDSXGR_LEGACYLOOPVOL 0x0094
  74. #define YDSXGR_LEGACYLOOPVOLL 0x0094
  75. #define YDSXGR_LEGACYLOOPVOLR 0x0096
  76. #define YDSXGR_NATIVEDACLOOPVOL 0x0098
  77. #define YDSXGR_NATIVEDACLOOPVOLL 0x0098
  78. #define YDSXGR_NATIVEDACLOOPVOLR 0x009A
  79. #define YDSXGR_ZVLOOPVOL 0x009C
  80. #define YDSXGR_ZVLOOPVOLL 0x009E
  81. #define YDSXGR_ZVLOOPVOLR 0x009E
  82. #define YDSXGR_SECADCLOOPVOL 0x00A0
  83. #define YDSXGR_SECADCLOOPVOLL 0x00A0
  84. #define YDSXGR_SECADCLOOPVOLR 0x00A2
  85. #define YDSXGR_PRIADCLOOPVOL 0x00A4
  86. #define YDSXGR_PRIADCLOOPVOLL 0x00A4
  87. #define YDSXGR_PRIADCLOOPVOLR 0x00A6
  88. #define YDSXGR_NATIVEADCINVOL 0x00A8
  89. #define YDSXGR_NATIVEADCINVOLL 0x00A8
  90. #define YDSXGR_NATIVEADCINVOLR 0x00AA
  91. #define YDSXGR_NATIVEDACINVOL 0x00AC
  92. #define YDSXGR_NATIVEDACINVOLL 0x00AC
  93. #define YDSXGR_NATIVEDACINVOLR 0x00AE
  94. #define YDSXGR_BUF441OUTVOL 0x00B0
  95. #define YDSXGR_BUF441OUTVOLL 0x00B0
  96. #define YDSXGR_BUF441OUTVOLR 0x00B2
  97. #define YDSXGR_BUF441LOOPVOL 0x00B4
  98. #define YDSXGR_BUF441LOOPVOLL 0x00B4
  99. #define YDSXGR_BUF441LOOPVOLR 0x00B6
  100. #define YDSXGR_SPDIFOUTVOL 0x00B8
  101. #define YDSXGR_SPDIFOUTVOLL 0x00B8
  102. #define YDSXGR_SPDIFOUTVOLR 0x00BA
  103. #define YDSXGR_SPDIFLOOPVOL 0x00BC
  104. #define YDSXGR_SPDIFLOOPVOLL 0x00BC
  105. #define YDSXGR_SPDIFLOOPVOLR 0x00BE
  106. #define YDSXGR_ADCSLOTSR 0x00C0
  107. #define YDSXGR_RECSLOTSR 0x00C4
  108. #define YDSXGR_ADCFORMAT 0x00C8
  109. #define YDSXGR_RECFORMAT 0x00CC
  110. #define YDSXGR_P44SLOTSR 0x00D0
  111. #define YDSXGR_STATUS 0x0100
  112. #define YDSXGR_CTRLSELECT 0x0104
  113. #define YDSXGR_MODE 0x0108
  114. #define YDSXGR_SAMPLECOUNT 0x010C
  115. #define YDSXGR_NUMOFSAMPLES 0x0110
  116. #define YDSXGR_CONFIG 0x0114
  117. #define YDSXGR_PLAYCTRLSIZE 0x0140
  118. #define YDSXGR_RECCTRLSIZE 0x0144
  119. #define YDSXGR_EFFCTRLSIZE 0x0148
  120. #define YDSXGR_WORKSIZE 0x014C
  121. #define YDSXGR_MAPOFREC 0x0150
  122. #define YDSXGR_MAPOFEFFECT 0x0154
  123. #define YDSXGR_PLAYCTRLBASE 0x0158
  124. #define YDSXGR_RECCTRLBASE 0x015C
  125. #define YDSXGR_EFFCTRLBASE 0x0160
  126. #define YDSXGR_WORKBASE 0x0164
  127. #define YDSXGR_DSPINSTRAM 0x1000
  128. #define YDSXGR_CTRLINSTRAM 0x4000
  129. #define YDSXG_AC97READCMD 0x8000
  130. #define YDSXG_AC97WRITECMD 0x0000
  131. #define PCIR_DSXG_LEGACY 0x40
  132. #define PCIR_DSXG_ELEGACY 0x42
  133. #define PCIR_DSXG_CTRL 0x48
  134. #define PCIR_DSXG_PWRCTRL1 0x4a
  135. #define PCIR_DSXG_PWRCTRL2 0x4e
  136. #define PCIR_DSXG_FMBASE 0x60
  137. #define PCIR_DSXG_SBBASE 0x62
  138. #define PCIR_DSXG_MPU401BASE 0x64
  139. #define PCIR_DSXG_JOYBASE 0x66
  140. #define YDSXG_DSPLENGTH 0x0080
  141. #define YDSXG_CTRLLENGTH 0x3000
  142. #define YDSXG_DEFAULT_WORK_SIZE 0x0400
  143. #define YDSXG_PLAYBACK_VOICES 64
  144. #define YDSXG_CAPTURE_VOICES 2
  145. #define YDSXG_EFFECT_VOICES 5
  146. #define YMFPCI_LEGACY_SBEN (1 << 0) /* soundblaster enable */
  147. #define YMFPCI_LEGACY_FMEN (1 << 1) /* OPL3 enable */
  148. #define YMFPCI_LEGACY_JPEN (1 << 2) /* joystick enable */
  149. #define YMFPCI_LEGACY_MEN (1 << 3) /* MPU401 enable */
  150. #define YMFPCI_LEGACY_MIEN (1 << 4) /* MPU RX irq enable */
  151. #define YMFPCI_LEGACY_IOBITS (1 << 5) /* i/o bits range, 0 = 16bit, 1 =10bit */
  152. #define YMFPCI_LEGACY_SDMA (3 << 6) /* SB DMA select */
  153. #define YMFPCI_LEGACY_SBIRQ (7 << 8) /* SB IRQ select */
  154. #define YMFPCI_LEGACY_MPUIRQ (7 << 11) /* MPU IRQ select */
  155. #define YMFPCI_LEGACY_SIEN (1 << 14) /* serialized IRQ */
  156. #define YMFPCI_LEGACY_LAD (1 << 15) /* legacy audio disable */
  157. #define YMFPCI_LEGACY2_FMIO (3 << 0) /* OPL3 i/o address (724/740) */
  158. #define YMFPCI_LEGACY2_SBIO (3 << 2) /* SB i/o address (724/740) */
  159. #define YMFPCI_LEGACY2_MPUIO (3 << 4) /* MPU401 i/o address (724/740) */
  160. #define YMFPCI_LEGACY2_JSIO (3 << 6) /* joystick i/o address (724/740) */
  161. #define YMFPCI_LEGACY2_MAIM (1 << 8) /* MPU401 ack intr mask */
  162. #define YMFPCI_LEGACY2_SMOD (3 << 11) /* SB DMA mode */
  163. #define YMFPCI_LEGACY2_SBVER (3 << 13) /* SB version select */
  164. #define YMFPCI_LEGACY2_IMOD (1 << 15) /* legacy IRQ mode */
  165. /* SIEN:IMOD 0:0 = legacy irq, 0:1 = INTA, 1:0 = serialized IRQ */
  166. #if defined(CONFIG_GAMEPORT) || (defined(MODULE) && defined(CONFIG_GAMEPORT_MODULE))
  167. #define SUPPORT_JOYSTICK
  168. #endif
  169. /*
  170. *
  171. */
  172. struct snd_ymfpci_playback_bank {
  173. u32 format;
  174. u32 loop_default;
  175. u32 base; /* 32-bit address */
  176. u32 loop_start; /* 32-bit offset */
  177. u32 loop_end; /* 32-bit offset */
  178. u32 loop_frac; /* 8-bit fraction - loop_start */
  179. u32 delta_end; /* pitch delta end */
  180. u32 lpfK_end;
  181. u32 eg_gain_end;
  182. u32 left_gain_end;
  183. u32 right_gain_end;
  184. u32 eff1_gain_end;
  185. u32 eff2_gain_end;
  186. u32 eff3_gain_end;
  187. u32 lpfQ;
  188. u32 status;
  189. u32 num_of_frames;
  190. u32 loop_count;
  191. u32 start;
  192. u32 start_frac;
  193. u32 delta;
  194. u32 lpfK;
  195. u32 eg_gain;
  196. u32 left_gain;
  197. u32 right_gain;
  198. u32 eff1_gain;
  199. u32 eff2_gain;
  200. u32 eff3_gain;
  201. u32 lpfD1;
  202. u32 lpfD2;
  203. };
  204. struct snd_ymfpci_capture_bank {
  205. u32 base; /* 32-bit address */
  206. u32 loop_end; /* 32-bit offset */
  207. u32 start; /* 32-bit offset */
  208. u32 num_of_loops; /* counter */
  209. };
  210. struct snd_ymfpci_effect_bank {
  211. u32 base; /* 32-bit address */
  212. u32 loop_end; /* 32-bit offset */
  213. u32 start; /* 32-bit offset */
  214. u32 temp;
  215. };
  216. struct snd_ymfpci_pcm;
  217. struct snd_ymfpci;
  218. enum snd_ymfpci_voice_type {
  219. YMFPCI_PCM,
  220. YMFPCI_SYNTH,
  221. YMFPCI_MIDI
  222. };
  223. struct snd_ymfpci_voice {
  224. struct snd_ymfpci *chip;
  225. int number;
  226. unsigned int use: 1,
  227. pcm: 1,
  228. synth: 1,
  229. midi: 1;
  230. struct snd_ymfpci_playback_bank *bank;
  231. dma_addr_t bank_addr;
  232. void (*interrupt)(struct snd_ymfpci *chip, struct snd_ymfpci_voice *voice);
  233. struct snd_ymfpci_pcm *ypcm;
  234. };
  235. enum snd_ymfpci_pcm_type {
  236. PLAYBACK_VOICE,
  237. CAPTURE_REC,
  238. CAPTURE_AC97,
  239. EFFECT_DRY_LEFT,
  240. EFFECT_DRY_RIGHT,
  241. EFFECT_EFF1,
  242. EFFECT_EFF2,
  243. EFFECT_EFF3
  244. };
  245. struct snd_ymfpci_pcm {
  246. struct snd_ymfpci *chip;
  247. enum snd_ymfpci_pcm_type type;
  248. struct snd_pcm_substream *substream;
  249. struct snd_ymfpci_voice *voices[2]; /* playback only */
  250. unsigned int running: 1,
  251. use_441_slot: 1,
  252. output_front: 1,
  253. output_rear: 1,
  254. swap_rear: 1;
  255. unsigned int update_pcm_vol;
  256. u32 period_size; /* cached from runtime->period_size */
  257. u32 buffer_size; /* cached from runtime->buffer_size */
  258. u32 period_pos;
  259. u32 last_pos;
  260. u32 capture_bank_number;
  261. u32 shift;
  262. };
  263. struct snd_ymfpci {
  264. int irq;
  265. unsigned int device_id; /* PCI device ID */
  266. unsigned char rev; /* PCI revision */
  267. unsigned long reg_area_phys;
  268. void __iomem *reg_area_virt;
  269. struct resource *res_reg_area;
  270. struct resource *fm_res;
  271. struct resource *mpu_res;
  272. unsigned short old_legacy_ctrl;
  273. #ifdef SUPPORT_JOYSTICK
  274. struct gameport *gameport;
  275. #endif
  276. struct snd_dma_buffer work_ptr;
  277. unsigned int bank_size_playback;
  278. unsigned int bank_size_capture;
  279. unsigned int bank_size_effect;
  280. unsigned int work_size;
  281. void *bank_base_playback;
  282. void *bank_base_capture;
  283. void *bank_base_effect;
  284. void *work_base;
  285. dma_addr_t bank_base_playback_addr;
  286. dma_addr_t bank_base_capture_addr;
  287. dma_addr_t bank_base_effect_addr;
  288. dma_addr_t work_base_addr;
  289. struct snd_dma_buffer ac3_tmp_base;
  290. u32 *ctrl_playback;
  291. struct snd_ymfpci_playback_bank *bank_playback[YDSXG_PLAYBACK_VOICES][2];
  292. struct snd_ymfpci_capture_bank *bank_capture[YDSXG_CAPTURE_VOICES][2];
  293. struct snd_ymfpci_effect_bank *bank_effect[YDSXG_EFFECT_VOICES][2];
  294. int start_count;
  295. u32 active_bank;
  296. struct snd_ymfpci_voice voices[64];
  297. int src441_used;
  298. struct snd_ac97_bus *ac97_bus;
  299. struct snd_ac97 *ac97;
  300. struct snd_rawmidi *rawmidi;
  301. struct snd_timer *timer;
  302. struct pci_dev *pci;
  303. struct snd_card *card;
  304. struct snd_pcm *pcm;
  305. struct snd_pcm *pcm2;
  306. struct snd_pcm *pcm_spdif;
  307. struct snd_pcm *pcm_4ch;
  308. struct snd_pcm_substream *capture_substream[YDSXG_CAPTURE_VOICES];
  309. struct snd_pcm_substream *effect_substream[YDSXG_EFFECT_VOICES];
  310. struct snd_kcontrol *ctl_vol_recsrc;
  311. struct snd_kcontrol *ctl_vol_adcrec;
  312. struct snd_kcontrol *ctl_vol_spdifrec;
  313. unsigned short spdif_bits, spdif_pcm_bits;
  314. struct snd_kcontrol *spdif_pcm_ctl;
  315. int mode_dup4ch;
  316. int rear_opened;
  317. int spdif_opened;
  318. struct snd_ymfpci_pcm_mixer {
  319. u16 left;
  320. u16 right;
  321. struct snd_kcontrol *ctl;
  322. } pcm_mixer[32];
  323. spinlock_t reg_lock;
  324. spinlock_t voice_lock;
  325. wait_queue_head_t interrupt_sleep;
  326. atomic_t interrupt_sleep_count;
  327. struct snd_info_entry *proc_entry;
  328. const struct firmware *dsp_microcode;
  329. const struct firmware *controller_microcode;
  330. #ifdef CONFIG_PM
  331. u32 *saved_regs;
  332. u32 saved_ydsxgr_mode;
  333. #endif
  334. };
  335. int snd_ymfpci_create(struct snd_card *card,
  336. struct pci_dev *pci,
  337. unsigned short old_legacy_ctrl,
  338. struct snd_ymfpci ** rcodec);
  339. void snd_ymfpci_free_gameport(struct snd_ymfpci *chip);
  340. int snd_ymfpci_suspend(struct pci_dev *pci, pm_message_t state);
  341. int snd_ymfpci_resume(struct pci_dev *pci);
  342. int snd_ymfpci_pcm(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm);
  343. int snd_ymfpci_pcm2(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm);
  344. int snd_ymfpci_pcm_spdif(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm);
  345. int snd_ymfpci_pcm_4ch(struct snd_ymfpci *chip, int device, struct snd_pcm **rpcm);
  346. int snd_ymfpci_mixer(struct snd_ymfpci *chip, int rear_switch);
  347. int snd_ymfpci_timer(struct snd_ymfpci *chip, int device);
  348. #endif /* __SOUND_YMFPCI_H */