emu10k1.h 96 KB

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  1. #ifndef __SOUND_EMU10K1_H
  2. #define __SOUND_EMU10K1_H
  3. /*
  4. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
  5. * Creative Labs, Inc.
  6. * Definitions for EMU10K1 (SB Live!) chips
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #ifdef __KERNEL__
  25. #include <sound/pcm.h>
  26. #include <sound/rawmidi.h>
  27. #include <sound/hwdep.h>
  28. #include <sound/ac97_codec.h>
  29. #include <sound/util_mem.h>
  30. #include <sound/pcm-indirect.h>
  31. #include <sound/timer.h>
  32. #include <linux/interrupt.h>
  33. #include <linux/mutex.h>
  34. #include <asm/io.h>
  35. /* ------------------- DEFINES -------------------- */
  36. #define EMUPAGESIZE 4096
  37. #define MAXREQVOICES 8
  38. #define MAXPAGES 8192
  39. #define RESERVED 0
  40. #define NUM_MIDI 16
  41. #define NUM_G 64 /* use all channels */
  42. #define NUM_FXSENDS 4
  43. #define NUM_EFX_PLAYBACK 16
  44. /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
  45. #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
  46. #define AUDIGY_DMA_MASK 0x7fffffffUL /* 31bit FIXME - 32 should work? */
  47. /* See ALSA bug #1276 - rlrevell */
  48. #define TMEMSIZE 256*1024
  49. #define TMEMSIZEREG 4
  50. #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
  51. // Audigy specify registers are prefixed with 'A_'
  52. /************************************************************************************************/
  53. /* PCI function 0 registers, address = <val> + PCIBASE0 */
  54. /************************************************************************************************/
  55. #define PTR 0x00 /* Indexed register set pointer register */
  56. /* NOTE: The CHANNELNUM and ADDRESS words can */
  57. /* be modified independently of each other. */
  58. #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
  59. /* channel number of the register to be */
  60. /* accessed. For non per-channel registers the */
  61. /* value should be set to zero. */
  62. #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
  63. #define A_PTR_ADDRESS_MASK 0x0fff0000
  64. #define DATA 0x04 /* Indexed register set data register */
  65. #define IPR 0x08 /* Global interrupt pending register */
  66. /* Clear pending interrupts by writing a 1 to */
  67. /* the relevant bits and zero to the other bits */
  68. #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
  69. to interrupt */
  70. #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
  71. which INTE bits enable it) */
  72. /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
  73. #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
  74. #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
  75. #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
  76. #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
  77. #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
  78. #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
  79. #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
  80. #define IPR_PCIERROR 0x00200000 /* PCI bus error */
  81. #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
  82. #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
  83. #define IPR_MUTE 0x00040000 /* Mute button pressed */
  84. #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
  85. #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
  86. #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
  87. #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
  88. #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
  89. #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
  90. #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
  91. #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
  92. #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
  93. #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
  94. #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
  95. #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
  96. #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
  97. /* highest set channel in CLIPL, CLIPH, HLIPL, */
  98. /* or HLIPH. When IP is written with CL set, */
  99. /* the bit in H/CLIPL or H/CLIPH corresponding */
  100. /* to the CIN value written will be cleared. */
  101. #define INTE 0x0c /* Interrupt enable register */
  102. #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
  103. #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
  104. #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
  105. #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
  106. #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
  107. #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
  108. #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
  109. #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
  110. #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
  111. #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
  112. #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
  113. #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
  114. #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
  115. #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
  116. #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
  117. #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
  118. #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
  119. #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
  120. #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
  121. /* NOTE: There is no reason to use this under */
  122. /* Linux, and it will cause odd hardware */
  123. /* behavior and possibly random segfaults and */
  124. /* lockups if enabled. */
  125. /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
  126. #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
  127. #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
  128. #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
  129. /* NOTE: This bit must always be enabled */
  130. #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
  131. #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
  132. #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
  133. #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
  134. #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
  135. #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
  136. #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
  137. #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
  138. #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
  139. #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
  140. #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
  141. #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
  142. #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
  143. #define WC 0x10 /* Wall Clock register */
  144. #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
  145. #define WC_SAMPLECOUNTER 0x14060010
  146. #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
  147. /* NOTE: Each channel takes 1/64th of a sample */
  148. /* period to be serviced. */
  149. #define HCFG 0x14 /* Hardware config register */
  150. /* NOTE: There is no reason to use the legacy */
  151. /* SoundBlaster emulation stuff described below */
  152. /* under Linux, and all kinds of weird hardware */
  153. /* behavior can result if you try. Don't. */
  154. #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
  155. #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
  156. #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
  157. #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
  158. #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
  159. #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
  160. #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
  161. #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
  162. #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
  163. #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
  164. #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
  165. #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
  166. /* NOTE: The rest of the bits in this register */
  167. /* _are_ relevant under Linux. */
  168. #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
  169. #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
  170. #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
  171. #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
  172. /* Specific to Alice2, CA0102 */
  173. #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
  174. #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
  175. #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
  176. /* will automatically mute their output when */
  177. /* they are not rate-locked to the external */
  178. /* async audio source */
  179. #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
  180. /* will automatically mute their output when */
  181. /* the SPDIF V-bit indicates invalid audio */
  182. #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
  183. #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
  184. /* 0x00000800 not used on Alice2 */
  185. #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
  186. /* phase track the previous input. */
  187. /* I2S0 can phase track the last S/PDIF input */
  188. #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
  189. /* conversion for the corresponding */
  190. /* I2S format input */
  191. /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
  192. /* Older chips */
  193. #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
  194. #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
  195. #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
  196. #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
  197. #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
  198. #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
  199. #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
  200. #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
  201. #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
  202. #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
  203. /* 1 = Force all 3 async digital inputs to use */
  204. /* the same async sample rate tracker (ZVIDEO) */
  205. #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
  206. #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
  207. #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
  208. #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
  209. #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
  210. /* will automatically mute their output when */
  211. /* they are not rate-locked to the external */
  212. /* async audio source */
  213. #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
  214. /* NOTE: This should generally never be used. */
  215. #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
  216. /* NOTE: This should generally never be used. */
  217. #define HCFG_LOCKTANKCACHE 0x01020014
  218. #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
  219. /* NOTE: This is a 'cheap' way to implement a */
  220. /* master mute function on the mute button, and */
  221. /* in general should not be used unless a more */
  222. /* sophisticated master mute function has not */
  223. /* been written. */
  224. #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
  225. /* Should be set to 1 when the EMU10K1 is */
  226. /* completely initialized. */
  227. //For Audigy, MPU port move to 0x70-0x74 ptr register
  228. #define MUDATA 0x18 /* MPU401 data register (8 bits) */
  229. #define MUCMD 0x19 /* MPU401 command register (8 bits) */
  230. #define MUCMD_RESET 0xff /* RESET command */
  231. #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
  232. /* NOTE: All other commands are ignored */
  233. #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
  234. #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
  235. #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
  236. #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
  237. #define A_GPINPUT_MASK 0xff00
  238. #define A_GPOUTPUT_MASK 0x00ff
  239. // Audigy output/GPIO stuff taken from the kX drivers
  240. #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
  241. #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
  242. #define A_IOCFG_ENABLE_DIGITAL 0x0004
  243. #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
  244. #define A_IOCFG_UNKNOWN_20 0x0020
  245. #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
  246. #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
  247. #define A_IOCFG_GPOUT2 0x0001 /* IR */
  248. #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
  249. /* + digital for generic 10k2 */
  250. #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
  251. #define A_IOCFG_FRONT_JACK 0x4000
  252. #define A_IOCFG_REAR_JACK 0x8000
  253. #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
  254. /* outputs:
  255. * for audigy2 platinum: 0xa00
  256. * for a2 platinum ex: 0x1c00
  257. * for a1 platinum: 0x0
  258. */
  259. #define TIMER 0x1a /* Timer terminal count register */
  260. /* NOTE: After the rate is changed, a maximum */
  261. /* of 1024 sample periods should be allowed */
  262. /* before the new rate is guaranteed accurate. */
  263. #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
  264. /* 0 == 1024 periods, [1..4] are not useful */
  265. #define TIMER_RATE 0x0a00001a
  266. #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
  267. #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
  268. #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
  269. #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
  270. /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
  271. #define PTR2 0x20 /* Indexed register set pointer register */
  272. #define DATA2 0x24 /* Indexed register set data register */
  273. #define IPR2 0x28 /* P16V interrupt pending register */
  274. #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
  275. #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
  276. #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
  277. #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
  278. /* 0x00000100 Playback. Only in once per period.
  279. * 0x00110000 Capture. Int on half buffer.
  280. */
  281. #define INTE2 0x2c /* P16V Interrupt enable register. */
  282. #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
  283. #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
  284. #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
  285. #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
  286. #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
  287. #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
  288. #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
  289. #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
  290. #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
  291. #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
  292. #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
  293. /* 0x00000000 2-channel output. */
  294. /* 0x00000200 8-channel output. */
  295. /* 0x00000004 pauses stream/irq fail. */
  296. /* Rest of bits no nothing to sound output */
  297. /* bit 0: Enable P16V audio.
  298. * bit 1: Lock P16V record memory cache.
  299. * bit 2: Lock P16V playback memory cache.
  300. * bit 3: Dummy record insert zero samples.
  301. * bit 8: Record 8-channel in phase.
  302. * bit 9: Playback 8-channel in phase.
  303. * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
  304. * bit 13: Playback mixer enable.
  305. * bit 14: Route SRC48 mixer output to fx engine.
  306. * bit 15: Enable IEEE 1394 chip.
  307. */
  308. #define IPR3 0x38 /* Cdif interrupt pending register */
  309. #define INTE3 0x3c /* Cdif interrupt enable register. */
  310. /************************************************************************************************/
  311. /* PCI function 1 registers, address = <val> + PCIBASE1 */
  312. /************************************************************************************************/
  313. #define JOYSTICK1 0x00 /* Analog joystick port register */
  314. #define JOYSTICK2 0x01 /* Analog joystick port register */
  315. #define JOYSTICK3 0x02 /* Analog joystick port register */
  316. #define JOYSTICK4 0x03 /* Analog joystick port register */
  317. #define JOYSTICK5 0x04 /* Analog joystick port register */
  318. #define JOYSTICK6 0x05 /* Analog joystick port register */
  319. #define JOYSTICK7 0x06 /* Analog joystick port register */
  320. #define JOYSTICK8 0x07 /* Analog joystick port register */
  321. /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
  322. /* When reading, use these bitfields: */
  323. #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
  324. #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
  325. /********************************************************************************************************/
  326. /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
  327. /********************************************************************************************************/
  328. #define CPF 0x00 /* Current pitch and fraction register */
  329. #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
  330. #define CPF_CURRENTPITCH 0x10100000
  331. #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
  332. #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
  333. #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
  334. #define PTRX 0x01 /* Pitch target and send A/B amounts register */
  335. #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
  336. #define PTRX_PITCHTARGET 0x10100001
  337. #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
  338. #define PTRX_FXSENDAMOUNT_A 0x08080001
  339. #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
  340. #define PTRX_FXSENDAMOUNT_B 0x08000001
  341. #define CVCF 0x02 /* Current volume and filter cutoff register */
  342. #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
  343. #define CVCF_CURRENTVOL 0x10100002
  344. #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
  345. #define CVCF_CURRENTFILTER 0x10000002
  346. #define VTFT 0x03 /* Volume target and filter cutoff target register */
  347. #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
  348. #define VTFT_VOLUMETARGET 0x10100003
  349. #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
  350. #define VTFT_FILTERTARGET 0x10000003
  351. #define Z1 0x05 /* Filter delay memory 1 register */
  352. #define Z2 0x04 /* Filter delay memory 2 register */
  353. #define PSST 0x06 /* Send C amount and loop start address register */
  354. #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
  355. #define PSST_FXSENDAMOUNT_C 0x08180006
  356. #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
  357. #define PSST_LOOPSTARTADDR 0x18000006
  358. #define DSL 0x07 /* Send D amount and loop start address register */
  359. #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
  360. #define DSL_FXSENDAMOUNT_D 0x08180007
  361. #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
  362. #define DSL_LOOPENDADDR 0x18000007
  363. #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
  364. #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
  365. #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
  366. /* 1 == full band, 7 == lowpass */
  367. /* ROM 0 is used when pitch shifting downward or less */
  368. /* then 3 semitones upward. Increasingly higher ROM */
  369. /* numbers are used, typically in steps of 3 semitones, */
  370. /* as upward pitch shifting is performed. */
  371. #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
  372. #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
  373. #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
  374. #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
  375. #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
  376. #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
  377. #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
  378. #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
  379. #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
  380. #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
  381. #define CCCA_CURRADDR 0x18000008
  382. #define CCR 0x09 /* Cache control register */
  383. #define CCR_CACHEINVALIDSIZE 0x07190009
  384. #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
  385. #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
  386. #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
  387. #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
  388. #define CCR_READADDRESS 0x06100009
  389. #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
  390. #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
  391. /* NOTE: This is valid only if CACHELOOPFLAG is set */
  392. #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
  393. #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
  394. #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
  395. /* NOTE: This register is normally not used */
  396. #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
  397. #define FXRT 0x0b /* Effects send routing register */
  398. /* NOTE: It is illegal to assign the same routing to */
  399. /* two effects sends. */
  400. #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
  401. #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
  402. #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
  403. #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
  404. #define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
  405. #define MAPA 0x0c /* Cache map A */
  406. #define MAPB 0x0d /* Cache map B */
  407. #define MAP_PTE_MASK 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
  408. #define MAP_PTI_MASK 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
  409. /* 0x0e, 0x0f: Not used */
  410. #define ENVVOL 0x10 /* Volume envelope register */
  411. #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
  412. /* 0x8000-n == 666*n usec delay */
  413. #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
  414. #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
  415. #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
  416. #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
  417. /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
  418. #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
  419. #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
  420. #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
  421. #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
  422. /* this channel and from writing to pitch, filter and */
  423. /* volume targets. */
  424. #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
  425. /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
  426. #define LFOVAL1 0x13 /* Modulation LFO value */
  427. #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
  428. /* 0x8000-n == 666*n usec delay */
  429. #define ENVVAL 0x14 /* Modulation envelope register */
  430. #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
  431. /* 0x8000-n == 666*n usec delay */
  432. #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
  433. #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
  434. #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
  435. #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
  436. /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
  437. #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
  438. #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
  439. #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
  440. #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
  441. /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
  442. #define LFOVAL2 0x17 /* Vibrato LFO register */
  443. #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
  444. /* 0x8000-n == 666*n usec delay */
  445. #define IP 0x18 /* Initial pitch register */
  446. #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
  447. /* 4 bits of octave, 12 bits of fractional octave */
  448. #define IP_UNITY 0x0000e000 /* Unity pitch shift */
  449. #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
  450. #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
  451. /* 6 most significant bits are semitones */
  452. /* 2 least significant bits are fractions */
  453. #define IFATN_FILTERCUTOFF 0x08080019
  454. #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
  455. #define IFATN_ATTENUATION 0x08000019
  456. #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
  457. #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
  458. /* Signed 2's complement, +/- one octave peak extremes */
  459. #define PEFE_PITCHAMOUNT 0x0808001a
  460. #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
  461. /* Signed 2's complement, +/- six octaves peak extremes */
  462. #define PEFE_FILTERAMOUNT 0x0800001a
  463. #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
  464. #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
  465. /* Signed 2's complement, +/- one octave extremes */
  466. #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
  467. /* Signed 2's complement, +/- three octave extremes */
  468. #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
  469. #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
  470. /* Signed 2's complement, with +/- 12dB extremes */
  471. #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
  472. /* ??Hz steps, maximum of ?? Hz. */
  473. #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
  474. #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
  475. /* Signed 2's complement, +/- one octave extremes */
  476. #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
  477. /* 0.039Hz steps, maximum of 9.85 Hz. */
  478. #define TEMPENV 0x1e /* Tempory envelope register */
  479. #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
  480. /* NOTE: All channels contain internal variables; do */
  481. /* not write to these locations. */
  482. /* 0x1f: not used */
  483. #define CD0 0x20 /* Cache data 0 register */
  484. #define CD1 0x21 /* Cache data 1 register */
  485. #define CD2 0x22 /* Cache data 2 register */
  486. #define CD3 0x23 /* Cache data 3 register */
  487. #define CD4 0x24 /* Cache data 4 register */
  488. #define CD5 0x25 /* Cache data 5 register */
  489. #define CD6 0x26 /* Cache data 6 register */
  490. #define CD7 0x27 /* Cache data 7 register */
  491. #define CD8 0x28 /* Cache data 8 register */
  492. #define CD9 0x29 /* Cache data 9 register */
  493. #define CDA 0x2a /* Cache data A register */
  494. #define CDB 0x2b /* Cache data B register */
  495. #define CDC 0x2c /* Cache data C register */
  496. #define CDD 0x2d /* Cache data D register */
  497. #define CDE 0x2e /* Cache data E register */
  498. #define CDF 0x2f /* Cache data F register */
  499. /* 0x30-3f seem to be the same as 0x20-2f */
  500. #define PTB 0x40 /* Page table base register */
  501. #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
  502. #define TCB 0x41 /* Tank cache base register */
  503. #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
  504. #define ADCCR 0x42 /* ADC sample rate/stereo control register */
  505. #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
  506. #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
  507. /* NOTE: To guarantee phase coherency, both channels */
  508. /* must be disabled prior to enabling both channels. */
  509. #define A_ADCCR_RCHANENABLE 0x00000020
  510. #define A_ADCCR_LCHANENABLE 0x00000010
  511. #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
  512. #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
  513. #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
  514. #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
  515. #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
  516. #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
  517. #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
  518. #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
  519. #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
  520. #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
  521. #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
  522. #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
  523. #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
  524. #define FXWC 0x43 /* FX output write channels register */
  525. /* When set, each bit enables the writing of the */
  526. /* corresponding FX output channel (internal registers */
  527. /* 0x20-0x3f) to host memory. This mode of recording */
  528. /* is 16bit, 48KHz only. All 32 channels can be enabled */
  529. /* simultaneously. */
  530. #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
  531. #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
  532. #define FXWC_DEFAULTROUTE_A (1<<12)
  533. #define FXWC_DEFAULTROUTE_D (1<<13)
  534. #define FXWC_ADCLEFT (1<<18)
  535. #define FXWC_CDROMSPDIFLEFT (1<<18)
  536. #define FXWC_ADCRIGHT (1<<19)
  537. #define FXWC_CDROMSPDIFRIGHT (1<<19)
  538. #define FXWC_MIC (1<<20)
  539. #define FXWC_ZOOMLEFT (1<<20)
  540. #define FXWC_ZOOMRIGHT (1<<21)
  541. #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
  542. #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
  543. #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
  544. #define TCBS 0x44 /* Tank cache buffer size register */
  545. #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
  546. #define TCBS_BUFFSIZE_16K 0x00000000
  547. #define TCBS_BUFFSIZE_32K 0x00000001
  548. #define TCBS_BUFFSIZE_64K 0x00000002
  549. #define TCBS_BUFFSIZE_128K 0x00000003
  550. #define TCBS_BUFFSIZE_256K 0x00000004
  551. #define TCBS_BUFFSIZE_512K 0x00000005
  552. #define TCBS_BUFFSIZE_1024K 0x00000006
  553. #define TCBS_BUFFSIZE_2048K 0x00000007
  554. #define MICBA 0x45 /* AC97 microphone buffer address register */
  555. #define MICBA_MASK 0xfffff000 /* 20 bit base address */
  556. #define ADCBA 0x46 /* ADC buffer address register */
  557. #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
  558. #define FXBA 0x47 /* FX Buffer Address */
  559. #define FXBA_MASK 0xfffff000 /* 20 bit base address */
  560. #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
  561. #define MICBS 0x49 /* Microphone buffer size register */
  562. #define ADCBS 0x4a /* ADC buffer size register */
  563. #define FXBS 0x4b /* FX buffer size register */
  564. /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
  565. /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
  566. #define ADCBS_BUFSIZE_NONE 0x00000000
  567. #define ADCBS_BUFSIZE_384 0x00000001
  568. #define ADCBS_BUFSIZE_448 0x00000002
  569. #define ADCBS_BUFSIZE_512 0x00000003
  570. #define ADCBS_BUFSIZE_640 0x00000004
  571. #define ADCBS_BUFSIZE_768 0x00000005
  572. #define ADCBS_BUFSIZE_896 0x00000006
  573. #define ADCBS_BUFSIZE_1024 0x00000007
  574. #define ADCBS_BUFSIZE_1280 0x00000008
  575. #define ADCBS_BUFSIZE_1536 0x00000009
  576. #define ADCBS_BUFSIZE_1792 0x0000000a
  577. #define ADCBS_BUFSIZE_2048 0x0000000b
  578. #define ADCBS_BUFSIZE_2560 0x0000000c
  579. #define ADCBS_BUFSIZE_3072 0x0000000d
  580. #define ADCBS_BUFSIZE_3584 0x0000000e
  581. #define ADCBS_BUFSIZE_4096 0x0000000f
  582. #define ADCBS_BUFSIZE_5120 0x00000010
  583. #define ADCBS_BUFSIZE_6144 0x00000011
  584. #define ADCBS_BUFSIZE_7168 0x00000012
  585. #define ADCBS_BUFSIZE_8192 0x00000013
  586. #define ADCBS_BUFSIZE_10240 0x00000014
  587. #define ADCBS_BUFSIZE_12288 0x00000015
  588. #define ADCBS_BUFSIZE_14366 0x00000016
  589. #define ADCBS_BUFSIZE_16384 0x00000017
  590. #define ADCBS_BUFSIZE_20480 0x00000018
  591. #define ADCBS_BUFSIZE_24576 0x00000019
  592. #define ADCBS_BUFSIZE_28672 0x0000001a
  593. #define ADCBS_BUFSIZE_32768 0x0000001b
  594. #define ADCBS_BUFSIZE_40960 0x0000001c
  595. #define ADCBS_BUFSIZE_49152 0x0000001d
  596. #define ADCBS_BUFSIZE_57344 0x0000001e
  597. #define ADCBS_BUFSIZE_65536 0x0000001f
  598. /* Current Send B, A Amounts */
  599. #define A_CSBA 0x4c
  600. /* Current Send D, C Amounts */
  601. #define A_CSDC 0x4d
  602. /* Current Send F, E Amounts */
  603. #define A_CSFE 0x4e
  604. /* Current Send H, G Amounts */
  605. #define A_CSHG 0x4f
  606. #define CDCS 0x50 /* CD-ROM digital channel status register */
  607. #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
  608. #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
  609. /* S/PDIF Input C Channel Status */
  610. #define A_SPSC 0x52
  611. #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
  612. #define A_DBG 0x53
  613. #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
  614. #define A_DBG_ZC 0x40000000 /* zero tram counter */
  615. #define A_DBG_STEP_ADDR 0x000003ff
  616. #define A_DBG_SATURATION_OCCURED 0x20000000
  617. #define A_DBG_SATURATION_ADDR 0x0ffc0000
  618. // NOTE: 0x54,55,56: 64-bit
  619. #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
  620. #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
  621. #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
  622. #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
  623. #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
  624. #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
  625. #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
  626. #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
  627. #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
  628. #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
  629. #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
  630. #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
  631. #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
  632. #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
  633. #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
  634. #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
  635. #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
  636. #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
  637. #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
  638. #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
  639. #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
  640. #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
  641. #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
  642. #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
  643. #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
  644. #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
  645. /* 0x57: Not used */
  646. /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
  647. #define CLIEL 0x58 /* Channel loop interrupt enable low register */
  648. #define CLIEH 0x59 /* Channel loop interrupt enable high register */
  649. #define CLIPL 0x5a /* Channel loop interrupt pending low register */
  650. #define CLIPH 0x5b /* Channel loop interrupt pending high register */
  651. #define SOLEL 0x5c /* Stop on loop enable low register */
  652. #define SOLEH 0x5d /* Stop on loop enable high register */
  653. #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
  654. #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
  655. #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
  656. /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
  657. #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
  658. #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
  659. #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
  660. #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
  661. #define AC97SLOT_CNTR 0x10 /* Center enable */
  662. #define AC97SLOT_LFE 0x20 /* LFE enable */
  663. /* PCB Revision */
  664. #define A_PCB 0x5f
  665. // NOTE: 0x60,61,62: 64-bit
  666. #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
  667. #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
  668. #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
  669. /* NOTE: This one has no SPDIFLOCKED field */
  670. /* Assumes sample lock */
  671. /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
  672. #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
  673. #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
  674. #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
  675. #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
  676. /* Note that these values can vary +/- by a small amount */
  677. #define SRCS_SPDIFRATE_44 0x0003acd9
  678. #define SRCS_SPDIFRATE_48 0x00040000
  679. #define SRCS_SPDIFRATE_96 0x00080000
  680. #define MICIDX 0x63 /* Microphone recording buffer index register */
  681. #define MICIDX_MASK 0x0000ffff /* 16-bit value */
  682. #define MICIDX_IDX 0x10000063
  683. #define ADCIDX 0x64 /* ADC recording buffer index register */
  684. #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
  685. #define ADCIDX_IDX 0x10000064
  686. #define A_ADCIDX 0x63
  687. #define A_ADCIDX_IDX 0x10000063
  688. #define A_MICIDX 0x64
  689. #define A_MICIDX_IDX 0x10000064
  690. #define FXIDX 0x65 /* FX recording buffer index register */
  691. #define FXIDX_MASK 0x0000ffff /* 16-bit value */
  692. #define FXIDX_IDX 0x10000065
  693. /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
  694. #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
  695. #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
  696. #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
  697. #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
  698. /* S/PDIF Host Record Index (bypasses SRC) */
  699. #define A_SPRI 0x6a
  700. /* S/PDIF Host Record Address */
  701. #define A_SPRA 0x6b
  702. /* S/PDIF Host Record Control */
  703. #define A_SPRC 0x6c
  704. /* Delayed Interrupt Counter & Enable */
  705. #define A_DICE 0x6d
  706. /* Tank Table Base */
  707. #define A_TTB 0x6e
  708. /* Tank Delay Offset */
  709. #define A_TDOF 0x6f
  710. /* This is the MPU port on the card (via the game port) */
  711. #define A_MUDATA1 0x70
  712. #define A_MUCMD1 0x71
  713. #define A_MUSTAT1 A_MUCMD1
  714. /* This is the MPU port on the Audigy Drive */
  715. #define A_MUDATA2 0x72
  716. #define A_MUCMD2 0x73
  717. #define A_MUSTAT2 A_MUCMD2
  718. /* The next two are the Audigy equivalent of FXWC */
  719. /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
  720. /* Each bit selects a channel for recording */
  721. #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
  722. #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
  723. /* Extended Hardware Control */
  724. #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
  725. #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
  726. #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
  727. #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
  728. #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
  729. #define A_SPDIF_48000 0x00000000
  730. #define A_SPDIF_192000 0x00000020
  731. #define A_SPDIF_96000 0x00000040
  732. #define A_SPDIF_44100 0x00000080
  733. #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
  734. #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
  735. #define A_I2S_CAPTURE_192000 0x00000200
  736. #define A_I2S_CAPTURE_96000 0x00000400
  737. #define A_I2S_CAPTURE_44100 0x00000800
  738. #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
  739. #define A_PCM_48000 0x00000000
  740. #define A_PCM_192000 0x00002000
  741. #define A_PCM_96000 0x00004000
  742. #define A_PCM_44100 0x00008000
  743. /* I2S0 Sample Rate Tracker Status */
  744. #define A_SRT3 0x77
  745. /* I2S1 Sample Rate Tracker Status */
  746. #define A_SRT4 0x78
  747. /* I2S2 Sample Rate Tracker Status */
  748. #define A_SRT5 0x79
  749. /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
  750. /* Tank Table DMA Address */
  751. #define A_TTDA 0x7a
  752. /* Tank Table DMA Data */
  753. #define A_TTDD 0x7b
  754. #define A_FXRT2 0x7c
  755. #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
  756. #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
  757. #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
  758. #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
  759. #define A_SENDAMOUNTS 0x7d
  760. #define A_FXSENDAMOUNT_E_MASK 0xFF000000
  761. #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
  762. #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
  763. #define A_FXSENDAMOUNT_H_MASK 0x000000FF
  764. /* 0x7c, 0x7e "high bit is used for filtering" */
  765. /* The send amounts for this one are the same as used with the emu10k1 */
  766. #define A_FXRT1 0x7e
  767. #define A_FXRT_CHANNELA 0x0000003f
  768. #define A_FXRT_CHANNELB 0x00003f00
  769. #define A_FXRT_CHANNELC 0x003f0000
  770. #define A_FXRT_CHANNELD 0x3f000000
  771. /* 0x7f: Not used */
  772. /* Each FX general purpose register is 32 bits in length, all bits are used */
  773. #define FXGPREGBASE 0x100 /* FX general purpose registers base */
  774. #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
  775. #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
  776. #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
  777. /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
  778. /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
  779. /* locations are for external TRAM. */
  780. #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
  781. #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
  782. /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
  783. #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
  784. #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
  785. #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
  786. #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
  787. #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
  788. #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
  789. #define MICROCODEBASE 0x400 /* Microcode data base address */
  790. /* Each DSP microcode instruction is mapped into 2 doublewords */
  791. /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
  792. #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
  793. #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
  794. #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
  795. #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
  796. #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
  797. /* Audigy Soundcard have a different instruction format */
  798. #define A_MICROCODEBASE 0x600
  799. #define A_LOWORD_OPY_MASK 0x000007ff
  800. #define A_LOWORD_OPX_MASK 0x007ff000
  801. #define A_HIWORD_OPCODE_MASK 0x0f000000
  802. #define A_HIWORD_RESULT_MASK 0x007ff000
  803. #define A_HIWORD_OPA_MASK 0x000007ff
  804. /************************************************************************************************/
  805. /* EMU1010m HANA FPGA registers */
  806. /************************************************************************************************/
  807. #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
  808. #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
  809. #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
  810. #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
  811. #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
  812. #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
  813. #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
  814. /* Must be written after power on to reset DLL */
  815. /* One is unable to detect the Audio dock without this */
  816. #define EMU_HANA_WCLOCK_SRC_MASK 0x07
  817. #define EMU_HANA_WCLOCK_INT_48K 0x00
  818. #define EMU_HANA_WCLOCK_INT_44_1K 0x01
  819. #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
  820. #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
  821. #define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
  822. #define EMU_HANA_WCLOCK_2ND_HANA 0x05
  823. #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
  824. #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
  825. #define EMU_HANA_WCLOCK_MULT_MASK 0x18
  826. #define EMU_HANA_WCLOCK_1X 0x00
  827. #define EMU_HANA_WCLOCK_2X 0x08
  828. #define EMU_HANA_WCLOCK_4X 0x10
  829. #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
  830. #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
  831. #define EMU_HANA_DEFCLOCK_48K 0x00
  832. #define EMU_HANA_DEFCLOCK_44_1K 0x01
  833. #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
  834. #define EMU_MUTE 0x00
  835. #define EMU_UNMUTE 0x01
  836. #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
  837. #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
  838. #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
  839. #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
  840. #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
  841. #define EMU_HANA_IRQ_ADAT 0x02
  842. #define EMU_HANA_IRQ_DOCK 0x04
  843. #define EMU_HANA_IRQ_DOCK_LOST 0x08
  844. #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
  845. #define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
  846. #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
  847. #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
  848. #define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
  849. #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
  850. #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
  851. #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
  852. #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
  853. #define EMU_HANA_OPTICAL_IN_SPDIF 0x00
  854. #define EMU_HANA_OPTICAL_IN_ADAT 0x01
  855. #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
  856. #define EMU_HANA_OPTICAL_OUT_ADAT 0x02
  857. #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
  858. #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
  859. #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
  860. #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
  861. #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
  862. #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
  863. #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
  864. #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
  865. #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
  866. #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
  867. #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
  868. #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
  869. #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
  870. #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
  871. #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
  872. #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
  873. #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
  874. #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
  875. #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
  876. #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
  877. #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
  878. #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
  879. #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
  880. #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
  881. #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
  882. #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
  883. #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
  884. #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
  885. #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
  886. #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
  887. #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
  888. #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
  889. #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
  890. #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
  891. #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
  892. #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
  893. #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
  894. #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
  895. #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
  896. #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
  897. #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
  898. #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
  899. #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
  900. #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
  901. #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
  902. #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
  903. #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
  904. #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
  905. /* 0x14 - 0x1f Unused R/W registers */
  906. #define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
  907. #if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
  908. #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
  909. #define EMU_HANA_IRQ_ADAT 0x02
  910. #define EMU_HANA_IRQ_DOCK 0x04
  911. #define EMU_HANA_IRQ_DOCK_LOST 0x08
  912. #endif
  913. #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
  914. #define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
  915. #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
  916. #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
  917. #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
  918. #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
  919. #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
  920. #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
  921. #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
  922. #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
  923. #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
  924. #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
  925. #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
  926. #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
  927. #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
  928. #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
  929. #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
  930. #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
  931. #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
  932. #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
  933. #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
  934. /* 0x30 - 0x3f Unused Read only registers */
  935. /************************************************************************************************/
  936. /* EMU1010m HANA Destinations */
  937. /************************************************************************************************/
  938. #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
  939. #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  940. #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  941. #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  942. #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  943. #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  944. #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  945. #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  946. #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  947. #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  948. #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
  949. #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
  950. #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
  951. #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
  952. #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
  953. #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
  954. #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
  955. #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
  956. #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
  957. #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
  958. #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
  959. #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
  960. #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
  961. #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
  962. #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
  963. #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
  964. #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
  965. #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
  966. #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
  967. #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
  968. #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
  969. #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
  970. #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
  971. #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
  972. #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
  973. #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
  974. #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
  975. #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
  976. #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
  977. #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
  978. #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
  979. #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
  980. #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
  981. #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
  982. #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
  983. #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
  984. #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
  985. #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
  986. #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
  987. #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
  988. #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
  989. #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
  990. #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
  991. #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
  992. #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
  993. #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
  994. #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
  995. #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
  996. #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
  997. #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
  998. #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
  999. #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
  1000. #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
  1001. #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
  1002. #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
  1003. #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
  1004. #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
  1005. #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
  1006. #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
  1007. #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
  1008. #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
  1009. #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
  1010. #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
  1011. #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
  1012. #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
  1013. /************************************************************************************************/
  1014. /* EMU1010m HANA Sources */
  1015. /************************************************************************************************/
  1016. #define EMU_SRC_SILENCE 0x0000 /* Silence */
  1017. #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
  1018. #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
  1019. #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
  1020. #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
  1021. #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
  1022. #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
  1023. #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
  1024. #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
  1025. #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
  1026. #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
  1027. #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
  1028. #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
  1029. #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
  1030. #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
  1031. #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
  1032. #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
  1033. #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
  1034. #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
  1035. #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
  1036. #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
  1037. #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
  1038. #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
  1039. #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
  1040. #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
  1041. #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
  1042. #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
  1043. #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
  1044. #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
  1045. #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
  1046. #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
  1047. #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
  1048. #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
  1049. #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
  1050. #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
  1051. #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
  1052. #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
  1053. #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
  1054. #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
  1055. #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
  1056. #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
  1057. #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
  1058. #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
  1059. #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
  1060. #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
  1061. #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
  1062. #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
  1063. #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
  1064. /* 0x600 and 0x700 no used */
  1065. /* ------------------- STRUCTURES -------------------- */
  1066. enum {
  1067. EMU10K1_EFX,
  1068. EMU10K1_PCM,
  1069. EMU10K1_SYNTH,
  1070. EMU10K1_MIDI
  1071. };
  1072. struct snd_emu10k1;
  1073. struct snd_emu10k1_voice {
  1074. struct snd_emu10k1 *emu;
  1075. int number;
  1076. unsigned int use: 1,
  1077. pcm: 1,
  1078. efx: 1,
  1079. synth: 1,
  1080. midi: 1;
  1081. void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
  1082. struct snd_emu10k1_pcm *epcm;
  1083. };
  1084. enum {
  1085. PLAYBACK_EMUVOICE,
  1086. PLAYBACK_EFX,
  1087. CAPTURE_AC97ADC,
  1088. CAPTURE_AC97MIC,
  1089. CAPTURE_EFX
  1090. };
  1091. struct snd_emu10k1_pcm {
  1092. struct snd_emu10k1 *emu;
  1093. int type;
  1094. struct snd_pcm_substream *substream;
  1095. struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
  1096. struct snd_emu10k1_voice *extra;
  1097. unsigned short running;
  1098. unsigned short first_ptr;
  1099. struct snd_util_memblk *memblk;
  1100. unsigned int start_addr;
  1101. unsigned int ccca_start_addr;
  1102. unsigned int capture_ipr; /* interrupt acknowledge mask */
  1103. unsigned int capture_inte; /* interrupt enable mask */
  1104. unsigned int capture_ba_reg; /* buffer address register */
  1105. unsigned int capture_bs_reg; /* buffer size register */
  1106. unsigned int capture_idx_reg; /* buffer index register */
  1107. unsigned int capture_cr_val; /* control value */
  1108. unsigned int capture_cr_val2; /* control value2 (for audigy) */
  1109. unsigned int capture_bs_val; /* buffer size value */
  1110. unsigned int capture_bufsize; /* buffer size in bytes */
  1111. };
  1112. struct snd_emu10k1_pcm_mixer {
  1113. /* mono, left, right x 8 sends (4 on emu10k1) */
  1114. unsigned char send_routing[3][8];
  1115. unsigned char send_volume[3][8];
  1116. unsigned short attn[3];
  1117. struct snd_emu10k1_pcm *epcm;
  1118. };
  1119. #define snd_emu10k1_compose_send_routing(route) \
  1120. ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
  1121. #define snd_emu10k1_compose_audigy_fxrt1(route) \
  1122. ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
  1123. #define snd_emu10k1_compose_audigy_fxrt2(route) \
  1124. ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
  1125. struct snd_emu10k1_memblk {
  1126. struct snd_util_memblk mem;
  1127. /* private part */
  1128. int first_page, last_page, pages, mapped_page;
  1129. unsigned int map_locked;
  1130. struct list_head mapped_link;
  1131. struct list_head mapped_order_link;
  1132. };
  1133. #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
  1134. #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
  1135. struct snd_emu10k1_fx8010_ctl {
  1136. struct list_head list; /* list link container */
  1137. unsigned int vcount;
  1138. unsigned int count; /* count of GPR (1..16) */
  1139. unsigned short gpr[32]; /* GPR number(s) */
  1140. unsigned int value[32];
  1141. unsigned int min; /* minimum range */
  1142. unsigned int max; /* maximum range */
  1143. unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
  1144. struct snd_kcontrol *kcontrol;
  1145. };
  1146. typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
  1147. struct snd_emu10k1_fx8010_irq {
  1148. struct snd_emu10k1_fx8010_irq *next;
  1149. snd_fx8010_irq_handler_t *handler;
  1150. unsigned short gpr_running;
  1151. void *private_data;
  1152. };
  1153. struct snd_emu10k1_fx8010_pcm {
  1154. unsigned int valid: 1,
  1155. opened: 1,
  1156. active: 1;
  1157. unsigned int channels; /* 16-bit channels count */
  1158. unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
  1159. unsigned int buffer_size; /* count of buffered samples */
  1160. unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
  1161. unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
  1162. unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
  1163. unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
  1164. unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
  1165. unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
  1166. unsigned char etram[32]; /* external TRAM address & data */
  1167. struct snd_pcm_indirect pcm_rec;
  1168. unsigned int tram_pos;
  1169. unsigned int tram_shift;
  1170. struct snd_emu10k1_fx8010_irq *irq;
  1171. };
  1172. struct snd_emu10k1_fx8010 {
  1173. unsigned short fxbus_mask; /* used FX buses (bitmask) */
  1174. unsigned short extin_mask; /* used external inputs (bitmask) */
  1175. unsigned short extout_mask; /* used external outputs (bitmask) */
  1176. unsigned short pad1;
  1177. unsigned int itram_size; /* internal TRAM size in samples */
  1178. struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
  1179. unsigned int dbg; /* FX debugger register */
  1180. unsigned char name[128];
  1181. int gpr_size; /* size of allocated GPR controls */
  1182. int gpr_count; /* count of used kcontrols */
  1183. struct list_head gpr_ctl; /* GPR controls */
  1184. struct mutex lock;
  1185. struct snd_emu10k1_fx8010_pcm pcm[8];
  1186. spinlock_t irq_lock;
  1187. struct snd_emu10k1_fx8010_irq *irq_handlers;
  1188. };
  1189. #define emu10k1_gpr_ctl(n) list_entry(n, struct snd_emu10k1_fx8010_ctl, list)
  1190. struct snd_emu10k1_midi {
  1191. struct snd_emu10k1 *emu;
  1192. struct snd_rawmidi *rmidi;
  1193. struct snd_rawmidi_substream *substream_input;
  1194. struct snd_rawmidi_substream *substream_output;
  1195. unsigned int midi_mode;
  1196. spinlock_t input_lock;
  1197. spinlock_t output_lock;
  1198. spinlock_t open_lock;
  1199. int tx_enable, rx_enable;
  1200. int port;
  1201. int ipr_tx, ipr_rx;
  1202. void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
  1203. };
  1204. struct snd_emu_chip_details {
  1205. u32 vendor;
  1206. u32 device;
  1207. u32 subsystem;
  1208. unsigned char revision;
  1209. unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
  1210. unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
  1211. unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
  1212. unsigned char ca0108_chip; /* Audigy 2 Value */
  1213. unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
  1214. unsigned char ca0151_chip; /* P16V */
  1215. unsigned char spk71; /* Has 7.1 speakers */
  1216. unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
  1217. unsigned char spdif_bug; /* Has Spdif phasing bug */
  1218. unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
  1219. unsigned char ecard; /* APS EEPROM */
  1220. unsigned char emu1010; /* EMU 1010m card */
  1221. unsigned char spi_dac; /* SPI interface for DAC */
  1222. unsigned char i2c_adc; /* I2C interface for ADC */
  1223. unsigned char adc_1361t; /* Use Philips 1361T ADC */
  1224. const char *driver;
  1225. const char *name;
  1226. const char *id; /* for backward compatibility - can be NULL if not needed */
  1227. };
  1228. struct snd_emu1010 {
  1229. unsigned int output_source[64];
  1230. unsigned int input_source[64];
  1231. unsigned int adc_pads; /* bit mask */
  1232. unsigned int dac_pads; /* bit mask */
  1233. unsigned int internal_clock; /* 44100 or 48000 */
  1234. };
  1235. struct snd_emu10k1 {
  1236. int irq;
  1237. unsigned long port; /* I/O port number */
  1238. unsigned int tos_link: 1, /* tos link detected */
  1239. rear_ac97: 1, /* rear channels are on AC'97 */
  1240. enable_ir: 1;
  1241. unsigned int support_tlv :1;
  1242. /* Contains profile of card capabilities */
  1243. const struct snd_emu_chip_details *card_capabilities;
  1244. unsigned int audigy; /* is Audigy? */
  1245. unsigned int revision; /* chip revision */
  1246. unsigned int serial; /* serial number */
  1247. unsigned short model; /* subsystem id */
  1248. unsigned int card_type; /* EMU10K1_CARD_* */
  1249. unsigned int ecard_ctrl; /* ecard control bits */
  1250. unsigned long dma_mask; /* PCI DMA mask */
  1251. int max_cache_pages; /* max memory size / PAGE_SIZE */
  1252. struct snd_dma_buffer silent_page; /* silent page */
  1253. struct snd_dma_buffer ptb_pages; /* page table pages */
  1254. struct snd_dma_device p16v_dma_dev;
  1255. struct snd_dma_buffer p16v_buffer;
  1256. struct snd_util_memhdr *memhdr; /* page allocation list */
  1257. struct snd_emu10k1_memblk *reserved_page; /* reserved page */
  1258. struct list_head mapped_link_head;
  1259. struct list_head mapped_order_link_head;
  1260. void **page_ptr_table;
  1261. unsigned long *page_addr_table;
  1262. spinlock_t memblk_lock;
  1263. unsigned int spdif_bits[3]; /* s/pdif out setup */
  1264. unsigned int i2c_capture_source;
  1265. u8 i2c_capture_volume[4][2];
  1266. struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
  1267. int gpr_base;
  1268. struct snd_ac97 *ac97;
  1269. struct pci_dev *pci;
  1270. struct snd_card *card;
  1271. struct snd_pcm *pcm;
  1272. struct snd_pcm *pcm_mic;
  1273. struct snd_pcm *pcm_efx;
  1274. struct snd_pcm *pcm_multi;
  1275. struct snd_pcm *pcm_p16v;
  1276. spinlock_t synth_lock;
  1277. void *synth;
  1278. int (*get_synth_voice)(struct snd_emu10k1 *emu);
  1279. spinlock_t reg_lock;
  1280. spinlock_t emu_lock;
  1281. spinlock_t voice_lock;
  1282. struct snd_emu10k1_voice voices[NUM_G];
  1283. struct snd_emu10k1_voice p16v_voices[4];
  1284. struct snd_emu10k1_voice p16v_capture_voice;
  1285. int p16v_device_offset;
  1286. u32 p16v_capture_source;
  1287. u32 p16v_capture_channel;
  1288. struct snd_emu1010 emu1010;
  1289. struct snd_emu10k1_pcm_mixer pcm_mixer[32];
  1290. struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
  1291. struct snd_kcontrol *ctl_send_routing;
  1292. struct snd_kcontrol *ctl_send_volume;
  1293. struct snd_kcontrol *ctl_attn;
  1294. struct snd_kcontrol *ctl_efx_send_routing;
  1295. struct snd_kcontrol *ctl_efx_send_volume;
  1296. struct snd_kcontrol *ctl_efx_attn;
  1297. void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
  1298. void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
  1299. void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
  1300. void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
  1301. void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
  1302. void (*dsp_interrupt)(struct snd_emu10k1 *emu);
  1303. struct snd_pcm_substream *pcm_capture_substream;
  1304. struct snd_pcm_substream *pcm_capture_mic_substream;
  1305. struct snd_pcm_substream *pcm_capture_efx_substream;
  1306. struct snd_pcm_substream *pcm_playback_efx_substream;
  1307. struct snd_timer *timer;
  1308. struct snd_emu10k1_midi midi;
  1309. struct snd_emu10k1_midi midi2; /* for audigy */
  1310. unsigned int efx_voices_mask[2];
  1311. unsigned int next_free_voice;
  1312. #ifdef CONFIG_PM
  1313. unsigned int *saved_ptr;
  1314. unsigned int *saved_gpr;
  1315. unsigned int *tram_val_saved;
  1316. unsigned int *tram_addr_saved;
  1317. unsigned int *saved_icode;
  1318. unsigned int *p16v_saved;
  1319. unsigned int saved_a_iocfg, saved_hcfg;
  1320. #endif
  1321. };
  1322. int snd_emu10k1_create(struct snd_card *card,
  1323. struct pci_dev *pci,
  1324. unsigned short extin_mask,
  1325. unsigned short extout_mask,
  1326. long max_cache_bytes,
  1327. int enable_ir,
  1328. uint subsystem,
  1329. struct snd_emu10k1 ** remu);
  1330. int snd_emu10k1_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
  1331. int snd_emu10k1_pcm_mic(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
  1332. int snd_emu10k1_pcm_efx(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
  1333. int snd_p16v_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
  1334. int snd_p16v_free(struct snd_emu10k1 * emu);
  1335. int snd_p16v_mixer(struct snd_emu10k1 * emu);
  1336. int snd_emu10k1_pcm_multi(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
  1337. int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 * emu, int device, struct snd_pcm ** rpcm);
  1338. int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
  1339. int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
  1340. int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device, struct snd_hwdep ** rhwdep);
  1341. irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
  1342. void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
  1343. int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
  1344. void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
  1345. int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
  1346. int snd_emu10k1_done(struct snd_emu10k1 * emu);
  1347. /* I/O functions */
  1348. unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
  1349. void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
  1350. unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
  1351. void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
  1352. int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
  1353. int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
  1354. int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, int reg, int value);
  1355. int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, int reg, int *value);
  1356. int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, int dst, int src);
  1357. unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
  1358. void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
  1359. void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
  1360. void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
  1361. void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
  1362. void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
  1363. void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
  1364. void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
  1365. void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
  1366. void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
  1367. void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
  1368. void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
  1369. static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
  1370. unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
  1371. void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
  1372. unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
  1373. #ifdef CONFIG_PM
  1374. void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
  1375. void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
  1376. void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
  1377. int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
  1378. void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
  1379. void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
  1380. void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
  1381. int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
  1382. void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
  1383. void snd_p16v_suspend(struct snd_emu10k1 *emu);
  1384. void snd_p16v_resume(struct snd_emu10k1 *emu);
  1385. #endif
  1386. /* memory allocation */
  1387. struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
  1388. int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
  1389. struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
  1390. int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
  1391. int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
  1392. int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
  1393. int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
  1394. /* voice allocation */
  1395. int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
  1396. int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
  1397. /* MIDI uart */
  1398. int snd_emu10k1_midi(struct snd_emu10k1 * emu);
  1399. int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
  1400. /* proc interface */
  1401. int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
  1402. /* fx8010 irq handler */
  1403. int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
  1404. snd_fx8010_irq_handler_t *handler,
  1405. unsigned char gpr_running,
  1406. void *private_data,
  1407. struct snd_emu10k1_fx8010_irq **r_irq);
  1408. int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
  1409. struct snd_emu10k1_fx8010_irq *irq);
  1410. #endif /* __KERNEL__ */
  1411. /*
  1412. * ---- FX8010 ----
  1413. */
  1414. #define EMU10K1_CARD_CREATIVE 0x00000000
  1415. #define EMU10K1_CARD_EMUAPS 0x00000001
  1416. #define EMU10K1_FX8010_PCM_COUNT 8
  1417. /* instruction set */
  1418. #define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */
  1419. #define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */
  1420. #define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */
  1421. #define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */
  1422. #define iMACINT0 0x04 /* R = A + X * Y ; saturation */
  1423. #define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */
  1424. #define iACC3 0x06 /* R = A + X + Y ; saturation */
  1425. #define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */
  1426. #define iANDXOR 0x08 /* R = (A & X) ^ Y */
  1427. #define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */
  1428. #define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */
  1429. #define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */
  1430. #define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */
  1431. #define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */
  1432. #define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */
  1433. #define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */
  1434. /* GPRs */
  1435. #define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */
  1436. #define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */
  1437. #define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */
  1438. #define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */
  1439. /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */
  1440. #define C_00000000 0x40
  1441. #define C_00000001 0x41
  1442. #define C_00000002 0x42
  1443. #define C_00000003 0x43
  1444. #define C_00000004 0x44
  1445. #define C_00000008 0x45
  1446. #define C_00000010 0x46
  1447. #define C_00000020 0x47
  1448. #define C_00000100 0x48
  1449. #define C_00010000 0x49
  1450. #define C_00080000 0x4a
  1451. #define C_10000000 0x4b
  1452. #define C_20000000 0x4c
  1453. #define C_40000000 0x4d
  1454. #define C_80000000 0x4e
  1455. #define C_7fffffff 0x4f
  1456. #define C_ffffffff 0x50
  1457. #define C_fffffffe 0x51
  1458. #define C_c0000000 0x52
  1459. #define C_4f1bbcdc 0x53
  1460. #define C_5a7ef9db 0x54
  1461. #define C_00100000 0x55 /* ?? */
  1462. #define GPR_ACCU 0x56 /* ACCUM, accumulator */
  1463. #define GPR_COND 0x57 /* CCR, condition register */
  1464. #define GPR_NOISE0 0x58 /* noise source */
  1465. #define GPR_NOISE1 0x59 /* noise source */
  1466. #define GPR_IRQ 0x5a /* IRQ register */
  1467. #define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */
  1468. #define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */
  1469. #define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
  1470. #define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
  1471. #define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */
  1472. #define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */
  1473. #define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
  1474. #define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
  1475. #define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
  1476. #define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
  1477. #define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */
  1478. #define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */
  1479. #define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */
  1480. #define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */
  1481. #define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */
  1482. #define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */
  1483. #define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */
  1484. #define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */
  1485. #define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */
  1486. #define A_GPR(x) (A_FXGPREGBASE + (x))
  1487. /* cc_reg constants */
  1488. #define CC_REG_NORMALIZED C_00000001
  1489. #define CC_REG_BORROW C_00000002
  1490. #define CC_REG_MINUS C_00000004
  1491. #define CC_REG_ZERO C_00000008
  1492. #define CC_REG_SATURATE C_00000010
  1493. #define CC_REG_NONZERO C_00000100
  1494. /* FX buses */
  1495. #define FXBUS_PCM_LEFT 0x00
  1496. #define FXBUS_PCM_RIGHT 0x01
  1497. #define FXBUS_PCM_LEFT_REAR 0x02
  1498. #define FXBUS_PCM_RIGHT_REAR 0x03
  1499. #define FXBUS_MIDI_LEFT 0x04
  1500. #define FXBUS_MIDI_RIGHT 0x05
  1501. #define FXBUS_PCM_CENTER 0x06
  1502. #define FXBUS_PCM_LFE 0x07
  1503. #define FXBUS_PCM_LEFT_FRONT 0x08
  1504. #define FXBUS_PCM_RIGHT_FRONT 0x09
  1505. #define FXBUS_MIDI_REVERB 0x0c
  1506. #define FXBUS_MIDI_CHORUS 0x0d
  1507. #define FXBUS_PCM_LEFT_SIDE 0x0e
  1508. #define FXBUS_PCM_RIGHT_SIDE 0x0f
  1509. #define FXBUS_PT_LEFT 0x14
  1510. #define FXBUS_PT_RIGHT 0x15
  1511. /* Inputs */
  1512. #define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
  1513. #define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
  1514. #define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */
  1515. #define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */
  1516. #define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */
  1517. #define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */
  1518. #define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */
  1519. #define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */
  1520. #define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */
  1521. #define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */
  1522. #define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */
  1523. #define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */
  1524. #define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */
  1525. #define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */
  1526. /* Outputs */
  1527. #define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */
  1528. #define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */
  1529. #define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */
  1530. #define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */
  1531. #define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */
  1532. #define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */
  1533. #define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */
  1534. #define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */
  1535. #define EXTOUT_REAR_L 0x08 /* Rear channel - left */
  1536. #define EXTOUT_REAR_R 0x09 /* Rear channel - right */
  1537. #define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */
  1538. #define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */
  1539. #define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */
  1540. #define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */
  1541. #define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */
  1542. #define EXTOUT_ACENTER 0x11 /* Analog Center */
  1543. #define EXTOUT_ALFE 0x12 /* Analog LFE */
  1544. /* Audigy Inputs */
  1545. #define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */
  1546. #define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */
  1547. #define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */
  1548. #define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */
  1549. #define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */
  1550. #define A_EXTIN_OPT_SPDIF_R 0x05 /* right */
  1551. #define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */
  1552. #define A_EXTIN_LINE2_R 0x09 /* right */
  1553. #define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */
  1554. #define A_EXTIN_ADC_R 0x0b /* right */
  1555. #define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */
  1556. #define A_EXTIN_AUX2_R 0x0d /* - right */
  1557. /* Audigiy Outputs */
  1558. #define A_EXTOUT_FRONT_L 0x00 /* digital front left */
  1559. #define A_EXTOUT_FRONT_R 0x01 /* right */
  1560. #define A_EXTOUT_CENTER 0x02 /* digital front center */
  1561. #define A_EXTOUT_LFE 0x03 /* digital front lfe */
  1562. #define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */
  1563. #define A_EXTOUT_HEADPHONE_R 0x05 /* right */
  1564. #define A_EXTOUT_REAR_L 0x06 /* digital rear left */
  1565. #define A_EXTOUT_REAR_R 0x07 /* right */
  1566. #define A_EXTOUT_AFRONT_L 0x08 /* analog front left */
  1567. #define A_EXTOUT_AFRONT_R 0x09 /* right */
  1568. #define A_EXTOUT_ACENTER 0x0a /* analog center */
  1569. #define A_EXTOUT_ALFE 0x0b /* analog LFE */
  1570. #define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */
  1571. #define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */
  1572. #define A_EXTOUT_AREAR_L 0x0e /* analog rear left */
  1573. #define A_EXTOUT_AREAR_R 0x0f /* right */
  1574. #define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */
  1575. #define A_EXTOUT_AC97_R 0x11 /* right */
  1576. #define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */
  1577. #define A_EXTOUT_ADC_CAP_R 0x17 /* right */
  1578. #define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */
  1579. /* Audigy constants */
  1580. #define A_C_00000000 0xc0
  1581. #define A_C_00000001 0xc1
  1582. #define A_C_00000002 0xc2
  1583. #define A_C_00000003 0xc3
  1584. #define A_C_00000004 0xc4
  1585. #define A_C_00000008 0xc5
  1586. #define A_C_00000010 0xc6
  1587. #define A_C_00000020 0xc7
  1588. #define A_C_00000100 0xc8
  1589. #define A_C_00010000 0xc9
  1590. #define A_C_00000800 0xca
  1591. #define A_C_10000000 0xcb
  1592. #define A_C_20000000 0xcc
  1593. #define A_C_40000000 0xcd
  1594. #define A_C_80000000 0xce
  1595. #define A_C_7fffffff 0xcf
  1596. #define A_C_ffffffff 0xd0
  1597. #define A_C_fffffffe 0xd1
  1598. #define A_C_c0000000 0xd2
  1599. #define A_C_4f1bbcdc 0xd3
  1600. #define A_C_5a7ef9db 0xd4
  1601. #define A_C_00100000 0xd5
  1602. #define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */
  1603. #define A_GPR_COND 0xd7 /* CCR, condition register */
  1604. #define A_GPR_NOISE0 0xd8 /* noise source */
  1605. #define A_GPR_NOISE1 0xd9 /* noise source */
  1606. #define A_GPR_IRQ 0xda /* IRQ register */
  1607. #define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */
  1608. #define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */
  1609. /* definitions for debug register */
  1610. #define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */
  1611. #define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */
  1612. #define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */
  1613. #define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */
  1614. #define EMU10K1_DBG_STEP 0x00004000 /* start single step */
  1615. #define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */
  1616. #define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */
  1617. /* tank memory address line */
  1618. #ifndef __KERNEL__
  1619. #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
  1620. #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
  1621. #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
  1622. #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
  1623. #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
  1624. #endif
  1625. struct snd_emu10k1_fx8010_info {
  1626. unsigned int internal_tram_size; /* in samples */
  1627. unsigned int external_tram_size; /* in samples */
  1628. char fxbus_names[16][32]; /* names of FXBUSes */
  1629. char extin_names[16][32]; /* names of external inputs */
  1630. char extout_names[32][32]; /* names of external outputs */
  1631. unsigned int gpr_controls; /* count of GPR controls */
  1632. };
  1633. #define EMU10K1_GPR_TRANSLATION_NONE 0
  1634. #define EMU10K1_GPR_TRANSLATION_TABLE100 1
  1635. #define EMU10K1_GPR_TRANSLATION_BASS 2
  1636. #define EMU10K1_GPR_TRANSLATION_TREBLE 3
  1637. #define EMU10K1_GPR_TRANSLATION_ONOFF 4
  1638. struct snd_emu10k1_fx8010_control_gpr {
  1639. struct snd_ctl_elem_id id; /* full control ID definition */
  1640. unsigned int vcount; /* visible count */
  1641. unsigned int count; /* count of GPR (1..16) */
  1642. unsigned short gpr[32]; /* GPR number(s) */
  1643. unsigned int value[32]; /* initial values */
  1644. unsigned int min; /* minimum range */
  1645. unsigned int max; /* maximum range */
  1646. unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
  1647. const unsigned int *tlv;
  1648. };
  1649. /* old ABI without TLV support */
  1650. struct snd_emu10k1_fx8010_control_old_gpr {
  1651. struct snd_ctl_elem_id id;
  1652. unsigned int vcount;
  1653. unsigned int count;
  1654. unsigned short gpr[32];
  1655. unsigned int value[32];
  1656. unsigned int min;
  1657. unsigned int max;
  1658. unsigned int translation;
  1659. };
  1660. struct snd_emu10k1_fx8010_code {
  1661. char name[128];
  1662. DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */
  1663. u_int32_t __user *gpr_map; /* initializers */
  1664. unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */
  1665. struct snd_emu10k1_fx8010_control_gpr __user *gpr_add_controls; /* GPR controls to add/replace */
  1666. unsigned int gpr_del_control_count; /* count of GPR controls to remove */
  1667. struct snd_ctl_elem_id __user *gpr_del_controls; /* IDs of GPR controls to remove */
  1668. unsigned int gpr_list_control_count; /* count of GPR controls to list */
  1669. unsigned int gpr_list_control_total; /* total count of GPR controls */
  1670. struct snd_emu10k1_fx8010_control_gpr __user *gpr_list_controls; /* listed GPR controls */
  1671. DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */
  1672. u_int32_t __user *tram_data_map; /* data initializers */
  1673. u_int32_t __user *tram_addr_map; /* map initializers */
  1674. DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */
  1675. u_int32_t __user *code; /* one instruction - 64 bits */
  1676. };
  1677. struct snd_emu10k1_fx8010_tram {
  1678. unsigned int address; /* 31.bit == 1 -> external TRAM */
  1679. unsigned int size; /* size in samples (4 bytes) */
  1680. unsigned int *samples; /* pointer to samples (20-bit) */
  1681. /* NULL->clear memory */
  1682. };
  1683. struct snd_emu10k1_fx8010_pcm_rec {
  1684. unsigned int substream; /* substream number */
  1685. unsigned int res1; /* reserved */
  1686. unsigned int channels; /* 16-bit channels count, zero = remove this substream */
  1687. unsigned int tram_start; /* ring buffer position in TRAM (in samples) */
  1688. unsigned int buffer_size; /* count of buffered samples */
  1689. unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */
  1690. unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
  1691. unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
  1692. unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
  1693. unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
  1694. unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
  1695. unsigned char pad; /* reserved */
  1696. unsigned char etram[32]; /* external TRAM address & data (one per channel) */
  1697. unsigned int res2; /* reserved */
  1698. };
  1699. #define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1)
  1700. #define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info)
  1701. #define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code)
  1702. #define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code)
  1703. #define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int)
  1704. #define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram)
  1705. #define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram)
  1706. #define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec)
  1707. #define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec)
  1708. #define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int)
  1709. #define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80)
  1710. #define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81)
  1711. #define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82)
  1712. #define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int)
  1713. #define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int)
  1714. /* typedefs for compatibility to user-space */
  1715. typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t;
  1716. typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t;
  1717. typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t;
  1718. typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t;
  1719. typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t;
  1720. #endif /* __SOUND_EMU10K1_H */