cs46xx.h 72 KB

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  1. #ifndef __SOUND_CS46XX_H
  2. #define __SOUND_CS46XX_H
  3. /*
  4. * Copyright (c) by Jaroslav Kysela <perex@suse.cz>,
  5. * Cirrus Logic, Inc.
  6. * Definitions for Cirrus Logic CS46xx chips
  7. *
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. */
  24. #include "pcm.h"
  25. #include "pcm-indirect.h"
  26. #include "rawmidi.h"
  27. #include "ac97_codec.h"
  28. #include "cs46xx_dsp_spos.h"
  29. /*
  30. * Direct registers
  31. */
  32. /*
  33. * The following define the offsets of the registers accessed via base address
  34. * register zero on the CS46xx part.
  35. */
  36. #define BA0_HISR 0x00000000
  37. #define BA0_HSR0 0x00000004
  38. #define BA0_HICR 0x00000008
  39. #define BA0_DMSR 0x00000100
  40. #define BA0_HSAR 0x00000110
  41. #define BA0_HDAR 0x00000114
  42. #define BA0_HDMR 0x00000118
  43. #define BA0_HDCR 0x0000011C
  44. #define BA0_PFMC 0x00000200
  45. #define BA0_PFCV1 0x00000204
  46. #define BA0_PFCV2 0x00000208
  47. #define BA0_PCICFG00 0x00000300
  48. #define BA0_PCICFG04 0x00000304
  49. #define BA0_PCICFG08 0x00000308
  50. #define BA0_PCICFG0C 0x0000030C
  51. #define BA0_PCICFG10 0x00000310
  52. #define BA0_PCICFG14 0x00000314
  53. #define BA0_PCICFG18 0x00000318
  54. #define BA0_PCICFG1C 0x0000031C
  55. #define BA0_PCICFG20 0x00000320
  56. #define BA0_PCICFG24 0x00000324
  57. #define BA0_PCICFG28 0x00000328
  58. #define BA0_PCICFG2C 0x0000032C
  59. #define BA0_PCICFG30 0x00000330
  60. #define BA0_PCICFG34 0x00000334
  61. #define BA0_PCICFG38 0x00000338
  62. #define BA0_PCICFG3C 0x0000033C
  63. #define BA0_CLKCR1 0x00000400
  64. #define BA0_CLKCR2 0x00000404
  65. #define BA0_PLLM 0x00000408
  66. #define BA0_PLLCC 0x0000040C
  67. #define BA0_FRR 0x00000410
  68. #define BA0_CFL1 0x00000414
  69. #define BA0_CFL2 0x00000418
  70. #define BA0_SERMC1 0x00000420
  71. #define BA0_SERMC2 0x00000424
  72. #define BA0_SERC1 0x00000428
  73. #define BA0_SERC2 0x0000042C
  74. #define BA0_SERC3 0x00000430
  75. #define BA0_SERC4 0x00000434
  76. #define BA0_SERC5 0x00000438
  77. #define BA0_SERBSP 0x0000043C
  78. #define BA0_SERBST 0x00000440
  79. #define BA0_SERBCM 0x00000444
  80. #define BA0_SERBAD 0x00000448
  81. #define BA0_SERBCF 0x0000044C
  82. #define BA0_SERBWP 0x00000450
  83. #define BA0_SERBRP 0x00000454
  84. #ifndef NO_CS4612
  85. #define BA0_ASER_FADDR 0x00000458
  86. #endif
  87. #define BA0_ACCTL 0x00000460
  88. #define BA0_ACSTS 0x00000464
  89. #define BA0_ACOSV 0x00000468
  90. #define BA0_ACCAD 0x0000046C
  91. #define BA0_ACCDA 0x00000470
  92. #define BA0_ACISV 0x00000474
  93. #define BA0_ACSAD 0x00000478
  94. #define BA0_ACSDA 0x0000047C
  95. #define BA0_JSPT 0x00000480
  96. #define BA0_JSCTL 0x00000484
  97. #define BA0_JSC1 0x00000488
  98. #define BA0_JSC2 0x0000048C
  99. #define BA0_MIDCR 0x00000490
  100. #define BA0_MIDSR 0x00000494
  101. #define BA0_MIDWP 0x00000498
  102. #define BA0_MIDRP 0x0000049C
  103. #define BA0_JSIO 0x000004A0
  104. #ifndef NO_CS4612
  105. #define BA0_ASER_MASTER 0x000004A4
  106. #endif
  107. #define BA0_CFGI 0x000004B0
  108. #define BA0_SSVID 0x000004B4
  109. #define BA0_GPIOR 0x000004B8
  110. #ifndef NO_CS4612
  111. #define BA0_EGPIODR 0x000004BC
  112. #define BA0_EGPIOPTR 0x000004C0
  113. #define BA0_EGPIOTR 0x000004C4
  114. #define BA0_EGPIOWR 0x000004C8
  115. #define BA0_EGPIOSR 0x000004CC
  116. #define BA0_SERC6 0x000004D0
  117. #define BA0_SERC7 0x000004D4
  118. #define BA0_SERACC 0x000004D8
  119. #define BA0_ACCTL2 0x000004E0
  120. #define BA0_ACSTS2 0x000004E4
  121. #define BA0_ACOSV2 0x000004E8
  122. #define BA0_ACCAD2 0x000004EC
  123. #define BA0_ACCDA2 0x000004F0
  124. #define BA0_ACISV2 0x000004F4
  125. #define BA0_ACSAD2 0x000004F8
  126. #define BA0_ACSDA2 0x000004FC
  127. #define BA0_IOTAC0 0x00000500
  128. #define BA0_IOTAC1 0x00000504
  129. #define BA0_IOTAC2 0x00000508
  130. #define BA0_IOTAC3 0x0000050C
  131. #define BA0_IOTAC4 0x00000510
  132. #define BA0_IOTAC5 0x00000514
  133. #define BA0_IOTAC6 0x00000518
  134. #define BA0_IOTAC7 0x0000051C
  135. #define BA0_IOTAC8 0x00000520
  136. #define BA0_IOTAC9 0x00000524
  137. #define BA0_IOTAC10 0x00000528
  138. #define BA0_IOTAC11 0x0000052C
  139. #define BA0_IOTFR0 0x00000540
  140. #define BA0_IOTFR1 0x00000544
  141. #define BA0_IOTFR2 0x00000548
  142. #define BA0_IOTFR3 0x0000054C
  143. #define BA0_IOTFR4 0x00000550
  144. #define BA0_IOTFR5 0x00000554
  145. #define BA0_IOTFR6 0x00000558
  146. #define BA0_IOTFR7 0x0000055C
  147. #define BA0_IOTFIFO 0x00000580
  148. #define BA0_IOTRRD 0x00000584
  149. #define BA0_IOTFP 0x00000588
  150. #define BA0_IOTCR 0x0000058C
  151. #define BA0_DPCID 0x00000590
  152. #define BA0_DPCIA 0x00000594
  153. #define BA0_DPCIC 0x00000598
  154. #define BA0_PCPCIR 0x00000600
  155. #define BA0_PCPCIG 0x00000604
  156. #define BA0_PCPCIEN 0x00000608
  157. #define BA0_EPCIPMC 0x00000610
  158. #endif
  159. /*
  160. * The following define the offsets of the registers and memories accessed via
  161. * base address register one on the CS46xx part.
  162. */
  163. #define BA1_SP_DMEM0 0x00000000
  164. #define BA1_SP_DMEM1 0x00010000
  165. #define BA1_SP_PMEM 0x00020000
  166. #define BA1_SP_REG 0x00030000
  167. #define BA1_SPCR 0x00030000
  168. #define BA1_DREG 0x00030004
  169. #define BA1_DSRWP 0x00030008
  170. #define BA1_TWPR 0x0003000C
  171. #define BA1_SPWR 0x00030010
  172. #define BA1_SPIR 0x00030014
  173. #define BA1_FGR1 0x00030020
  174. #define BA1_SPCS 0x00030028
  175. #define BA1_SDSR 0x0003002C
  176. #define BA1_FRMT 0x00030030
  177. #define BA1_FRCC 0x00030034
  178. #define BA1_FRSC 0x00030038
  179. #define BA1_OMNI_MEM 0x000E0000
  180. /*
  181. * The following defines are for the flags in the host interrupt status
  182. * register.
  183. */
  184. #define HISR_VC_MASK 0x0000FFFF
  185. #define HISR_VC0 0x00000001
  186. #define HISR_VC1 0x00000002
  187. #define HISR_VC2 0x00000004
  188. #define HISR_VC3 0x00000008
  189. #define HISR_VC4 0x00000010
  190. #define HISR_VC5 0x00000020
  191. #define HISR_VC6 0x00000040
  192. #define HISR_VC7 0x00000080
  193. #define HISR_VC8 0x00000100
  194. #define HISR_VC9 0x00000200
  195. #define HISR_VC10 0x00000400
  196. #define HISR_VC11 0x00000800
  197. #define HISR_VC12 0x00001000
  198. #define HISR_VC13 0x00002000
  199. #define HISR_VC14 0x00004000
  200. #define HISR_VC15 0x00008000
  201. #define HISR_INT0 0x00010000
  202. #define HISR_INT1 0x00020000
  203. #define HISR_DMAI 0x00040000
  204. #define HISR_FROVR 0x00080000
  205. #define HISR_MIDI 0x00100000
  206. #ifdef NO_CS4612
  207. #define HISR_RESERVED 0x0FE00000
  208. #else
  209. #define HISR_SBINT 0x00200000
  210. #define HISR_RESERVED 0x0FC00000
  211. #endif
  212. #define HISR_H0P 0x40000000
  213. #define HISR_INTENA 0x80000000
  214. /*
  215. * The following defines are for the flags in the host signal register 0.
  216. */
  217. #define HSR0_VC_MASK 0xFFFFFFFF
  218. #define HSR0_VC16 0x00000001
  219. #define HSR0_VC17 0x00000002
  220. #define HSR0_VC18 0x00000004
  221. #define HSR0_VC19 0x00000008
  222. #define HSR0_VC20 0x00000010
  223. #define HSR0_VC21 0x00000020
  224. #define HSR0_VC22 0x00000040
  225. #define HSR0_VC23 0x00000080
  226. #define HSR0_VC24 0x00000100
  227. #define HSR0_VC25 0x00000200
  228. #define HSR0_VC26 0x00000400
  229. #define HSR0_VC27 0x00000800
  230. #define HSR0_VC28 0x00001000
  231. #define HSR0_VC29 0x00002000
  232. #define HSR0_VC30 0x00004000
  233. #define HSR0_VC31 0x00008000
  234. #define HSR0_VC32 0x00010000
  235. #define HSR0_VC33 0x00020000
  236. #define HSR0_VC34 0x00040000
  237. #define HSR0_VC35 0x00080000
  238. #define HSR0_VC36 0x00100000
  239. #define HSR0_VC37 0x00200000
  240. #define HSR0_VC38 0x00400000
  241. #define HSR0_VC39 0x00800000
  242. #define HSR0_VC40 0x01000000
  243. #define HSR0_VC41 0x02000000
  244. #define HSR0_VC42 0x04000000
  245. #define HSR0_VC43 0x08000000
  246. #define HSR0_VC44 0x10000000
  247. #define HSR0_VC45 0x20000000
  248. #define HSR0_VC46 0x40000000
  249. #define HSR0_VC47 0x80000000
  250. /*
  251. * The following defines are for the flags in the host interrupt control
  252. * register.
  253. */
  254. #define HICR_IEV 0x00000001
  255. #define HICR_CHGM 0x00000002
  256. /*
  257. * The following defines are for the flags in the DMA status register.
  258. */
  259. #define DMSR_HP 0x00000001
  260. #define DMSR_HR 0x00000002
  261. #define DMSR_SP 0x00000004
  262. #define DMSR_SR 0x00000008
  263. /*
  264. * The following defines are for the flags in the host DMA source address
  265. * register.
  266. */
  267. #define HSAR_HOST_ADDR_MASK 0xFFFFFFFF
  268. #define HSAR_DSP_ADDR_MASK 0x0000FFFF
  269. #define HSAR_MEMID_MASK 0x000F0000
  270. #define HSAR_MEMID_SP_DMEM0 0x00000000
  271. #define HSAR_MEMID_SP_DMEM1 0x00010000
  272. #define HSAR_MEMID_SP_PMEM 0x00020000
  273. #define HSAR_MEMID_SP_DEBUG 0x00030000
  274. #define HSAR_MEMID_OMNI_MEM 0x000E0000
  275. #define HSAR_END 0x40000000
  276. #define HSAR_ERR 0x80000000
  277. /*
  278. * The following defines are for the flags in the host DMA destination address
  279. * register.
  280. */
  281. #define HDAR_HOST_ADDR_MASK 0xFFFFFFFF
  282. #define HDAR_DSP_ADDR_MASK 0x0000FFFF
  283. #define HDAR_MEMID_MASK 0x000F0000
  284. #define HDAR_MEMID_SP_DMEM0 0x00000000
  285. #define HDAR_MEMID_SP_DMEM1 0x00010000
  286. #define HDAR_MEMID_SP_PMEM 0x00020000
  287. #define HDAR_MEMID_SP_DEBUG 0x00030000
  288. #define HDAR_MEMID_OMNI_MEM 0x000E0000
  289. #define HDAR_END 0x40000000
  290. #define HDAR_ERR 0x80000000
  291. /*
  292. * The following defines are for the flags in the host DMA control register.
  293. */
  294. #define HDMR_AC_MASK 0x0000F000
  295. #define HDMR_AC_8_16 0x00001000
  296. #define HDMR_AC_M_S 0x00002000
  297. #define HDMR_AC_B_L 0x00004000
  298. #define HDMR_AC_S_U 0x00008000
  299. /*
  300. * The following defines are for the flags in the host DMA control register.
  301. */
  302. #define HDCR_COUNT_MASK 0x000003FF
  303. #define HDCR_DONE 0x00004000
  304. #define HDCR_OPT 0x00008000
  305. #define HDCR_WBD 0x00400000
  306. #define HDCR_WBS 0x00800000
  307. #define HDCR_DMS_MASK 0x07000000
  308. #define HDCR_DMS_LINEAR 0x00000000
  309. #define HDCR_DMS_16_DWORDS 0x01000000
  310. #define HDCR_DMS_32_DWORDS 0x02000000
  311. #define HDCR_DMS_64_DWORDS 0x03000000
  312. #define HDCR_DMS_128_DWORDS 0x04000000
  313. #define HDCR_DMS_256_DWORDS 0x05000000
  314. #define HDCR_DMS_512_DWORDS 0x06000000
  315. #define HDCR_DMS_1024_DWORDS 0x07000000
  316. #define HDCR_DH 0x08000000
  317. #define HDCR_SMS_MASK 0x70000000
  318. #define HDCR_SMS_LINEAR 0x00000000
  319. #define HDCR_SMS_16_DWORDS 0x10000000
  320. #define HDCR_SMS_32_DWORDS 0x20000000
  321. #define HDCR_SMS_64_DWORDS 0x30000000
  322. #define HDCR_SMS_128_DWORDS 0x40000000
  323. #define HDCR_SMS_256_DWORDS 0x50000000
  324. #define HDCR_SMS_512_DWORDS 0x60000000
  325. #define HDCR_SMS_1024_DWORDS 0x70000000
  326. #define HDCR_SH 0x80000000
  327. #define HDCR_COUNT_SHIFT 0
  328. /*
  329. * The following defines are for the flags in the performance monitor control
  330. * register.
  331. */
  332. #define PFMC_C1SS_MASK 0x0000001F
  333. #define PFMC_C1EV 0x00000020
  334. #define PFMC_C1RS 0x00008000
  335. #define PFMC_C2SS_MASK 0x001F0000
  336. #define PFMC_C2EV 0x00200000
  337. #define PFMC_C2RS 0x80000000
  338. #define PFMC_C1SS_SHIFT 0
  339. #define PFMC_C2SS_SHIFT 16
  340. #define PFMC_BUS_GRANT 0
  341. #define PFMC_GRANT_AFTER_REQ 1
  342. #define PFMC_TRANSACTION 2
  343. #define PFMC_DWORD_TRANSFER 3
  344. #define PFMC_SLAVE_READ 4
  345. #define PFMC_SLAVE_WRITE 5
  346. #define PFMC_PREEMPTION 6
  347. #define PFMC_DISCONNECT_RETRY 7
  348. #define PFMC_INTERRUPT 8
  349. #define PFMC_BUS_OWNERSHIP 9
  350. #define PFMC_TRANSACTION_LAG 10
  351. #define PFMC_PCI_CLOCK 11
  352. #define PFMC_SERIAL_CLOCK 12
  353. #define PFMC_SP_CLOCK 13
  354. /*
  355. * The following defines are for the flags in the performance counter value 1
  356. * register.
  357. */
  358. #define PFCV1_PC1V_MASK 0xFFFFFFFF
  359. #define PFCV1_PC1V_SHIFT 0
  360. /*
  361. * The following defines are for the flags in the performance counter value 2
  362. * register.
  363. */
  364. #define PFCV2_PC2V_MASK 0xFFFFFFFF
  365. #define PFCV2_PC2V_SHIFT 0
  366. /*
  367. * The following defines are for the flags in the clock control register 1.
  368. */
  369. #define CLKCR1_OSCS 0x00000001
  370. #define CLKCR1_OSCP 0x00000002
  371. #define CLKCR1_PLLSS_MASK 0x0000000C
  372. #define CLKCR1_PLLSS_SERIAL 0x00000000
  373. #define CLKCR1_PLLSS_CRYSTAL 0x00000004
  374. #define CLKCR1_PLLSS_PCI 0x00000008
  375. #define CLKCR1_PLLSS_RESERVED 0x0000000C
  376. #define CLKCR1_PLLP 0x00000010
  377. #define CLKCR1_SWCE 0x00000020
  378. #define CLKCR1_PLLOS 0x00000040
  379. /*
  380. * The following defines are for the flags in the clock control register 2.
  381. */
  382. #define CLKCR2_PDIVS_MASK 0x0000000F
  383. #define CLKCR2_PDIVS_1 0x00000001
  384. #define CLKCR2_PDIVS_2 0x00000002
  385. #define CLKCR2_PDIVS_4 0x00000004
  386. #define CLKCR2_PDIVS_7 0x00000007
  387. #define CLKCR2_PDIVS_8 0x00000008
  388. #define CLKCR2_PDIVS_16 0x00000000
  389. /*
  390. * The following defines are for the flags in the PLL multiplier register.
  391. */
  392. #define PLLM_MASK 0x000000FF
  393. #define PLLM_SHIFT 0
  394. /*
  395. * The following defines are for the flags in the PLL capacitor coefficient
  396. * register.
  397. */
  398. #define PLLCC_CDR_MASK 0x00000007
  399. #ifndef NO_CS4610
  400. #define PLLCC_CDR_240_350_MHZ 0x00000000
  401. #define PLLCC_CDR_184_265_MHZ 0x00000001
  402. #define PLLCC_CDR_144_205_MHZ 0x00000002
  403. #define PLLCC_CDR_111_160_MHZ 0x00000003
  404. #define PLLCC_CDR_87_123_MHZ 0x00000004
  405. #define PLLCC_CDR_67_96_MHZ 0x00000005
  406. #define PLLCC_CDR_52_74_MHZ 0x00000006
  407. #define PLLCC_CDR_45_58_MHZ 0x00000007
  408. #endif
  409. #ifndef NO_CS4612
  410. #define PLLCC_CDR_271_398_MHZ 0x00000000
  411. #define PLLCC_CDR_227_330_MHZ 0x00000001
  412. #define PLLCC_CDR_167_239_MHZ 0x00000002
  413. #define PLLCC_CDR_150_215_MHZ 0x00000003
  414. #define PLLCC_CDR_107_154_MHZ 0x00000004
  415. #define PLLCC_CDR_98_140_MHZ 0x00000005
  416. #define PLLCC_CDR_73_104_MHZ 0x00000006
  417. #define PLLCC_CDR_63_90_MHZ 0x00000007
  418. #endif
  419. #define PLLCC_LPF_MASK 0x000000F8
  420. #ifndef NO_CS4610
  421. #define PLLCC_LPF_23850_60000_KHZ 0x00000000
  422. #define PLLCC_LPF_7960_26290_KHZ 0x00000008
  423. #define PLLCC_LPF_4160_10980_KHZ 0x00000018
  424. #define PLLCC_LPF_1740_4580_KHZ 0x00000038
  425. #define PLLCC_LPF_724_1910_KHZ 0x00000078
  426. #define PLLCC_LPF_317_798_KHZ 0x000000F8
  427. #endif
  428. #ifndef NO_CS4612
  429. #define PLLCC_LPF_25580_64530_KHZ 0x00000000
  430. #define PLLCC_LPF_14360_37270_KHZ 0x00000008
  431. #define PLLCC_LPF_6100_16020_KHZ 0x00000018
  432. #define PLLCC_LPF_2540_6690_KHZ 0x00000038
  433. #define PLLCC_LPF_1050_2780_KHZ 0x00000078
  434. #define PLLCC_LPF_450_1160_KHZ 0x000000F8
  435. #endif
  436. /*
  437. * The following defines are for the flags in the feature reporting register.
  438. */
  439. #define FRR_FAB_MASK 0x00000003
  440. #define FRR_MASK_MASK 0x0000001C
  441. #ifdef NO_CS4612
  442. #define FRR_CFOP_MASK 0x000000E0
  443. #else
  444. #define FRR_CFOP_MASK 0x00000FE0
  445. #endif
  446. #define FRR_CFOP_NOT_DVD 0x00000020
  447. #define FRR_CFOP_A3D 0x00000040
  448. #define FRR_CFOP_128_PIN 0x00000080
  449. #ifndef NO_CS4612
  450. #define FRR_CFOP_CS4280 0x00000800
  451. #endif
  452. #define FRR_FAB_SHIFT 0
  453. #define FRR_MASK_SHIFT 2
  454. #define FRR_CFOP_SHIFT 5
  455. /*
  456. * The following defines are for the flags in the configuration load 1
  457. * register.
  458. */
  459. #define CFL1_CLOCK_SOURCE_MASK 0x00000003
  460. #define CFL1_CLOCK_SOURCE_CS423X 0x00000000
  461. #define CFL1_CLOCK_SOURCE_AC97 0x00000001
  462. #define CFL1_CLOCK_SOURCE_CRYSTAL 0x00000002
  463. #define CFL1_CLOCK_SOURCE_DUAL_AC97 0x00000003
  464. #define CFL1_VALID_DATA_MASK 0x000000FF
  465. /*
  466. * The following defines are for the flags in the configuration load 2
  467. * register.
  468. */
  469. #define CFL2_VALID_DATA_MASK 0x000000FF
  470. /*
  471. * The following defines are for the flags in the serial port master control
  472. * register 1.
  473. */
  474. #define SERMC1_MSPE 0x00000001
  475. #define SERMC1_PTC_MASK 0x0000000E
  476. #define SERMC1_PTC_CS423X 0x00000000
  477. #define SERMC1_PTC_AC97 0x00000002
  478. #define SERMC1_PTC_DAC 0x00000004
  479. #define SERMC1_PLB 0x00000010
  480. #define SERMC1_XLB 0x00000020
  481. /*
  482. * The following defines are for the flags in the serial port master control
  483. * register 2.
  484. */
  485. #define SERMC2_LROE 0x00000001
  486. #define SERMC2_MCOE 0x00000002
  487. #define SERMC2_MCDIV 0x00000004
  488. /*
  489. * The following defines are for the flags in the serial port 1 configuration
  490. * register.
  491. */
  492. #define SERC1_SO1EN 0x00000001
  493. #define SERC1_SO1F_MASK 0x0000000E
  494. #define SERC1_SO1F_CS423X 0x00000000
  495. #define SERC1_SO1F_AC97 0x00000002
  496. #define SERC1_SO1F_DAC 0x00000004
  497. #define SERC1_SO1F_SPDIF 0x00000006
  498. /*
  499. * The following defines are for the flags in the serial port 2 configuration
  500. * register.
  501. */
  502. #define SERC2_SI1EN 0x00000001
  503. #define SERC2_SI1F_MASK 0x0000000E
  504. #define SERC2_SI1F_CS423X 0x00000000
  505. #define SERC2_SI1F_AC97 0x00000002
  506. #define SERC2_SI1F_ADC 0x00000004
  507. #define SERC2_SI1F_SPDIF 0x00000006
  508. /*
  509. * The following defines are for the flags in the serial port 3 configuration
  510. * register.
  511. */
  512. #define SERC3_SO2EN 0x00000001
  513. #define SERC3_SO2F_MASK 0x00000006
  514. #define SERC3_SO2F_DAC 0x00000000
  515. #define SERC3_SO2F_SPDIF 0x00000002
  516. /*
  517. * The following defines are for the flags in the serial port 4 configuration
  518. * register.
  519. */
  520. #define SERC4_SO3EN 0x00000001
  521. #define SERC4_SO3F_MASK 0x00000006
  522. #define SERC4_SO3F_DAC 0x00000000
  523. #define SERC4_SO3F_SPDIF 0x00000002
  524. /*
  525. * The following defines are for the flags in the serial port 5 configuration
  526. * register.
  527. */
  528. #define SERC5_SI2EN 0x00000001
  529. #define SERC5_SI2F_MASK 0x00000006
  530. #define SERC5_SI2F_ADC 0x00000000
  531. #define SERC5_SI2F_SPDIF 0x00000002
  532. /*
  533. * The following defines are for the flags in the serial port backdoor sample
  534. * pointer register.
  535. */
  536. #define SERBSP_FSP_MASK 0x0000000F
  537. #define SERBSP_FSP_SHIFT 0
  538. /*
  539. * The following defines are for the flags in the serial port backdoor status
  540. * register.
  541. */
  542. #define SERBST_RRDY 0x00000001
  543. #define SERBST_WBSY 0x00000002
  544. /*
  545. * The following defines are for the flags in the serial port backdoor command
  546. * register.
  547. */
  548. #define SERBCM_RDC 0x00000001
  549. #define SERBCM_WRC 0x00000002
  550. /*
  551. * The following defines are for the flags in the serial port backdoor address
  552. * register.
  553. */
  554. #ifdef NO_CS4612
  555. #define SERBAD_FAD_MASK 0x000000FF
  556. #else
  557. #define SERBAD_FAD_MASK 0x000001FF
  558. #endif
  559. #define SERBAD_FAD_SHIFT 0
  560. /*
  561. * The following defines are for the flags in the serial port backdoor
  562. * configuration register.
  563. */
  564. #define SERBCF_HBP 0x00000001
  565. /*
  566. * The following defines are for the flags in the serial port backdoor write
  567. * port register.
  568. */
  569. #define SERBWP_FWD_MASK 0x000FFFFF
  570. #define SERBWP_FWD_SHIFT 0
  571. /*
  572. * The following defines are for the flags in the serial port backdoor read
  573. * port register.
  574. */
  575. #define SERBRP_FRD_MASK 0x000FFFFF
  576. #define SERBRP_FRD_SHIFT 0
  577. /*
  578. * The following defines are for the flags in the async FIFO address register.
  579. */
  580. #ifndef NO_CS4612
  581. #define ASER_FADDR_A1_MASK 0x000001FF
  582. #define ASER_FADDR_EN1 0x00008000
  583. #define ASER_FADDR_A2_MASK 0x01FF0000
  584. #define ASER_FADDR_EN2 0x80000000
  585. #define ASER_FADDR_A1_SHIFT 0
  586. #define ASER_FADDR_A2_SHIFT 16
  587. #endif
  588. /*
  589. * The following defines are for the flags in the AC97 control register.
  590. */
  591. #define ACCTL_RSTN 0x00000001
  592. #define ACCTL_ESYN 0x00000002
  593. #define ACCTL_VFRM 0x00000004
  594. #define ACCTL_DCV 0x00000008
  595. #define ACCTL_CRW 0x00000010
  596. #define ACCTL_ASYN 0x00000020
  597. #ifndef NO_CS4612
  598. #define ACCTL_TC 0x00000040
  599. #endif
  600. /*
  601. * The following defines are for the flags in the AC97 status register.
  602. */
  603. #define ACSTS_CRDY 0x00000001
  604. #define ACSTS_VSTS 0x00000002
  605. #ifndef NO_CS4612
  606. #define ACSTS_WKUP 0x00000004
  607. #endif
  608. /*
  609. * The following defines are for the flags in the AC97 output slot valid
  610. * register.
  611. */
  612. #define ACOSV_SLV3 0x00000001
  613. #define ACOSV_SLV4 0x00000002
  614. #define ACOSV_SLV5 0x00000004
  615. #define ACOSV_SLV6 0x00000008
  616. #define ACOSV_SLV7 0x00000010
  617. #define ACOSV_SLV8 0x00000020
  618. #define ACOSV_SLV9 0x00000040
  619. #define ACOSV_SLV10 0x00000080
  620. #define ACOSV_SLV11 0x00000100
  621. #define ACOSV_SLV12 0x00000200
  622. /*
  623. * The following defines are for the flags in the AC97 command address
  624. * register.
  625. */
  626. #define ACCAD_CI_MASK 0x0000007F
  627. #define ACCAD_CI_SHIFT 0
  628. /*
  629. * The following defines are for the flags in the AC97 command data register.
  630. */
  631. #define ACCDA_CD_MASK 0x0000FFFF
  632. #define ACCDA_CD_SHIFT 0
  633. /*
  634. * The following defines are for the flags in the AC97 input slot valid
  635. * register.
  636. */
  637. #define ACISV_ISV3 0x00000001
  638. #define ACISV_ISV4 0x00000002
  639. #define ACISV_ISV5 0x00000004
  640. #define ACISV_ISV6 0x00000008
  641. #define ACISV_ISV7 0x00000010
  642. #define ACISV_ISV8 0x00000020
  643. #define ACISV_ISV9 0x00000040
  644. #define ACISV_ISV10 0x00000080
  645. #define ACISV_ISV11 0x00000100
  646. #define ACISV_ISV12 0x00000200
  647. /*
  648. * The following defines are for the flags in the AC97 status address
  649. * register.
  650. */
  651. #define ACSAD_SI_MASK 0x0000007F
  652. #define ACSAD_SI_SHIFT 0
  653. /*
  654. * The following defines are for the flags in the AC97 status data register.
  655. */
  656. #define ACSDA_SD_MASK 0x0000FFFF
  657. #define ACSDA_SD_SHIFT 0
  658. /*
  659. * The following defines are for the flags in the joystick poll/trigger
  660. * register.
  661. */
  662. #define JSPT_CAX 0x00000001
  663. #define JSPT_CAY 0x00000002
  664. #define JSPT_CBX 0x00000004
  665. #define JSPT_CBY 0x00000008
  666. #define JSPT_BA1 0x00000010
  667. #define JSPT_BA2 0x00000020
  668. #define JSPT_BB1 0x00000040
  669. #define JSPT_BB2 0x00000080
  670. /*
  671. * The following defines are for the flags in the joystick control register.
  672. */
  673. #define JSCTL_SP_MASK 0x00000003
  674. #define JSCTL_SP_SLOW 0x00000000
  675. #define JSCTL_SP_MEDIUM_SLOW 0x00000001
  676. #define JSCTL_SP_MEDIUM_FAST 0x00000002
  677. #define JSCTL_SP_FAST 0x00000003
  678. #define JSCTL_ARE 0x00000004
  679. /*
  680. * The following defines are for the flags in the joystick coordinate pair 1
  681. * readback register.
  682. */
  683. #define JSC1_Y1V_MASK 0x0000FFFF
  684. #define JSC1_X1V_MASK 0xFFFF0000
  685. #define JSC1_Y1V_SHIFT 0
  686. #define JSC1_X1V_SHIFT 16
  687. /*
  688. * The following defines are for the flags in the joystick coordinate pair 2
  689. * readback register.
  690. */
  691. #define JSC2_Y2V_MASK 0x0000FFFF
  692. #define JSC2_X2V_MASK 0xFFFF0000
  693. #define JSC2_Y2V_SHIFT 0
  694. #define JSC2_X2V_SHIFT 16
  695. /*
  696. * The following defines are for the flags in the MIDI control register.
  697. */
  698. #define MIDCR_TXE 0x00000001 /* Enable transmitting. */
  699. #define MIDCR_RXE 0x00000002 /* Enable receiving. */
  700. #define MIDCR_RIE 0x00000004 /* Interrupt upon tx ready. */
  701. #define MIDCR_TIE 0x00000008 /* Interrupt upon rx ready. */
  702. #define MIDCR_MLB 0x00000010 /* Enable midi loopback. */
  703. #define MIDCR_MRST 0x00000020 /* Reset interface. */
  704. /*
  705. * The following defines are for the flags in the MIDI status register.
  706. */
  707. #define MIDSR_TBF 0x00000001 /* Tx FIFO is full. */
  708. #define MIDSR_RBE 0x00000002 /* Rx FIFO is empty. */
  709. /*
  710. * The following defines are for the flags in the MIDI write port register.
  711. */
  712. #define MIDWP_MWD_MASK 0x000000FF
  713. #define MIDWP_MWD_SHIFT 0
  714. /*
  715. * The following defines are for the flags in the MIDI read port register.
  716. */
  717. #define MIDRP_MRD_MASK 0x000000FF
  718. #define MIDRP_MRD_SHIFT 0
  719. /*
  720. * The following defines are for the flags in the joystick GPIO register.
  721. */
  722. #define JSIO_DAX 0x00000001
  723. #define JSIO_DAY 0x00000002
  724. #define JSIO_DBX 0x00000004
  725. #define JSIO_DBY 0x00000008
  726. #define JSIO_AXOE 0x00000010
  727. #define JSIO_AYOE 0x00000020
  728. #define JSIO_BXOE 0x00000040
  729. #define JSIO_BYOE 0x00000080
  730. /*
  731. * The following defines are for the flags in the master async/sync serial
  732. * port enable register.
  733. */
  734. #ifndef NO_CS4612
  735. #define ASER_MASTER_ME 0x00000001
  736. #endif
  737. /*
  738. * The following defines are for the flags in the configuration interface
  739. * register.
  740. */
  741. #define CFGI_CLK 0x00000001
  742. #define CFGI_DOUT 0x00000002
  743. #define CFGI_DIN_EEN 0x00000004
  744. #define CFGI_EELD 0x00000008
  745. /*
  746. * The following defines are for the flags in the subsystem ID and vendor ID
  747. * register.
  748. */
  749. #define SSVID_VID_MASK 0x0000FFFF
  750. #define SSVID_SID_MASK 0xFFFF0000
  751. #define SSVID_VID_SHIFT 0
  752. #define SSVID_SID_SHIFT 16
  753. /*
  754. * The following defines are for the flags in the GPIO pin interface register.
  755. */
  756. #define GPIOR_VOLDN 0x00000001
  757. #define GPIOR_VOLUP 0x00000002
  758. #define GPIOR_SI2D 0x00000004
  759. #define GPIOR_SI2OE 0x00000008
  760. /*
  761. * The following defines are for the flags in the extended GPIO pin direction
  762. * register.
  763. */
  764. #ifndef NO_CS4612
  765. #define EGPIODR_GPOE0 0x00000001
  766. #define EGPIODR_GPOE1 0x00000002
  767. #define EGPIODR_GPOE2 0x00000004
  768. #define EGPIODR_GPOE3 0x00000008
  769. #define EGPIODR_GPOE4 0x00000010
  770. #define EGPIODR_GPOE5 0x00000020
  771. #define EGPIODR_GPOE6 0x00000040
  772. #define EGPIODR_GPOE7 0x00000080
  773. #define EGPIODR_GPOE8 0x00000100
  774. #endif
  775. /*
  776. * The following defines are for the flags in the extended GPIO pin polarity/
  777. * type register.
  778. */
  779. #ifndef NO_CS4612
  780. #define EGPIOPTR_GPPT0 0x00000001
  781. #define EGPIOPTR_GPPT1 0x00000002
  782. #define EGPIOPTR_GPPT2 0x00000004
  783. #define EGPIOPTR_GPPT3 0x00000008
  784. #define EGPIOPTR_GPPT4 0x00000010
  785. #define EGPIOPTR_GPPT5 0x00000020
  786. #define EGPIOPTR_GPPT6 0x00000040
  787. #define EGPIOPTR_GPPT7 0x00000080
  788. #define EGPIOPTR_GPPT8 0x00000100
  789. #endif
  790. /*
  791. * The following defines are for the flags in the extended GPIO pin sticky
  792. * register.
  793. */
  794. #ifndef NO_CS4612
  795. #define EGPIOTR_GPS0 0x00000001
  796. #define EGPIOTR_GPS1 0x00000002
  797. #define EGPIOTR_GPS2 0x00000004
  798. #define EGPIOTR_GPS3 0x00000008
  799. #define EGPIOTR_GPS4 0x00000010
  800. #define EGPIOTR_GPS5 0x00000020
  801. #define EGPIOTR_GPS6 0x00000040
  802. #define EGPIOTR_GPS7 0x00000080
  803. #define EGPIOTR_GPS8 0x00000100
  804. #endif
  805. /*
  806. * The following defines are for the flags in the extended GPIO ping wakeup
  807. * register.
  808. */
  809. #ifndef NO_CS4612
  810. #define EGPIOWR_GPW0 0x00000001
  811. #define EGPIOWR_GPW1 0x00000002
  812. #define EGPIOWR_GPW2 0x00000004
  813. #define EGPIOWR_GPW3 0x00000008
  814. #define EGPIOWR_GPW4 0x00000010
  815. #define EGPIOWR_GPW5 0x00000020
  816. #define EGPIOWR_GPW6 0x00000040
  817. #define EGPIOWR_GPW7 0x00000080
  818. #define EGPIOWR_GPW8 0x00000100
  819. #endif
  820. /*
  821. * The following defines are for the flags in the extended GPIO pin status
  822. * register.
  823. */
  824. #ifndef NO_CS4612
  825. #define EGPIOSR_GPS0 0x00000001
  826. #define EGPIOSR_GPS1 0x00000002
  827. #define EGPIOSR_GPS2 0x00000004
  828. #define EGPIOSR_GPS3 0x00000008
  829. #define EGPIOSR_GPS4 0x00000010
  830. #define EGPIOSR_GPS5 0x00000020
  831. #define EGPIOSR_GPS6 0x00000040
  832. #define EGPIOSR_GPS7 0x00000080
  833. #define EGPIOSR_GPS8 0x00000100
  834. #endif
  835. /*
  836. * The following defines are for the flags in the serial port 6 configuration
  837. * register.
  838. */
  839. #ifndef NO_CS4612
  840. #define SERC6_ASDO2EN 0x00000001
  841. #endif
  842. /*
  843. * The following defines are for the flags in the serial port 7 configuration
  844. * register.
  845. */
  846. #ifndef NO_CS4612
  847. #define SERC7_ASDI2EN 0x00000001
  848. #define SERC7_POSILB 0x00000002
  849. #define SERC7_SIPOLB 0x00000004
  850. #define SERC7_SOSILB 0x00000008
  851. #define SERC7_SISOLB 0x00000010
  852. #endif
  853. /*
  854. * The following defines are for the flags in the serial port AC link
  855. * configuration register.
  856. */
  857. #ifndef NO_CS4612
  858. #define SERACC_CHIP_TYPE_MASK 0x00000001
  859. #define SERACC_CHIP_TYPE_1_03 0x00000000
  860. #define SERACC_CHIP_TYPE_2_0 0x00000001
  861. #define SERACC_TWO_CODECS 0x00000002
  862. #define SERACC_MDM 0x00000004
  863. #define SERACC_HSP 0x00000008
  864. #define SERACC_ODT 0x00000010 /* only CS4630 */
  865. #endif
  866. /*
  867. * The following defines are for the flags in the AC97 control register 2.
  868. */
  869. #ifndef NO_CS4612
  870. #define ACCTL2_RSTN 0x00000001
  871. #define ACCTL2_ESYN 0x00000002
  872. #define ACCTL2_VFRM 0x00000004
  873. #define ACCTL2_DCV 0x00000008
  874. #define ACCTL2_CRW 0x00000010
  875. #define ACCTL2_ASYN 0x00000020
  876. #endif
  877. /*
  878. * The following defines are for the flags in the AC97 status register 2.
  879. */
  880. #ifndef NO_CS4612
  881. #define ACSTS2_CRDY 0x00000001
  882. #define ACSTS2_VSTS 0x00000002
  883. #endif
  884. /*
  885. * The following defines are for the flags in the AC97 output slot valid
  886. * register 2.
  887. */
  888. #ifndef NO_CS4612
  889. #define ACOSV2_SLV3 0x00000001
  890. #define ACOSV2_SLV4 0x00000002
  891. #define ACOSV2_SLV5 0x00000004
  892. #define ACOSV2_SLV6 0x00000008
  893. #define ACOSV2_SLV7 0x00000010
  894. #define ACOSV2_SLV8 0x00000020
  895. #define ACOSV2_SLV9 0x00000040
  896. #define ACOSV2_SLV10 0x00000080
  897. #define ACOSV2_SLV11 0x00000100
  898. #define ACOSV2_SLV12 0x00000200
  899. #endif
  900. /*
  901. * The following defines are for the flags in the AC97 command address
  902. * register 2.
  903. */
  904. #ifndef NO_CS4612
  905. #define ACCAD2_CI_MASK 0x0000007F
  906. #define ACCAD2_CI_SHIFT 0
  907. #endif
  908. /*
  909. * The following defines are for the flags in the AC97 command data register
  910. * 2.
  911. */
  912. #ifndef NO_CS4612
  913. #define ACCDA2_CD_MASK 0x0000FFFF
  914. #define ACCDA2_CD_SHIFT 0
  915. #endif
  916. /*
  917. * The following defines are for the flags in the AC97 input slot valid
  918. * register 2.
  919. */
  920. #ifndef NO_CS4612
  921. #define ACISV2_ISV3 0x00000001
  922. #define ACISV2_ISV4 0x00000002
  923. #define ACISV2_ISV5 0x00000004
  924. #define ACISV2_ISV6 0x00000008
  925. #define ACISV2_ISV7 0x00000010
  926. #define ACISV2_ISV8 0x00000020
  927. #define ACISV2_ISV9 0x00000040
  928. #define ACISV2_ISV10 0x00000080
  929. #define ACISV2_ISV11 0x00000100
  930. #define ACISV2_ISV12 0x00000200
  931. #endif
  932. /*
  933. * The following defines are for the flags in the AC97 status address
  934. * register 2.
  935. */
  936. #ifndef NO_CS4612
  937. #define ACSAD2_SI_MASK 0x0000007F
  938. #define ACSAD2_SI_SHIFT 0
  939. #endif
  940. /*
  941. * The following defines are for the flags in the AC97 status data register 2.
  942. */
  943. #ifndef NO_CS4612
  944. #define ACSDA2_SD_MASK 0x0000FFFF
  945. #define ACSDA2_SD_SHIFT 0
  946. #endif
  947. /*
  948. * The following defines are for the flags in the I/O trap address and control
  949. * registers (all 12).
  950. */
  951. #ifndef NO_CS4612
  952. #define IOTAC_SA_MASK 0x0000FFFF
  953. #define IOTAC_MSK_MASK 0x000F0000
  954. #define IOTAC_IODC_MASK 0x06000000
  955. #define IOTAC_IODC_16_BIT 0x00000000
  956. #define IOTAC_IODC_10_BIT 0x02000000
  957. #define IOTAC_IODC_12_BIT 0x04000000
  958. #define IOTAC_WSPI 0x08000000
  959. #define IOTAC_RSPI 0x10000000
  960. #define IOTAC_WSE 0x20000000
  961. #define IOTAC_WE 0x40000000
  962. #define IOTAC_RE 0x80000000
  963. #define IOTAC_SA_SHIFT 0
  964. #define IOTAC_MSK_SHIFT 16
  965. #endif
  966. /*
  967. * The following defines are for the flags in the I/O trap fast read registers
  968. * (all 8).
  969. */
  970. #ifndef NO_CS4612
  971. #define IOTFR_D_MASK 0x0000FFFF
  972. #define IOTFR_A_MASK 0x000F0000
  973. #define IOTFR_R_MASK 0x0F000000
  974. #define IOTFR_ALL 0x40000000
  975. #define IOTFR_VL 0x80000000
  976. #define IOTFR_D_SHIFT 0
  977. #define IOTFR_A_SHIFT 16
  978. #define IOTFR_R_SHIFT 24
  979. #endif
  980. /*
  981. * The following defines are for the flags in the I/O trap FIFO register.
  982. */
  983. #ifndef NO_CS4612
  984. #define IOTFIFO_BA_MASK 0x00003FFF
  985. #define IOTFIFO_S_MASK 0x00FF0000
  986. #define IOTFIFO_OF 0x40000000
  987. #define IOTFIFO_SPIOF 0x80000000
  988. #define IOTFIFO_BA_SHIFT 0
  989. #define IOTFIFO_S_SHIFT 16
  990. #endif
  991. /*
  992. * The following defines are for the flags in the I/O trap retry read data
  993. * register.
  994. */
  995. #ifndef NO_CS4612
  996. #define IOTRRD_D_MASK 0x0000FFFF
  997. #define IOTRRD_RDV 0x80000000
  998. #define IOTRRD_D_SHIFT 0
  999. #endif
  1000. /*
  1001. * The following defines are for the flags in the I/O trap FIFO pointer
  1002. * register.
  1003. */
  1004. #ifndef NO_CS4612
  1005. #define IOTFP_CA_MASK 0x00003FFF
  1006. #define IOTFP_PA_MASK 0x3FFF0000
  1007. #define IOTFP_CA_SHIFT 0
  1008. #define IOTFP_PA_SHIFT 16
  1009. #endif
  1010. /*
  1011. * The following defines are for the flags in the I/O trap control register.
  1012. */
  1013. #ifndef NO_CS4612
  1014. #define IOTCR_ITD 0x00000001
  1015. #define IOTCR_HRV 0x00000002
  1016. #define IOTCR_SRV 0x00000004
  1017. #define IOTCR_DTI 0x00000008
  1018. #define IOTCR_DFI 0x00000010
  1019. #define IOTCR_DDP 0x00000020
  1020. #define IOTCR_JTE 0x00000040
  1021. #define IOTCR_PPE 0x00000080
  1022. #endif
  1023. /*
  1024. * The following defines are for the flags in the direct PCI data register.
  1025. */
  1026. #ifndef NO_CS4612
  1027. #define DPCID_D_MASK 0xFFFFFFFF
  1028. #define DPCID_D_SHIFT 0
  1029. #endif
  1030. /*
  1031. * The following defines are for the flags in the direct PCI address register.
  1032. */
  1033. #ifndef NO_CS4612
  1034. #define DPCIA_A_MASK 0xFFFFFFFF
  1035. #define DPCIA_A_SHIFT 0
  1036. #endif
  1037. /*
  1038. * The following defines are for the flags in the direct PCI command register.
  1039. */
  1040. #ifndef NO_CS4612
  1041. #define DPCIC_C_MASK 0x0000000F
  1042. #define DPCIC_C_IOREAD 0x00000002
  1043. #define DPCIC_C_IOWRITE 0x00000003
  1044. #define DPCIC_BE_MASK 0x000000F0
  1045. #endif
  1046. /*
  1047. * The following defines are for the flags in the PC/PCI request register.
  1048. */
  1049. #ifndef NO_CS4612
  1050. #define PCPCIR_RDC_MASK 0x00000007
  1051. #define PCPCIR_C_MASK 0x00007000
  1052. #define PCPCIR_REQ 0x00008000
  1053. #define PCPCIR_RDC_SHIFT 0
  1054. #define PCPCIR_C_SHIFT 12
  1055. #endif
  1056. /*
  1057. * The following defines are for the flags in the PC/PCI grant register.
  1058. */
  1059. #ifndef NO_CS4612
  1060. #define PCPCIG_GDC_MASK 0x00000007
  1061. #define PCPCIG_VL 0x00008000
  1062. #define PCPCIG_GDC_SHIFT 0
  1063. #endif
  1064. /*
  1065. * The following defines are for the flags in the PC/PCI master enable
  1066. * register.
  1067. */
  1068. #ifndef NO_CS4612
  1069. #define PCPCIEN_EN 0x00000001
  1070. #endif
  1071. /*
  1072. * The following defines are for the flags in the extended PCI power
  1073. * management control register.
  1074. */
  1075. #ifndef NO_CS4612
  1076. #define EPCIPMC_GWU 0x00000001
  1077. #define EPCIPMC_FSPC 0x00000002
  1078. #endif
  1079. /*
  1080. * The following defines are for the flags in the SP control register.
  1081. */
  1082. #define SPCR_RUN 0x00000001
  1083. #define SPCR_STPFR 0x00000002
  1084. #define SPCR_RUNFR 0x00000004
  1085. #define SPCR_TICK 0x00000008
  1086. #define SPCR_DRQEN 0x00000020
  1087. #define SPCR_RSTSP 0x00000040
  1088. #define SPCR_OREN 0x00000080
  1089. #ifndef NO_CS4612
  1090. #define SPCR_PCIINT 0x00000100
  1091. #define SPCR_OINTD 0x00000200
  1092. #define SPCR_CRE 0x00008000
  1093. #endif
  1094. /*
  1095. * The following defines are for the flags in the debug index register.
  1096. */
  1097. #define DREG_REGID_MASK 0x0000007F
  1098. #define DREG_DEBUG 0x00000080
  1099. #define DREG_RGBK_MASK 0x00000700
  1100. #define DREG_TRAP 0x00000800
  1101. #if !defined(NO_CS4612)
  1102. #if !defined(NO_CS4615)
  1103. #define DREG_TRAPX 0x00001000
  1104. #endif
  1105. #endif
  1106. #define DREG_REGID_SHIFT 0
  1107. #define DREG_RGBK_SHIFT 8
  1108. #define DREG_RGBK_REGID_MASK 0x0000077F
  1109. #define DREG_REGID_R0 0x00000010
  1110. #define DREG_REGID_R1 0x00000011
  1111. #define DREG_REGID_R2 0x00000012
  1112. #define DREG_REGID_R3 0x00000013
  1113. #define DREG_REGID_R4 0x00000014
  1114. #define DREG_REGID_R5 0x00000015
  1115. #define DREG_REGID_R6 0x00000016
  1116. #define DREG_REGID_R7 0x00000017
  1117. #define DREG_REGID_R8 0x00000018
  1118. #define DREG_REGID_R9 0x00000019
  1119. #define DREG_REGID_RA 0x0000001A
  1120. #define DREG_REGID_RB 0x0000001B
  1121. #define DREG_REGID_RC 0x0000001C
  1122. #define DREG_REGID_RD 0x0000001D
  1123. #define DREG_REGID_RE 0x0000001E
  1124. #define DREG_REGID_RF 0x0000001F
  1125. #define DREG_REGID_RA_BUS_LOW 0x00000020
  1126. #define DREG_REGID_RA_BUS_HIGH 0x00000038
  1127. #define DREG_REGID_YBUS_LOW 0x00000050
  1128. #define DREG_REGID_YBUS_HIGH 0x00000058
  1129. #define DREG_REGID_TRAP_0 0x00000100
  1130. #define DREG_REGID_TRAP_1 0x00000101
  1131. #define DREG_REGID_TRAP_2 0x00000102
  1132. #define DREG_REGID_TRAP_3 0x00000103
  1133. #define DREG_REGID_TRAP_4 0x00000104
  1134. #define DREG_REGID_TRAP_5 0x00000105
  1135. #define DREG_REGID_TRAP_6 0x00000106
  1136. #define DREG_REGID_TRAP_7 0x00000107
  1137. #define DREG_REGID_INDIRECT_ADDRESS 0x0000010E
  1138. #define DREG_REGID_TOP_OF_STACK 0x0000010F
  1139. #if !defined(NO_CS4612)
  1140. #if !defined(NO_CS4615)
  1141. #define DREG_REGID_TRAP_8 0x00000110
  1142. #define DREG_REGID_TRAP_9 0x00000111
  1143. #define DREG_REGID_TRAP_10 0x00000112
  1144. #define DREG_REGID_TRAP_11 0x00000113
  1145. #define DREG_REGID_TRAP_12 0x00000114
  1146. #define DREG_REGID_TRAP_13 0x00000115
  1147. #define DREG_REGID_TRAP_14 0x00000116
  1148. #define DREG_REGID_TRAP_15 0x00000117
  1149. #define DREG_REGID_TRAP_16 0x00000118
  1150. #define DREG_REGID_TRAP_17 0x00000119
  1151. #define DREG_REGID_TRAP_18 0x0000011A
  1152. #define DREG_REGID_TRAP_19 0x0000011B
  1153. #define DREG_REGID_TRAP_20 0x0000011C
  1154. #define DREG_REGID_TRAP_21 0x0000011D
  1155. #define DREG_REGID_TRAP_22 0x0000011E
  1156. #define DREG_REGID_TRAP_23 0x0000011F
  1157. #endif
  1158. #endif
  1159. #define DREG_REGID_RSA0_LOW 0x00000200
  1160. #define DREG_REGID_RSA0_HIGH 0x00000201
  1161. #define DREG_REGID_RSA1_LOW 0x00000202
  1162. #define DREG_REGID_RSA1_HIGH 0x00000203
  1163. #define DREG_REGID_RSA2 0x00000204
  1164. #define DREG_REGID_RSA3 0x00000205
  1165. #define DREG_REGID_RSI0_LOW 0x00000206
  1166. #define DREG_REGID_RSI0_HIGH 0x00000207
  1167. #define DREG_REGID_RSI1 0x00000208
  1168. #define DREG_REGID_RSI2 0x00000209
  1169. #define DREG_REGID_SAGUSTATUS 0x0000020A
  1170. #define DREG_REGID_RSCONFIG01_LOW 0x0000020B
  1171. #define DREG_REGID_RSCONFIG01_HIGH 0x0000020C
  1172. #define DREG_REGID_RSCONFIG23_LOW 0x0000020D
  1173. #define DREG_REGID_RSCONFIG23_HIGH 0x0000020E
  1174. #define DREG_REGID_RSDMA01E 0x0000020F
  1175. #define DREG_REGID_RSDMA23E 0x00000210
  1176. #define DREG_REGID_RSD0_LOW 0x00000211
  1177. #define DREG_REGID_RSD0_HIGH 0x00000212
  1178. #define DREG_REGID_RSD1_LOW 0x00000213
  1179. #define DREG_REGID_RSD1_HIGH 0x00000214
  1180. #define DREG_REGID_RSD2_LOW 0x00000215
  1181. #define DREG_REGID_RSD2_HIGH 0x00000216
  1182. #define DREG_REGID_RSD3_LOW 0x00000217
  1183. #define DREG_REGID_RSD3_HIGH 0x00000218
  1184. #define DREG_REGID_SRAR_HIGH 0x0000021A
  1185. #define DREG_REGID_SRAR_LOW 0x0000021B
  1186. #define DREG_REGID_DMA_STATE 0x0000021C
  1187. #define DREG_REGID_CURRENT_DMA_STREAM 0x0000021D
  1188. #define DREG_REGID_NEXT_DMA_STREAM 0x0000021E
  1189. #define DREG_REGID_CPU_STATUS 0x00000300
  1190. #define DREG_REGID_MAC_MODE 0x00000301
  1191. #define DREG_REGID_STACK_AND_REPEAT 0x00000302
  1192. #define DREG_REGID_INDEX0 0x00000304
  1193. #define DREG_REGID_INDEX1 0x00000305
  1194. #define DREG_REGID_DMA_STATE_0_3 0x00000400
  1195. #define DREG_REGID_DMA_STATE_4_7 0x00000404
  1196. #define DREG_REGID_DMA_STATE_8_11 0x00000408
  1197. #define DREG_REGID_DMA_STATE_12_15 0x0000040C
  1198. #define DREG_REGID_DMA_STATE_16_19 0x00000410
  1199. #define DREG_REGID_DMA_STATE_20_23 0x00000414
  1200. #define DREG_REGID_DMA_STATE_24_27 0x00000418
  1201. #define DREG_REGID_DMA_STATE_28_31 0x0000041C
  1202. #define DREG_REGID_DMA_STATE_32_35 0x00000420
  1203. #define DREG_REGID_DMA_STATE_36_39 0x00000424
  1204. #define DREG_REGID_DMA_STATE_40_43 0x00000428
  1205. #define DREG_REGID_DMA_STATE_44_47 0x0000042C
  1206. #define DREG_REGID_DMA_STATE_48_51 0x00000430
  1207. #define DREG_REGID_DMA_STATE_52_55 0x00000434
  1208. #define DREG_REGID_DMA_STATE_56_59 0x00000438
  1209. #define DREG_REGID_DMA_STATE_60_63 0x0000043C
  1210. #define DREG_REGID_DMA_STATE_64_67 0x00000440
  1211. #define DREG_REGID_DMA_STATE_68_71 0x00000444
  1212. #define DREG_REGID_DMA_STATE_72_75 0x00000448
  1213. #define DREG_REGID_DMA_STATE_76_79 0x0000044C
  1214. #define DREG_REGID_DMA_STATE_80_83 0x00000450
  1215. #define DREG_REGID_DMA_STATE_84_87 0x00000454
  1216. #define DREG_REGID_DMA_STATE_88_91 0x00000458
  1217. #define DREG_REGID_DMA_STATE_92_95 0x0000045C
  1218. #define DREG_REGID_TRAP_SELECT 0x00000500
  1219. #define DREG_REGID_TRAP_WRITE_0 0x00000500
  1220. #define DREG_REGID_TRAP_WRITE_1 0x00000501
  1221. #define DREG_REGID_TRAP_WRITE_2 0x00000502
  1222. #define DREG_REGID_TRAP_WRITE_3 0x00000503
  1223. #define DREG_REGID_TRAP_WRITE_4 0x00000504
  1224. #define DREG_REGID_TRAP_WRITE_5 0x00000505
  1225. #define DREG_REGID_TRAP_WRITE_6 0x00000506
  1226. #define DREG_REGID_TRAP_WRITE_7 0x00000507
  1227. #if !defined(NO_CS4612)
  1228. #if !defined(NO_CS4615)
  1229. #define DREG_REGID_TRAP_WRITE_8 0x00000510
  1230. #define DREG_REGID_TRAP_WRITE_9 0x00000511
  1231. #define DREG_REGID_TRAP_WRITE_10 0x00000512
  1232. #define DREG_REGID_TRAP_WRITE_11 0x00000513
  1233. #define DREG_REGID_TRAP_WRITE_12 0x00000514
  1234. #define DREG_REGID_TRAP_WRITE_13 0x00000515
  1235. #define DREG_REGID_TRAP_WRITE_14 0x00000516
  1236. #define DREG_REGID_TRAP_WRITE_15 0x00000517
  1237. #define DREG_REGID_TRAP_WRITE_16 0x00000518
  1238. #define DREG_REGID_TRAP_WRITE_17 0x00000519
  1239. #define DREG_REGID_TRAP_WRITE_18 0x0000051A
  1240. #define DREG_REGID_TRAP_WRITE_19 0x0000051B
  1241. #define DREG_REGID_TRAP_WRITE_20 0x0000051C
  1242. #define DREG_REGID_TRAP_WRITE_21 0x0000051D
  1243. #define DREG_REGID_TRAP_WRITE_22 0x0000051E
  1244. #define DREG_REGID_TRAP_WRITE_23 0x0000051F
  1245. #endif
  1246. #endif
  1247. #define DREG_REGID_MAC0_ACC0_LOW 0x00000600
  1248. #define DREG_REGID_MAC0_ACC1_LOW 0x00000601
  1249. #define DREG_REGID_MAC0_ACC2_LOW 0x00000602
  1250. #define DREG_REGID_MAC0_ACC3_LOW 0x00000603
  1251. #define DREG_REGID_MAC1_ACC0_LOW 0x00000604
  1252. #define DREG_REGID_MAC1_ACC1_LOW 0x00000605
  1253. #define DREG_REGID_MAC1_ACC2_LOW 0x00000606
  1254. #define DREG_REGID_MAC1_ACC3_LOW 0x00000607
  1255. #define DREG_REGID_MAC0_ACC0_MID 0x00000608
  1256. #define DREG_REGID_MAC0_ACC1_MID 0x00000609
  1257. #define DREG_REGID_MAC0_ACC2_MID 0x0000060A
  1258. #define DREG_REGID_MAC0_ACC3_MID 0x0000060B
  1259. #define DREG_REGID_MAC1_ACC0_MID 0x0000060C
  1260. #define DREG_REGID_MAC1_ACC1_MID 0x0000060D
  1261. #define DREG_REGID_MAC1_ACC2_MID 0x0000060E
  1262. #define DREG_REGID_MAC1_ACC3_MID 0x0000060F
  1263. #define DREG_REGID_MAC0_ACC0_HIGH 0x00000610
  1264. #define DREG_REGID_MAC0_ACC1_HIGH 0x00000611
  1265. #define DREG_REGID_MAC0_ACC2_HIGH 0x00000612
  1266. #define DREG_REGID_MAC0_ACC3_HIGH 0x00000613
  1267. #define DREG_REGID_MAC1_ACC0_HIGH 0x00000614
  1268. #define DREG_REGID_MAC1_ACC1_HIGH 0x00000615
  1269. #define DREG_REGID_MAC1_ACC2_HIGH 0x00000616
  1270. #define DREG_REGID_MAC1_ACC3_HIGH 0x00000617
  1271. #define DREG_REGID_RSHOUT_LOW 0x00000620
  1272. #define DREG_REGID_RSHOUT_MID 0x00000628
  1273. #define DREG_REGID_RSHOUT_HIGH 0x00000630
  1274. /*
  1275. * The following defines are for the flags in the DMA stream requestor write
  1276. */
  1277. #define DSRWP_DSR_MASK 0x0000000F
  1278. #define DSRWP_DSR_BG_RQ 0x00000001
  1279. #define DSRWP_DSR_PRIORITY_MASK 0x00000006
  1280. #define DSRWP_DSR_PRIORITY_0 0x00000000
  1281. #define DSRWP_DSR_PRIORITY_1 0x00000002
  1282. #define DSRWP_DSR_PRIORITY_2 0x00000004
  1283. #define DSRWP_DSR_PRIORITY_3 0x00000006
  1284. #define DSRWP_DSR_RQ_PENDING 0x00000008
  1285. /*
  1286. * The following defines are for the flags in the trap write port register.
  1287. */
  1288. #define TWPR_TW_MASK 0x0000FFFF
  1289. #define TWPR_TW_SHIFT 0
  1290. /*
  1291. * The following defines are for the flags in the stack pointer write
  1292. * register.
  1293. */
  1294. #define SPWR_STKP_MASK 0x0000000F
  1295. #define SPWR_STKP_SHIFT 0
  1296. /*
  1297. * The following defines are for the flags in the SP interrupt register.
  1298. */
  1299. #define SPIR_FRI 0x00000001
  1300. #define SPIR_DOI 0x00000002
  1301. #define SPIR_GPI2 0x00000004
  1302. #define SPIR_GPI3 0x00000008
  1303. #define SPIR_IP0 0x00000010
  1304. #define SPIR_IP1 0x00000020
  1305. #define SPIR_IP2 0x00000040
  1306. #define SPIR_IP3 0x00000080
  1307. /*
  1308. * The following defines are for the flags in the functional group 1 register.
  1309. */
  1310. #define FGR1_F1S_MASK 0x0000FFFF
  1311. #define FGR1_F1S_SHIFT 0
  1312. /*
  1313. * The following defines are for the flags in the SP clock status register.
  1314. */
  1315. #define SPCS_FRI 0x00000001
  1316. #define SPCS_DOI 0x00000002
  1317. #define SPCS_GPI2 0x00000004
  1318. #define SPCS_GPI3 0x00000008
  1319. #define SPCS_IP0 0x00000010
  1320. #define SPCS_IP1 0x00000020
  1321. #define SPCS_IP2 0x00000040
  1322. #define SPCS_IP3 0x00000080
  1323. #define SPCS_SPRUN 0x00000100
  1324. #define SPCS_SLEEP 0x00000200
  1325. #define SPCS_FG 0x00000400
  1326. #define SPCS_ORUN 0x00000800
  1327. #define SPCS_IRQ 0x00001000
  1328. #define SPCS_FGN_MASK 0x0000E000
  1329. #define SPCS_FGN_SHIFT 13
  1330. /*
  1331. * The following defines are for the flags in the SP DMA requestor status
  1332. * register.
  1333. */
  1334. #define SDSR_DCS_MASK 0x000000FF
  1335. #define SDSR_DCS_SHIFT 0
  1336. #define SDSR_DCS_NONE 0x00000007
  1337. /*
  1338. * The following defines are for the flags in the frame timer register.
  1339. */
  1340. #define FRMT_FTV_MASK 0x0000FFFF
  1341. #define FRMT_FTV_SHIFT 0
  1342. /*
  1343. * The following defines are for the flags in the frame timer current count
  1344. * register.
  1345. */
  1346. #define FRCC_FCC_MASK 0x0000FFFF
  1347. #define FRCC_FCC_SHIFT 0
  1348. /*
  1349. * The following defines are for the flags in the frame timer save count
  1350. * register.
  1351. */
  1352. #define FRSC_FCS_MASK 0x0000FFFF
  1353. #define FRSC_FCS_SHIFT 0
  1354. /*
  1355. * The following define the various flags stored in the scatter/gather
  1356. * descriptors.
  1357. */
  1358. #define DMA_SG_NEXT_ENTRY_MASK 0x00000FF8
  1359. #define DMA_SG_SAMPLE_END_MASK 0x0FFF0000
  1360. #define DMA_SG_SAMPLE_END_FLAG 0x10000000
  1361. #define DMA_SG_LOOP_END_FLAG 0x20000000
  1362. #define DMA_SG_SIGNAL_END_FLAG 0x40000000
  1363. #define DMA_SG_SIGNAL_PAGE_FLAG 0x80000000
  1364. #define DMA_SG_NEXT_ENTRY_SHIFT 3
  1365. #define DMA_SG_SAMPLE_END_SHIFT 16
  1366. /*
  1367. * The following define the offsets of the fields within the on-chip generic
  1368. * DMA requestor.
  1369. */
  1370. #define DMA_RQ_CONTROL1 0x00000000
  1371. #define DMA_RQ_CONTROL2 0x00000004
  1372. #define DMA_RQ_SOURCE_ADDR 0x00000008
  1373. #define DMA_RQ_DESTINATION_ADDR 0x0000000C
  1374. #define DMA_RQ_NEXT_PAGE_ADDR 0x00000010
  1375. #define DMA_RQ_NEXT_PAGE_SGDESC 0x00000014
  1376. #define DMA_RQ_LOOP_START_ADDR 0x00000018
  1377. #define DMA_RQ_POST_LOOP_ADDR 0x0000001C
  1378. #define DMA_RQ_PAGE_MAP_ADDR 0x00000020
  1379. /*
  1380. * The following defines are for the flags in the first control word of the
  1381. * on-chip generic DMA requestor.
  1382. */
  1383. #define DMA_RQ_C1_COUNT_MASK 0x000003FF
  1384. #define DMA_RQ_C1_DESTINATION_SCATTER 0x00001000
  1385. #define DMA_RQ_C1_SOURCE_GATHER 0x00002000
  1386. #define DMA_RQ_C1_DONE_FLAG 0x00004000
  1387. #define DMA_RQ_C1_OPTIMIZE_STATE 0x00008000
  1388. #define DMA_RQ_C1_SAMPLE_END_STATE_MASK 0x00030000
  1389. #define DMA_RQ_C1_FULL_PAGE 0x00000000
  1390. #define DMA_RQ_C1_BEFORE_SAMPLE_END 0x00010000
  1391. #define DMA_RQ_C1_PAGE_MAP_ERROR 0x00020000
  1392. #define DMA_RQ_C1_AT_SAMPLE_END 0x00030000
  1393. #define DMA_RQ_C1_LOOP_END_STATE_MASK 0x000C0000
  1394. #define DMA_RQ_C1_NOT_LOOP_END 0x00000000
  1395. #define DMA_RQ_C1_BEFORE_LOOP_END 0x00040000
  1396. #define DMA_RQ_C1_2PAGE_LOOP_BEGIN 0x00080000
  1397. #define DMA_RQ_C1_LOOP_BEGIN 0x000C0000
  1398. #define DMA_RQ_C1_PAGE_MAP_MASK 0x00300000
  1399. #define DMA_RQ_C1_PM_NONE_PENDING 0x00000000
  1400. #define DMA_RQ_C1_PM_NEXT_PENDING 0x00100000
  1401. #define DMA_RQ_C1_PM_RESERVED 0x00200000
  1402. #define DMA_RQ_C1_PM_LOOP_NEXT_PENDING 0x00300000
  1403. #define DMA_RQ_C1_WRITEBACK_DEST_FLAG 0x00400000
  1404. #define DMA_RQ_C1_WRITEBACK_SRC_FLAG 0x00800000
  1405. #define DMA_RQ_C1_DEST_SIZE_MASK 0x07000000
  1406. #define DMA_RQ_C1_DEST_LINEAR 0x00000000
  1407. #define DMA_RQ_C1_DEST_MOD16 0x01000000
  1408. #define DMA_RQ_C1_DEST_MOD32 0x02000000
  1409. #define DMA_RQ_C1_DEST_MOD64 0x03000000
  1410. #define DMA_RQ_C1_DEST_MOD128 0x04000000
  1411. #define DMA_RQ_C1_DEST_MOD256 0x05000000
  1412. #define DMA_RQ_C1_DEST_MOD512 0x06000000
  1413. #define DMA_RQ_C1_DEST_MOD1024 0x07000000
  1414. #define DMA_RQ_C1_DEST_ON_HOST 0x08000000
  1415. #define DMA_RQ_C1_SOURCE_SIZE_MASK 0x70000000
  1416. #define DMA_RQ_C1_SOURCE_LINEAR 0x00000000
  1417. #define DMA_RQ_C1_SOURCE_MOD16 0x10000000
  1418. #define DMA_RQ_C1_SOURCE_MOD32 0x20000000
  1419. #define DMA_RQ_C1_SOURCE_MOD64 0x30000000
  1420. #define DMA_RQ_C1_SOURCE_MOD128 0x40000000
  1421. #define DMA_RQ_C1_SOURCE_MOD256 0x50000000
  1422. #define DMA_RQ_C1_SOURCE_MOD512 0x60000000
  1423. #define DMA_RQ_C1_SOURCE_MOD1024 0x70000000
  1424. #define DMA_RQ_C1_SOURCE_ON_HOST 0x80000000
  1425. #define DMA_RQ_C1_COUNT_SHIFT 0
  1426. /*
  1427. * The following defines are for the flags in the second control word of the
  1428. * on-chip generic DMA requestor.
  1429. */
  1430. #define DMA_RQ_C2_VIRTUAL_CHANNEL_MASK 0x0000003F
  1431. #define DMA_RQ_C2_VIRTUAL_SIGNAL_MASK 0x00000300
  1432. #define DMA_RQ_C2_NO_VIRTUAL_SIGNAL 0x00000000
  1433. #define DMA_RQ_C2_SIGNAL_EVERY_DMA 0x00000100
  1434. #define DMA_RQ_C2_SIGNAL_SOURCE_PINGPONG 0x00000200
  1435. #define DMA_RQ_C2_SIGNAL_DEST_PINGPONG 0x00000300
  1436. #define DMA_RQ_C2_AUDIO_CONVERT_MASK 0x0000F000
  1437. #define DMA_RQ_C2_AC_NONE 0x00000000
  1438. #define DMA_RQ_C2_AC_8_TO_16_BIT 0x00001000
  1439. #define DMA_RQ_C2_AC_MONO_TO_STEREO 0x00002000
  1440. #define DMA_RQ_C2_AC_ENDIAN_CONVERT 0x00004000
  1441. #define DMA_RQ_C2_AC_SIGNED_CONVERT 0x00008000
  1442. #define DMA_RQ_C2_LOOP_END_MASK 0x0FFF0000
  1443. #define DMA_RQ_C2_LOOP_MASK 0x30000000
  1444. #define DMA_RQ_C2_NO_LOOP 0x00000000
  1445. #define DMA_RQ_C2_ONE_PAGE_LOOP 0x10000000
  1446. #define DMA_RQ_C2_TWO_PAGE_LOOP 0x20000000
  1447. #define DMA_RQ_C2_MULTI_PAGE_LOOP 0x30000000
  1448. #define DMA_RQ_C2_SIGNAL_LOOP_BACK 0x40000000
  1449. #define DMA_RQ_C2_SIGNAL_POST_BEGIN_PAGE 0x80000000
  1450. #define DMA_RQ_C2_VIRTUAL_CHANNEL_SHIFT 0
  1451. #define DMA_RQ_C2_LOOP_END_SHIFT 16
  1452. /*
  1453. * The following defines are for the flags in the source and destination words
  1454. * of the on-chip generic DMA requestor.
  1455. */
  1456. #define DMA_RQ_SD_ADDRESS_MASK 0x0000FFFF
  1457. #define DMA_RQ_SD_MEMORY_ID_MASK 0x000F0000
  1458. #define DMA_RQ_SD_SP_PARAM_ADDR 0x00000000
  1459. #define DMA_RQ_SD_SP_SAMPLE_ADDR 0x00010000
  1460. #define DMA_RQ_SD_SP_PROGRAM_ADDR 0x00020000
  1461. #define DMA_RQ_SD_SP_DEBUG_ADDR 0x00030000
  1462. #define DMA_RQ_SD_OMNIMEM_ADDR 0x000E0000
  1463. #define DMA_RQ_SD_END_FLAG 0x40000000
  1464. #define DMA_RQ_SD_ERROR_FLAG 0x80000000
  1465. #define DMA_RQ_SD_ADDRESS_SHIFT 0
  1466. /*
  1467. * The following defines are for the flags in the page map address word of the
  1468. * on-chip generic DMA requestor.
  1469. */
  1470. #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_MASK 0x00000FF8
  1471. #define DMA_RQ_PMA_PAGE_TABLE_MASK 0xFFFFF000
  1472. #define DMA_RQ_PMA_LOOP_THIRD_PAGE_ENTRY_SHIFT 3
  1473. #define DMA_RQ_PMA_PAGE_TABLE_SHIFT 12
  1474. #define BA1_VARIDEC_BUF_1 0x000
  1475. #define BA1_PDTC 0x0c0 /* BA1_PLAY_DMA_TRANSACTION_COUNT_REG */
  1476. #define BA1_PFIE 0x0c4 /* BA1_PLAY_FORMAT_&_INTERRUPT_ENABLE_REG */
  1477. #define BA1_PBA 0x0c8 /* BA1_PLAY_BUFFER_ADDRESS */
  1478. #define BA1_PVOL 0x0f8 /* BA1_PLAY_VOLUME_REG */
  1479. #define BA1_PSRC 0x288 /* BA1_PLAY_SAMPLE_RATE_CORRECTION_REG */
  1480. #define BA1_PCTL 0x2a4 /* BA1_PLAY_CONTROL_REG */
  1481. #define BA1_PPI 0x2b4 /* BA1_PLAY_PHASE_INCREMENT_REG */
  1482. #define BA1_CCTL 0x064 /* BA1_CAPTURE_CONTROL_REG */
  1483. #define BA1_CIE 0x104 /* BA1_CAPTURE_INTERRUPT_ENABLE_REG */
  1484. #define BA1_CBA 0x10c /* BA1_CAPTURE_BUFFER_ADDRESS */
  1485. #define BA1_CSRC 0x2c8 /* BA1_CAPTURE_SAMPLE_RATE_CORRECTION_REG */
  1486. #define BA1_CCI 0x2d8 /* BA1_CAPTURE_COEFFICIENT_INCREMENT_REG */
  1487. #define BA1_CD 0x2e0 /* BA1_CAPTURE_DELAY_REG */
  1488. #define BA1_CPI 0x2f4 /* BA1_CAPTURE_PHASE_INCREMENT_REG */
  1489. #define BA1_CVOL 0x2f8 /* BA1_CAPTURE_VOLUME_REG */
  1490. #define BA1_CFG1 0x134 /* BA1_CAPTURE_FRAME_GROUP_1_REG */
  1491. #define BA1_CFG2 0x138 /* BA1_CAPTURE_FRAME_GROUP_2_REG */
  1492. #define BA1_CCST 0x13c /* BA1_CAPTURE_CONSTANT_REG */
  1493. #define BA1_CSPB 0x340 /* BA1_CAPTURE_SPB_ADDRESS */
  1494. /*
  1495. *
  1496. */
  1497. #define CS46XX_MODE_OUTPUT (1<<0) /* MIDI UART - output */
  1498. #define CS46XX_MODE_INPUT (1<<1) /* MIDI UART - input */
  1499. /*
  1500. *
  1501. */
  1502. #define SAVE_REG_MAX 0x10
  1503. #define POWER_DOWN_ALL 0x7f0f
  1504. /* maxinum number of AC97 codecs connected, AC97 2.0 defined 4 */
  1505. #define MAX_NR_AC97 4
  1506. #define CS46XX_PRIMARY_CODEC_INDEX 0
  1507. #define CS46XX_SECONDARY_CODEC_INDEX 1
  1508. #define CS46XX_SECONDARY_CODEC_OFFSET 0x80
  1509. #define CS46XX_DSP_CAPTURE_CHANNEL 1
  1510. /* capture */
  1511. #define CS46XX_DSP_CAPTURE_CHANNEL 1
  1512. /* mixer */
  1513. #define CS46XX_MIXER_SPDIF_INPUT_ELEMENT 1
  1514. #define CS46XX_MIXER_SPDIF_OUTPUT_ELEMENT 2
  1515. struct snd_cs46xx_pcm {
  1516. struct snd_dma_buffer hw_buf;
  1517. unsigned int ctl;
  1518. unsigned int shift; /* Shift count to trasform frames in bytes */
  1519. struct snd_pcm_indirect pcm_rec;
  1520. struct snd_pcm_substream *substream;
  1521. struct dsp_pcm_channel_descriptor * pcm_channel;
  1522. int pcm_channel_id; /* Fron Rear, Center Lfe ... */
  1523. };
  1524. struct snd_cs46xx_region {
  1525. char name[24];
  1526. unsigned long base;
  1527. void __iomem *remap_addr;
  1528. unsigned long size;
  1529. struct resource *resource;
  1530. };
  1531. struct snd_cs46xx {
  1532. int irq;
  1533. unsigned long ba0_addr;
  1534. unsigned long ba1_addr;
  1535. union {
  1536. struct {
  1537. struct snd_cs46xx_region ba0;
  1538. struct snd_cs46xx_region data0;
  1539. struct snd_cs46xx_region data1;
  1540. struct snd_cs46xx_region pmem;
  1541. struct snd_cs46xx_region reg;
  1542. } name;
  1543. struct snd_cs46xx_region idx[5];
  1544. } region;
  1545. unsigned int mode;
  1546. struct {
  1547. struct snd_dma_buffer hw_buf;
  1548. unsigned int ctl;
  1549. unsigned int shift; /* Shift count to trasform frames in bytes */
  1550. struct snd_pcm_indirect pcm_rec;
  1551. struct snd_pcm_substream *substream;
  1552. } capt;
  1553. int nr_ac97_codecs;
  1554. struct snd_ac97_bus *ac97_bus;
  1555. struct snd_ac97 *ac97[MAX_NR_AC97];
  1556. struct pci_dev *pci;
  1557. struct snd_card *card;
  1558. struct snd_pcm *pcm;
  1559. struct snd_rawmidi *rmidi;
  1560. struct snd_rawmidi_substream *midi_input;
  1561. struct snd_rawmidi_substream *midi_output;
  1562. spinlock_t reg_lock;
  1563. unsigned int midcr;
  1564. unsigned int uartm;
  1565. int amplifier;
  1566. void (*amplifier_ctrl)(struct snd_cs46xx *, int);
  1567. void (*active_ctrl)(struct snd_cs46xx *, int);
  1568. void (*mixer_init)(struct snd_cs46xx *);
  1569. int acpi_port;
  1570. struct snd_kcontrol *eapd_switch; /* for amplifier hack */
  1571. int accept_valid; /* accept mmap valid (for OSS) */
  1572. int in_suspend;
  1573. struct gameport *gameport;
  1574. #ifdef CONFIG_SND_CS46XX_DEBUG_GPIO
  1575. int current_gpio;
  1576. #endif
  1577. #ifdef CONFIG_SND_CS46XX_NEW_DSP
  1578. struct mutex spos_mutex;
  1579. struct dsp_spos_instance * dsp_spos_instance;
  1580. struct snd_pcm *pcm_rear;
  1581. struct snd_pcm *pcm_center_lfe;
  1582. struct snd_pcm *pcm_iec958;
  1583. #else /* for compatibility */
  1584. struct snd_cs46xx_pcm *playback_pcm;
  1585. unsigned int play_ctl;
  1586. #endif
  1587. };
  1588. int snd_cs46xx_create(struct snd_card *card,
  1589. struct pci_dev *pci,
  1590. int external_amp, int thinkpad,
  1591. struct snd_cs46xx **rcodec);
  1592. int snd_cs46xx_suspend(struct pci_dev *pci, pm_message_t state);
  1593. int snd_cs46xx_resume(struct pci_dev *pci);
  1594. int snd_cs46xx_pcm(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm);
  1595. int snd_cs46xx_pcm_rear(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm);
  1596. int snd_cs46xx_pcm_iec958(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm);
  1597. int snd_cs46xx_pcm_center_lfe(struct snd_cs46xx *chip, int device, struct snd_pcm **rpcm);
  1598. int snd_cs46xx_mixer(struct snd_cs46xx *chip, int spdif_device);
  1599. int snd_cs46xx_midi(struct snd_cs46xx *chip, int device, struct snd_rawmidi **rmidi);
  1600. int snd_cs46xx_start_dsp(struct snd_cs46xx *chip);
  1601. int snd_cs46xx_gameport(struct snd_cs46xx *chip);
  1602. #endif /* __SOUND_CS46XX_H */