saa7146.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456
  1. #ifndef __SAA7146__
  2. #define __SAA7146__
  3. #include <linux/module.h> /* for module-version */
  4. #include <linux/delay.h> /* for delay-stuff */
  5. #include <linux/slab.h> /* for kmalloc/kfree */
  6. #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
  7. #include <linux/init.h> /* for "__init" */
  8. #include <linux/interrupt.h> /* for IMMEDIATE_BH */
  9. #include <linux/kmod.h> /* for kernel module loader */
  10. #include <linux/i2c.h> /* for i2c subsystem */
  11. #include <asm/io.h> /* for accessing devices */
  12. #include <linux/stringify.h>
  13. #include <linux/mutex.h>
  14. #include <linux/vmalloc.h> /* for vmalloc() */
  15. #include <linux/mm.h> /* for vmalloc_to_page() */
  16. #define SAA7146_VERSION_CODE 0x000500 /* 0.5.0 */
  17. #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
  18. #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
  19. extern unsigned int saa7146_debug;
  20. //#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),KBUILD_MODNAME,__FUNCTION__)
  21. #ifndef DEBUG_VARIABLE
  22. #define DEBUG_VARIABLE saa7146_debug
  23. #endif
  24. #define DEBUG_PROLOG printk("%s: %s(): ",KBUILD_MODNAME,__FUNCTION__)
  25. #define INFO(x) { printk("%s: ",KBUILD_MODNAME); printk x; }
  26. #define ERR(x) { DEBUG_PROLOG; printk x; }
  27. #define DEB_S(x) if (0!=(DEBUG_VARIABLE&0x01)) { DEBUG_PROLOG; printk x; } /* simple debug messages */
  28. #define DEB_D(x) if (0!=(DEBUG_VARIABLE&0x02)) { DEBUG_PROLOG; printk x; } /* more detailed debug messages */
  29. #define DEB_EE(x) if (0!=(DEBUG_VARIABLE&0x04)) { DEBUG_PROLOG; printk x; } /* print enter and exit of functions */
  30. #define DEB_I2C(x) if (0!=(DEBUG_VARIABLE&0x08)) { DEBUG_PROLOG; printk x; } /* i2c debug messages */
  31. #define DEB_VBI(x) if (0!=(DEBUG_VARIABLE&0x10)) { DEBUG_PROLOG; printk x; } /* vbi debug messages */
  32. #define DEB_INT(x) if (0!=(DEBUG_VARIABLE&0x20)) { DEBUG_PROLOG; printk x; } /* interrupt debug messages */
  33. #define DEB_CAP(x) if (0!=(DEBUG_VARIABLE&0x40)) { DEBUG_PROLOG; printk x; } /* capture debug messages */
  34. #define SAA7146_ISR_CLEAR(x,y) \
  35. saa7146_write(x, ISR, (y));
  36. struct saa7146_dev;
  37. struct saa7146_extension;
  38. struct saa7146_vv;
  39. /* saa7146 page table */
  40. struct saa7146_pgtable {
  41. unsigned int size;
  42. u32 *cpu;
  43. dma_addr_t dma;
  44. /* used for offsets for u,v planes for planar capture modes */
  45. unsigned long offset;
  46. /* used for custom pagetables (used for example by budget dvb cards) */
  47. struct scatterlist *slist;
  48. };
  49. struct saa7146_pci_extension_data {
  50. struct saa7146_extension *ext;
  51. void *ext_priv; /* most likely a name string */
  52. };
  53. #define MAKE_EXTENSION_PCI(x_var, x_vendor, x_device) \
  54. { \
  55. .vendor = PCI_VENDOR_ID_PHILIPS, \
  56. .device = PCI_DEVICE_ID_PHILIPS_SAA7146, \
  57. .subvendor = x_vendor, \
  58. .subdevice = x_device, \
  59. .driver_data = (unsigned long)& x_var, \
  60. }
  61. struct saa7146_extension
  62. {
  63. char name[32]; /* name of the device */
  64. #define SAA7146_USE_I2C_IRQ 0x1
  65. #define SAA7146_I2C_SHORT_DELAY 0x2
  66. int flags;
  67. /* pairs of subvendor and subdevice ids for
  68. supported devices, last entry 0xffff, 0xfff */
  69. struct module *module;
  70. struct pci_driver driver;
  71. struct pci_device_id *pci_tbl;
  72. /* extension functions */
  73. int (*probe)(struct saa7146_dev *);
  74. int (*attach)(struct saa7146_dev *, struct saa7146_pci_extension_data *);
  75. int (*detach)(struct saa7146_dev*);
  76. u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
  77. void (*irq_func)(struct saa7146_dev*, u32* irq_mask);
  78. };
  79. struct saa7146_dma
  80. {
  81. dma_addr_t dma_handle;
  82. u32 *cpu_addr;
  83. };
  84. struct saa7146_dev
  85. {
  86. struct module *module;
  87. struct list_head item;
  88. /* different device locks */
  89. spinlock_t slock;
  90. struct mutex lock;
  91. unsigned char __iomem *mem; /* pointer to mapped IO memory */
  92. int revision; /* chip revision; needed for bug-workarounds*/
  93. /* pci-device & irq stuff*/
  94. char name[32];
  95. struct pci_dev *pci;
  96. u32 int_todo;
  97. spinlock_t int_slock;
  98. /* extension handling */
  99. struct saa7146_extension *ext; /* indicates if handled by extension */
  100. void *ext_priv; /* pointer for extension private use (most likely some private data) */
  101. struct saa7146_ext_vv *ext_vv_data;
  102. /* per device video/vbi informations (if available) */
  103. struct saa7146_vv *vv_data;
  104. void (*vv_callback)(struct saa7146_dev *dev, unsigned long status);
  105. /* i2c-stuff */
  106. struct mutex i2c_lock;
  107. u32 i2c_bitrate;
  108. struct saa7146_dma d_i2c; /* pointer to i2c memory */
  109. wait_queue_head_t i2c_wq;
  110. int i2c_op;
  111. /* memories */
  112. struct saa7146_dma d_rps0;
  113. struct saa7146_dma d_rps1;
  114. };
  115. /* from saa7146_i2c.c */
  116. int saa7146_i2c_adapter_prepare(struct saa7146_dev *dev, struct i2c_adapter *i2c_adapter, u32 bitrate);
  117. int saa7146_i2c_transfer(struct saa7146_dev *saa, const struct i2c_msg *msgs, int num, int retries);
  118. /* from saa7146_core.c */
  119. extern struct list_head saa7146_devices;
  120. extern struct mutex saa7146_devices_lock;
  121. int saa7146_register_extension(struct saa7146_extension*);
  122. int saa7146_unregister_extension(struct saa7146_extension*);
  123. struct saa7146_format* format_by_fourcc(struct saa7146_dev *dev, int fourcc);
  124. int saa7146_pgtable_alloc(struct pci_dev *pci, struct saa7146_pgtable *pt);
  125. void saa7146_pgtable_free(struct pci_dev *pci, struct saa7146_pgtable *pt);
  126. int saa7146_pgtable_build_single(struct pci_dev *pci, struct saa7146_pgtable *pt, struct scatterlist *list, int length );
  127. char *saa7146_vmalloc_build_pgtable(struct pci_dev *pci, long length, struct saa7146_pgtable *pt);
  128. void saa7146_setgpio(struct saa7146_dev *dev, int port, u32 data);
  129. int saa7146_wait_for_debi_done(struct saa7146_dev *dev, int nobusyloop);
  130. /* some memory sizes */
  131. #define SAA7146_I2C_MEM ( 1*PAGE_SIZE)
  132. #define SAA7146_RPS_MEM ( 1*PAGE_SIZE)
  133. /* some i2c constants */
  134. #define SAA7146_I2C_TIMEOUT 100 /* i2c-timeout-value in ms */
  135. #define SAA7146_I2C_RETRIES 3 /* how many times shall we retry an i2c-operation? */
  136. #define SAA7146_I2C_DELAY 5 /* time we wait after certain i2c-operations */
  137. /* unsorted defines */
  138. #define ME1 0x0000000800
  139. #define PV1 0x0000000008
  140. /* gpio defines */
  141. #define SAA7146_GPIO_INPUT 0x00
  142. #define SAA7146_GPIO_IRQHI 0x10
  143. #define SAA7146_GPIO_IRQLO 0x20
  144. #define SAA7146_GPIO_IRQHL 0x30
  145. #define SAA7146_GPIO_OUTLO 0x40
  146. #define SAA7146_GPIO_OUTHI 0x50
  147. /* debi defines */
  148. #define DEBINOSWAP 0x000e0000
  149. /* define for the register programming sequencer (rps) */
  150. #define CMD_NOP 0x00000000 /* No operation */
  151. #define CMD_CLR_EVENT 0x00000000 /* Clear event */
  152. #define CMD_SET_EVENT 0x10000000 /* Set signal event */
  153. #define CMD_PAUSE 0x20000000 /* Pause */
  154. #define CMD_CHECK_LATE 0x30000000 /* Check late */
  155. #define CMD_UPLOAD 0x40000000 /* Upload */
  156. #define CMD_STOP 0x50000000 /* Stop */
  157. #define CMD_INTERRUPT 0x60000000 /* Interrupt */
  158. #define CMD_JUMP 0x80000000 /* Jump */
  159. #define CMD_WR_REG 0x90000000 /* Write (load) register */
  160. #define CMD_RD_REG 0xa0000000 /* Read (store) register */
  161. #define CMD_WR_REG_MASK 0xc0000000 /* Write register with mask */
  162. #define CMD_OAN MASK_27
  163. #define CMD_INV MASK_26
  164. #define CMD_SIG4 MASK_25
  165. #define CMD_SIG3 MASK_24
  166. #define CMD_SIG2 MASK_23
  167. #define CMD_SIG1 MASK_22
  168. #define CMD_SIG0 MASK_21
  169. #define CMD_O_FID_B MASK_14
  170. #define CMD_E_FID_B MASK_13
  171. #define CMD_O_FID_A MASK_12
  172. #define CMD_E_FID_A MASK_11
  173. /* some events and command modifiers for rps1 squarewave generator */
  174. #define EVT_HS (1<<15) // Source Line Threshold reached
  175. #define EVT_VBI_B (1<<9) // VSYNC Event
  176. #define RPS_OAN (1<<27) // 1: OR events, 0: AND events
  177. #define RPS_INV (1<<26) // Invert (compound) event
  178. #define GPIO3_MSK 0xFF000000 // GPIO #3 control bits
  179. /* Bit mask constants */
  180. #define MASK_00 0x00000001 /* Mask value for bit 0 */
  181. #define MASK_01 0x00000002 /* Mask value for bit 1 */
  182. #define MASK_02 0x00000004 /* Mask value for bit 2 */
  183. #define MASK_03 0x00000008 /* Mask value for bit 3 */
  184. #define MASK_04 0x00000010 /* Mask value for bit 4 */
  185. #define MASK_05 0x00000020 /* Mask value for bit 5 */
  186. #define MASK_06 0x00000040 /* Mask value for bit 6 */
  187. #define MASK_07 0x00000080 /* Mask value for bit 7 */
  188. #define MASK_08 0x00000100 /* Mask value for bit 8 */
  189. #define MASK_09 0x00000200 /* Mask value for bit 9 */
  190. #define MASK_10 0x00000400 /* Mask value for bit 10 */
  191. #define MASK_11 0x00000800 /* Mask value for bit 11 */
  192. #define MASK_12 0x00001000 /* Mask value for bit 12 */
  193. #define MASK_13 0x00002000 /* Mask value for bit 13 */
  194. #define MASK_14 0x00004000 /* Mask value for bit 14 */
  195. #define MASK_15 0x00008000 /* Mask value for bit 15 */
  196. #define MASK_16 0x00010000 /* Mask value for bit 16 */
  197. #define MASK_17 0x00020000 /* Mask value for bit 17 */
  198. #define MASK_18 0x00040000 /* Mask value for bit 18 */
  199. #define MASK_19 0x00080000 /* Mask value for bit 19 */
  200. #define MASK_20 0x00100000 /* Mask value for bit 20 */
  201. #define MASK_21 0x00200000 /* Mask value for bit 21 */
  202. #define MASK_22 0x00400000 /* Mask value for bit 22 */
  203. #define MASK_23 0x00800000 /* Mask value for bit 23 */
  204. #define MASK_24 0x01000000 /* Mask value for bit 24 */
  205. #define MASK_25 0x02000000 /* Mask value for bit 25 */
  206. #define MASK_26 0x04000000 /* Mask value for bit 26 */
  207. #define MASK_27 0x08000000 /* Mask value for bit 27 */
  208. #define MASK_28 0x10000000 /* Mask value for bit 28 */
  209. #define MASK_29 0x20000000 /* Mask value for bit 29 */
  210. #define MASK_30 0x40000000 /* Mask value for bit 30 */
  211. #define MASK_31 0x80000000 /* Mask value for bit 31 */
  212. #define MASK_B0 0x000000ff /* Mask value for byte 0 */
  213. #define MASK_B1 0x0000ff00 /* Mask value for byte 1 */
  214. #define MASK_B2 0x00ff0000 /* Mask value for byte 2 */
  215. #define MASK_B3 0xff000000 /* Mask value for byte 3 */
  216. #define MASK_W0 0x0000ffff /* Mask value for word 0 */
  217. #define MASK_W1 0xffff0000 /* Mask value for word 1 */
  218. #define MASK_PA 0xfffffffc /* Mask value for physical address */
  219. #define MASK_PR 0xfffffffe /* Mask value for protection register */
  220. #define MASK_ER 0xffffffff /* Mask value for the entire register */
  221. #define MASK_NONE 0x00000000 /* No mask */
  222. /* register aliases */
  223. #define BASE_ODD1 0x00 /* Video DMA 1 registers */
  224. #define BASE_EVEN1 0x04
  225. #define PROT_ADDR1 0x08
  226. #define PITCH1 0x0C
  227. #define BASE_PAGE1 0x10 /* Video DMA 1 base page */
  228. #define NUM_LINE_BYTE1 0x14
  229. #define BASE_ODD2 0x18 /* Video DMA 2 registers */
  230. #define BASE_EVEN2 0x1C
  231. #define PROT_ADDR2 0x20
  232. #define PITCH2 0x24
  233. #define BASE_PAGE2 0x28 /* Video DMA 2 base page */
  234. #define NUM_LINE_BYTE2 0x2C
  235. #define BASE_ODD3 0x30 /* Video DMA 3 registers */
  236. #define BASE_EVEN3 0x34
  237. #define PROT_ADDR3 0x38
  238. #define PITCH3 0x3C
  239. #define BASE_PAGE3 0x40 /* Video DMA 3 base page */
  240. #define NUM_LINE_BYTE3 0x44
  241. #define PCI_BT_V1 0x48 /* Video/FIFO 1 */
  242. #define PCI_BT_V2 0x49 /* Video/FIFO 2 */
  243. #define PCI_BT_V3 0x4A /* Video/FIFO 3 */
  244. #define PCI_BT_DEBI 0x4B /* DEBI */
  245. #define PCI_BT_A 0x4C /* Audio */
  246. #define DD1_INIT 0x50 /* Init setting of DD1 interface */
  247. #define DD1_STREAM_B 0x54 /* DD1 B video data stream handling */
  248. #define DD1_STREAM_A 0x56 /* DD1 A video data stream handling */
  249. #define BRS_CTRL 0x58 /* BRS control register */
  250. #define HPS_CTRL 0x5C /* HPS control register */
  251. #define HPS_V_SCALE 0x60 /* HPS vertical scale */
  252. #define HPS_V_GAIN 0x64 /* HPS vertical ACL and gain */
  253. #define HPS_H_PRESCALE 0x68 /* HPS horizontal prescale */
  254. #define HPS_H_SCALE 0x6C /* HPS horizontal scale */
  255. #define BCS_CTRL 0x70 /* BCS control */
  256. #define CHROMA_KEY_RANGE 0x74
  257. #define CLIP_FORMAT_CTRL 0x78 /* HPS outputs formats & clipping */
  258. #define DEBI_CONFIG 0x7C
  259. #define DEBI_COMMAND 0x80
  260. #define DEBI_PAGE 0x84
  261. #define DEBI_AD 0x88
  262. #define I2C_TRANSFER 0x8C
  263. #define I2C_STATUS 0x90
  264. #define BASE_A1_IN 0x94 /* Audio 1 input DMA */
  265. #define PROT_A1_IN 0x98
  266. #define PAGE_A1_IN 0x9C
  267. #define BASE_A1_OUT 0xA0 /* Audio 1 output DMA */
  268. #define PROT_A1_OUT 0xA4
  269. #define PAGE_A1_OUT 0xA8
  270. #define BASE_A2_IN 0xAC /* Audio 2 input DMA */
  271. #define PROT_A2_IN 0xB0
  272. #define PAGE_A2_IN 0xB4
  273. #define BASE_A2_OUT 0xB8 /* Audio 2 output DMA */
  274. #define PROT_A2_OUT 0xBC
  275. #define PAGE_A2_OUT 0xC0
  276. #define RPS_PAGE0 0xC4 /* RPS task 0 page register */
  277. #define RPS_PAGE1 0xC8 /* RPS task 1 page register */
  278. #define RPS_THRESH0 0xCC /* HBI threshold for task 0 */
  279. #define RPS_THRESH1 0xD0 /* HBI threshold for task 1 */
  280. #define RPS_TOV0 0xD4 /* RPS timeout for task 0 */
  281. #define RPS_TOV1 0xD8 /* RPS timeout for task 1 */
  282. #define IER 0xDC /* Interrupt enable register */
  283. #define GPIO_CTRL 0xE0 /* GPIO 0-3 register */
  284. #define EC1SSR 0xE4 /* Event cnt set 1 source select */
  285. #define EC2SSR 0xE8 /* Event cnt set 2 source select */
  286. #define ECT1R 0xEC /* Event cnt set 1 thresholds */
  287. #define ECT2R 0xF0 /* Event cnt set 2 thresholds */
  288. #define ACON1 0xF4
  289. #define ACON2 0xF8
  290. #define MC1 0xFC /* Main control register 1 */
  291. #define MC2 0x100 /* Main control register 2 */
  292. #define RPS_ADDR0 0x104 /* RPS task 0 address register */
  293. #define RPS_ADDR1 0x108 /* RPS task 1 address register */
  294. #define ISR 0x10C /* Interrupt status register */
  295. #define PSR 0x110 /* Primary status register */
  296. #define SSR 0x114 /* Secondary status register */
  297. #define EC1R 0x118 /* Event counter set 1 register */
  298. #define EC2R 0x11C /* Event counter set 2 register */
  299. #define PCI_VDP1 0x120 /* Video DMA pointer of FIFO 1 */
  300. #define PCI_VDP2 0x124 /* Video DMA pointer of FIFO 2 */
  301. #define PCI_VDP3 0x128 /* Video DMA pointer of FIFO 3 */
  302. #define PCI_ADP1 0x12C /* Audio DMA pointer of audio out 1 */
  303. #define PCI_ADP2 0x130 /* Audio DMA pointer of audio in 1 */
  304. #define PCI_ADP3 0x134 /* Audio DMA pointer of audio out 2 */
  305. #define PCI_ADP4 0x138 /* Audio DMA pointer of audio in 2 */
  306. #define PCI_DMA_DDP 0x13C /* DEBI DMA pointer */
  307. #define LEVEL_REP 0x140,
  308. #define A_TIME_SLOT1 0x180, /* from 180 - 1BC */
  309. #define A_TIME_SLOT2 0x1C0, /* from 1C0 - 1FC */
  310. /* isr masks */
  311. #define SPCI_PPEF 0x80000000 /* PCI parity error */
  312. #define SPCI_PABO 0x40000000 /* PCI access error (target or master abort) */
  313. #define SPCI_PPED 0x20000000 /* PCI parity error on 'real time data' */
  314. #define SPCI_RPS_I1 0x10000000 /* Interrupt issued by RPS1 */
  315. #define SPCI_RPS_I0 0x08000000 /* Interrupt issued by RPS0 */
  316. #define SPCI_RPS_LATE1 0x04000000 /* RPS task 1 is late */
  317. #define SPCI_RPS_LATE0 0x02000000 /* RPS task 0 is late */
  318. #define SPCI_RPS_E1 0x01000000 /* RPS error from task 1 */
  319. #define SPCI_RPS_E0 0x00800000 /* RPS error from task 0 */
  320. #define SPCI_RPS_TO1 0x00400000 /* RPS timeout task 1 */
  321. #define SPCI_RPS_TO0 0x00200000 /* RPS timeout task 0 */
  322. #define SPCI_UPLD 0x00100000 /* RPS in upload */
  323. #define SPCI_DEBI_S 0x00080000 /* DEBI status */
  324. #define SPCI_DEBI_E 0x00040000 /* DEBI error */
  325. #define SPCI_IIC_S 0x00020000 /* I2C status */
  326. #define SPCI_IIC_E 0x00010000 /* I2C error */
  327. #define SPCI_A2_IN 0x00008000 /* Audio 2 input DMA protection / limit */
  328. #define SPCI_A2_OUT 0x00004000 /* Audio 2 output DMA protection / limit */
  329. #define SPCI_A1_IN 0x00002000 /* Audio 1 input DMA protection / limit */
  330. #define SPCI_A1_OUT 0x00001000 /* Audio 1 output DMA protection / limit */
  331. #define SPCI_AFOU 0x00000800 /* Audio FIFO over- / underflow */
  332. #define SPCI_V_PE 0x00000400 /* Video protection address */
  333. #define SPCI_VFOU 0x00000200 /* Video FIFO over- / underflow */
  334. #define SPCI_FIDA 0x00000100 /* Field ID video port A */
  335. #define SPCI_FIDB 0x00000080 /* Field ID video port B */
  336. #define SPCI_PIN3 0x00000040 /* GPIO pin 3 */
  337. #define SPCI_PIN2 0x00000020 /* GPIO pin 2 */
  338. #define SPCI_PIN1 0x00000010 /* GPIO pin 1 */
  339. #define SPCI_PIN0 0x00000008 /* GPIO pin 0 */
  340. #define SPCI_ECS 0x00000004 /* Event counter 1, 2, 4, 5 */
  341. #define SPCI_EC3S 0x00000002 /* Event counter 3 */
  342. #define SPCI_EC0S 0x00000001 /* Event counter 0 */
  343. /* i2c */
  344. #define SAA7146_I2C_ABORT (1<<7)
  345. #define SAA7146_I2C_SPERR (1<<6)
  346. #define SAA7146_I2C_APERR (1<<5)
  347. #define SAA7146_I2C_DTERR (1<<4)
  348. #define SAA7146_I2C_DRERR (1<<3)
  349. #define SAA7146_I2C_AL (1<<2)
  350. #define SAA7146_I2C_ERR (1<<1)
  351. #define SAA7146_I2C_BUSY (1<<0)
  352. #define SAA7146_I2C_START (0x3)
  353. #define SAA7146_I2C_CONT (0x2)
  354. #define SAA7146_I2C_STOP (0x1)
  355. #define SAA7146_I2C_NOP (0x0)
  356. #define SAA7146_I2C_BUS_BIT_RATE_6400 (0x500)
  357. #define SAA7146_I2C_BUS_BIT_RATE_3200 (0x100)
  358. #define SAA7146_I2C_BUS_BIT_RATE_480 (0x400)
  359. #define SAA7146_I2C_BUS_BIT_RATE_320 (0x600)
  360. #define SAA7146_I2C_BUS_BIT_RATE_240 (0x700)
  361. #define SAA7146_I2C_BUS_BIT_RATE_120 (0x000)
  362. #define SAA7146_I2C_BUS_BIT_RATE_80 (0x200)
  363. #define SAA7146_I2C_BUS_BIT_RATE_60 (0x300)
  364. static inline void SAA7146_IER_DISABLE(struct saa7146_dev *x, unsigned y)
  365. {
  366. unsigned long flags;
  367. spin_lock_irqsave(&x->int_slock, flags);
  368. saa7146_write(x, IER, saa7146_read(x, IER) & ~y);
  369. spin_unlock_irqrestore(&x->int_slock, flags);
  370. }
  371. static inline void SAA7146_IER_ENABLE(struct saa7146_dev *x, unsigned y)
  372. {
  373. unsigned long flags;
  374. spin_lock_irqsave(&x->int_slock, flags);
  375. saa7146_write(x, IER, saa7146_read(x, IER) | y);
  376. spin_unlock_irqrestore(&x->int_slock, flags);
  377. }
  378. #endif