net2280.h 23 KB

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  1. /*
  2. * NetChip 2280 high/full speed USB device controller.
  3. * Unlike many such controllers, this one talks PCI.
  4. */
  5. #ifndef __LINUX_USB_NET2280_H
  6. #define __LINUX_USB_NET2280_H
  7. /*
  8. * Copyright (C) 2002 NetChip Technology, Inc. (http://www.netchip.com)
  9. * Copyright (C) 2003 David Brownell
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. */
  25. /*-------------------------------------------------------------------------*/
  26. /* NET2280 MEMORY MAPPED REGISTERS
  27. *
  28. * The register layout came from the chip documentation, and the bit
  29. * number definitions were extracted from chip specification.
  30. *
  31. * Use the shift operator ('<<') to build bit masks, with readl/writel
  32. * to access the registers through PCI.
  33. */
  34. /* main registers, BAR0 + 0x0000 */
  35. struct net2280_regs {
  36. // offset 0x0000
  37. u32 devinit;
  38. #define LOCAL_CLOCK_FREQUENCY 8
  39. #define FORCE_PCI_RESET 7
  40. #define PCI_ID 6
  41. #define PCI_ENABLE 5
  42. #define FIFO_SOFT_RESET 4
  43. #define CFG_SOFT_RESET 3
  44. #define PCI_SOFT_RESET 2
  45. #define USB_SOFT_RESET 1
  46. #define M8051_RESET 0
  47. u32 eectl;
  48. #define EEPROM_ADDRESS_WIDTH 23
  49. #define EEPROM_CHIP_SELECT_ACTIVE 22
  50. #define EEPROM_PRESENT 21
  51. #define EEPROM_VALID 20
  52. #define EEPROM_BUSY 19
  53. #define EEPROM_CHIP_SELECT_ENABLE 18
  54. #define EEPROM_BYTE_READ_START 17
  55. #define EEPROM_BYTE_WRITE_START 16
  56. #define EEPROM_READ_DATA 8
  57. #define EEPROM_WRITE_DATA 0
  58. u32 eeclkfreq;
  59. u32 _unused0;
  60. // offset 0x0010
  61. u32 pciirqenb0; /* interrupt PCI master ... */
  62. #define SETUP_PACKET_INTERRUPT_ENABLE 7
  63. #define ENDPOINT_F_INTERRUPT_ENABLE 6
  64. #define ENDPOINT_E_INTERRUPT_ENABLE 5
  65. #define ENDPOINT_D_INTERRUPT_ENABLE 4
  66. #define ENDPOINT_C_INTERRUPT_ENABLE 3
  67. #define ENDPOINT_B_INTERRUPT_ENABLE 2
  68. #define ENDPOINT_A_INTERRUPT_ENABLE 1
  69. #define ENDPOINT_0_INTERRUPT_ENABLE 0
  70. u32 pciirqenb1;
  71. #define PCI_INTERRUPT_ENABLE 31
  72. #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
  73. #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
  74. #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
  75. #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
  76. #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
  77. #define PCI_TARGET_ABORT_ASSERTED_INTERRUPT_ENABLE 18
  78. #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
  79. #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
  80. #define GPIO_INTERRUPT_ENABLE 13
  81. #define DMA_D_INTERRUPT_ENABLE 12
  82. #define DMA_C_INTERRUPT_ENABLE 11
  83. #define DMA_B_INTERRUPT_ENABLE 10
  84. #define DMA_A_INTERRUPT_ENABLE 9
  85. #define EEPROM_DONE_INTERRUPT_ENABLE 8
  86. #define VBUS_INTERRUPT_ENABLE 7
  87. #define CONTROL_STATUS_INTERRUPT_ENABLE 6
  88. #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
  89. #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
  90. #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
  91. #define RESUME_INTERRUPT_ENABLE 1
  92. #define SOF_INTERRUPT_ENABLE 0
  93. u32 cpu_irqenb0; /* ... or onboard 8051 */
  94. #define SETUP_PACKET_INTERRUPT_ENABLE 7
  95. #define ENDPOINT_F_INTERRUPT_ENABLE 6
  96. #define ENDPOINT_E_INTERRUPT_ENABLE 5
  97. #define ENDPOINT_D_INTERRUPT_ENABLE 4
  98. #define ENDPOINT_C_INTERRUPT_ENABLE 3
  99. #define ENDPOINT_B_INTERRUPT_ENABLE 2
  100. #define ENDPOINT_A_INTERRUPT_ENABLE 1
  101. #define ENDPOINT_0_INTERRUPT_ENABLE 0
  102. u32 cpu_irqenb1;
  103. #define CPU_INTERRUPT_ENABLE 31
  104. #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
  105. #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
  106. #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
  107. #define PCI_INTA_INTERRUPT_ENABLE 24
  108. #define PCI_PME_INTERRUPT_ENABLE 23
  109. #define PCI_SERR_INTERRUPT_ENABLE 22
  110. #define PCI_PERR_INTERRUPT_ENABLE 21
  111. #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
  112. #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
  113. #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
  114. #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
  115. #define GPIO_INTERRUPT_ENABLE 13
  116. #define DMA_D_INTERRUPT_ENABLE 12
  117. #define DMA_C_INTERRUPT_ENABLE 11
  118. #define DMA_B_INTERRUPT_ENABLE 10
  119. #define DMA_A_INTERRUPT_ENABLE 9
  120. #define EEPROM_DONE_INTERRUPT_ENABLE 8
  121. #define VBUS_INTERRUPT_ENABLE 7
  122. #define CONTROL_STATUS_INTERRUPT_ENABLE 6
  123. #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
  124. #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
  125. #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
  126. #define RESUME_INTERRUPT_ENABLE 1
  127. #define SOF_INTERRUPT_ENABLE 0
  128. // offset 0x0020
  129. u32 _unused1;
  130. u32 usbirqenb1;
  131. #define USB_INTERRUPT_ENABLE 31
  132. #define POWER_STATE_CHANGE_INTERRUPT_ENABLE 27
  133. #define PCI_ARBITER_TIMEOUT_INTERRUPT_ENABLE 26
  134. #define PCI_PARITY_ERROR_INTERRUPT_ENABLE 25
  135. #define PCI_INTA_INTERRUPT_ENABLE 24
  136. #define PCI_PME_INTERRUPT_ENABLE 23
  137. #define PCI_SERR_INTERRUPT_ENABLE 22
  138. #define PCI_PERR_INTERRUPT_ENABLE 21
  139. #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT_ENABLE 20
  140. #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT_ENABLE 19
  141. #define PCI_RETRY_ABORT_INTERRUPT_ENABLE 17
  142. #define PCI_MASTER_CYCLE_DONE_INTERRUPT_ENABLE 16
  143. #define GPIO_INTERRUPT_ENABLE 13
  144. #define DMA_D_INTERRUPT_ENABLE 12
  145. #define DMA_C_INTERRUPT_ENABLE 11
  146. #define DMA_B_INTERRUPT_ENABLE 10
  147. #define DMA_A_INTERRUPT_ENABLE 9
  148. #define EEPROM_DONE_INTERRUPT_ENABLE 8
  149. #define VBUS_INTERRUPT_ENABLE 7
  150. #define CONTROL_STATUS_INTERRUPT_ENABLE 6
  151. #define ROOT_PORT_RESET_INTERRUPT_ENABLE 4
  152. #define SUSPEND_REQUEST_INTERRUPT_ENABLE 3
  153. #define SUSPEND_REQUEST_CHANGE_INTERRUPT_ENABLE 2
  154. #define RESUME_INTERRUPT_ENABLE 1
  155. #define SOF_INTERRUPT_ENABLE 0
  156. u32 irqstat0;
  157. #define INTA_ASSERTED 12
  158. #define SETUP_PACKET_INTERRUPT 7
  159. #define ENDPOINT_F_INTERRUPT 6
  160. #define ENDPOINT_E_INTERRUPT 5
  161. #define ENDPOINT_D_INTERRUPT 4
  162. #define ENDPOINT_C_INTERRUPT 3
  163. #define ENDPOINT_B_INTERRUPT 2
  164. #define ENDPOINT_A_INTERRUPT 1
  165. #define ENDPOINT_0_INTERRUPT 0
  166. u32 irqstat1;
  167. #define POWER_STATE_CHANGE_INTERRUPT 27
  168. #define PCI_ARBITER_TIMEOUT_INTERRUPT 26
  169. #define PCI_PARITY_ERROR_INTERRUPT 25
  170. #define PCI_INTA_INTERRUPT 24
  171. #define PCI_PME_INTERRUPT 23
  172. #define PCI_SERR_INTERRUPT 22
  173. #define PCI_PERR_INTERRUPT 21
  174. #define PCI_MASTER_ABORT_RECEIVED_INTERRUPT 20
  175. #define PCI_TARGET_ABORT_RECEIVED_INTERRUPT 19
  176. #define PCI_RETRY_ABORT_INTERRUPT 17
  177. #define PCI_MASTER_CYCLE_DONE_INTERRUPT 16
  178. #define SOF_DOWN_INTERRUPT 14
  179. #define GPIO_INTERRUPT 13
  180. #define DMA_D_INTERRUPT 12
  181. #define DMA_C_INTERRUPT 11
  182. #define DMA_B_INTERRUPT 10
  183. #define DMA_A_INTERRUPT 9
  184. #define EEPROM_DONE_INTERRUPT 8
  185. #define VBUS_INTERRUPT 7
  186. #define CONTROL_STATUS_INTERRUPT 6
  187. #define ROOT_PORT_RESET_INTERRUPT 4
  188. #define SUSPEND_REQUEST_INTERRUPT 3
  189. #define SUSPEND_REQUEST_CHANGE_INTERRUPT 2
  190. #define RESUME_INTERRUPT 1
  191. #define SOF_INTERRUPT 0
  192. // offset 0x0030
  193. u32 idxaddr;
  194. u32 idxdata;
  195. u32 fifoctl;
  196. #define PCI_BASE2_RANGE 16
  197. #define IGNORE_FIFO_AVAILABILITY 3
  198. #define PCI_BASE2_SELECT 2
  199. #define FIFO_CONFIGURATION_SELECT 0
  200. u32 _unused2;
  201. // offset 0x0040
  202. u32 memaddr;
  203. #define START 28
  204. #define DIRECTION 27
  205. #define FIFO_DIAGNOSTIC_SELECT 24
  206. #define MEMORY_ADDRESS 0
  207. u32 memdata0;
  208. u32 memdata1;
  209. u32 _unused3;
  210. // offset 0x0050
  211. u32 gpioctl;
  212. #define GPIO3_LED_SELECT 12
  213. #define GPIO3_INTERRUPT_ENABLE 11
  214. #define GPIO2_INTERRUPT_ENABLE 10
  215. #define GPIO1_INTERRUPT_ENABLE 9
  216. #define GPIO0_INTERRUPT_ENABLE 8
  217. #define GPIO3_OUTPUT_ENABLE 7
  218. #define GPIO2_OUTPUT_ENABLE 6
  219. #define GPIO1_OUTPUT_ENABLE 5
  220. #define GPIO0_OUTPUT_ENABLE 4
  221. #define GPIO3_DATA 3
  222. #define GPIO2_DATA 2
  223. #define GPIO1_DATA 1
  224. #define GPIO0_DATA 0
  225. u32 gpiostat;
  226. #define GPIO3_INTERRUPT 3
  227. #define GPIO2_INTERRUPT 2
  228. #define GPIO1_INTERRUPT 1
  229. #define GPIO0_INTERRUPT 0
  230. } __attribute__ ((packed));
  231. /* usb control, BAR0 + 0x0080 */
  232. struct net2280_usb_regs {
  233. // offset 0x0080
  234. u32 stdrsp;
  235. #define STALL_UNSUPPORTED_REQUESTS 31
  236. #define SET_TEST_MODE 16
  237. #define GET_OTHER_SPEED_CONFIGURATION 15
  238. #define GET_DEVICE_QUALIFIER 14
  239. #define SET_ADDRESS 13
  240. #define ENDPOINT_SET_CLEAR_HALT 12
  241. #define DEVICE_SET_CLEAR_DEVICE_REMOTE_WAKEUP 11
  242. #define GET_STRING_DESCRIPTOR_2 10
  243. #define GET_STRING_DESCRIPTOR_1 9
  244. #define GET_STRING_DESCRIPTOR_0 8
  245. #define GET_SET_INTERFACE 6
  246. #define GET_SET_CONFIGURATION 5
  247. #define GET_CONFIGURATION_DESCRIPTOR 4
  248. #define GET_DEVICE_DESCRIPTOR 3
  249. #define GET_ENDPOINT_STATUS 2
  250. #define GET_INTERFACE_STATUS 1
  251. #define GET_DEVICE_STATUS 0
  252. u32 prodvendid;
  253. #define PRODUCT_ID 16
  254. #define VENDOR_ID 0
  255. u32 relnum;
  256. u32 usbctl;
  257. #define SERIAL_NUMBER_INDEX 16
  258. #define PRODUCT_ID_STRING_ENABLE 13
  259. #define VENDOR_ID_STRING_ENABLE 12
  260. #define USB_ROOT_PORT_WAKEUP_ENABLE 11
  261. #define VBUS_PIN 10
  262. #define TIMED_DISCONNECT 9
  263. #define SUSPEND_IMMEDIATELY 7
  264. #define SELF_POWERED_USB_DEVICE 6
  265. #define REMOTE_WAKEUP_SUPPORT 5
  266. #define PME_POLARITY 4
  267. #define USB_DETECT_ENABLE 3
  268. #define PME_WAKEUP_ENABLE 2
  269. #define DEVICE_REMOTE_WAKEUP_ENABLE 1
  270. #define SELF_POWERED_STATUS 0
  271. // offset 0x0090
  272. u32 usbstat;
  273. #define HIGH_SPEED 7
  274. #define FULL_SPEED 6
  275. #define GENERATE_RESUME 5
  276. #define GENERATE_DEVICE_REMOTE_WAKEUP 4
  277. u32 xcvrdiag;
  278. #define FORCE_HIGH_SPEED_MODE 31
  279. #define FORCE_FULL_SPEED_MODE 30
  280. #define USB_TEST_MODE 24
  281. #define LINE_STATE 16
  282. #define TRANSCEIVER_OPERATION_MODE 2
  283. #define TRANSCEIVER_SELECT 1
  284. #define TERMINATION_SELECT 0
  285. u32 setup0123;
  286. u32 setup4567;
  287. // offset 0x0090
  288. u32 _unused0;
  289. u32 ouraddr;
  290. #define FORCE_IMMEDIATE 7
  291. #define OUR_USB_ADDRESS 0
  292. u32 ourconfig;
  293. } __attribute__ ((packed));
  294. /* pci control, BAR0 + 0x0100 */
  295. struct net2280_pci_regs {
  296. // offset 0x0100
  297. u32 pcimstctl;
  298. #define PCI_ARBITER_PARK_SELECT 13
  299. #define PCI_MULTI LEVEL_ARBITER 12
  300. #define PCI_RETRY_ABORT_ENABLE 11
  301. #define DMA_MEMORY_WRITE_AND_INVALIDATE_ENABLE 10
  302. #define DMA_READ_MULTIPLE_ENABLE 9
  303. #define DMA_READ_LINE_ENABLE 8
  304. #define PCI_MASTER_COMMAND_SELECT 6
  305. #define MEM_READ_OR_WRITE 0
  306. #define IO_READ_OR_WRITE 1
  307. #define CFG_READ_OR_WRITE 2
  308. #define PCI_MASTER_START 5
  309. #define PCI_MASTER_READ_WRITE 4
  310. #define PCI_MASTER_WRITE 0
  311. #define PCI_MASTER_READ 1
  312. #define PCI_MASTER_BYTE_WRITE_ENABLES 0
  313. u32 pcimstaddr;
  314. u32 pcimstdata;
  315. u32 pcimststat;
  316. #define PCI_ARBITER_CLEAR 2
  317. #define PCI_EXTERNAL_ARBITER 1
  318. #define PCI_HOST_MODE 0
  319. } __attribute__ ((packed));
  320. /* dma control, BAR0 + 0x0180 ... array of four structs like this,
  321. * for channels 0..3. see also struct net2280_dma: descriptor
  322. * that can be loaded into some of these registers.
  323. */
  324. struct net2280_dma_regs { /* [11.7] */
  325. // offset 0x0180, 0x01a0, 0x01c0, 0x01e0,
  326. u32 dmactl;
  327. #define DMA_SCATTER_GATHER_DONE_INTERRUPT_ENABLE 25
  328. #define DMA_CLEAR_COUNT_ENABLE 21
  329. #define DESCRIPTOR_POLLING_RATE 19
  330. #define POLL_CONTINUOUS 0
  331. #define POLL_1_USEC 1
  332. #define POLL_100_USEC 2
  333. #define POLL_1_MSEC 3
  334. #define DMA_VALID_BIT_POLLING_ENABLE 18
  335. #define DMA_VALID_BIT_ENABLE 17
  336. #define DMA_SCATTER_GATHER_ENABLE 16
  337. #define DMA_OUT_AUTO_START_ENABLE 4
  338. #define DMA_PREEMPT_ENABLE 3
  339. #define DMA_FIFO_VALIDATE 2
  340. #define DMA_ENABLE 1
  341. #define DMA_ADDRESS_HOLD 0
  342. u32 dmastat;
  343. #define DMA_ABORT_DONE_INTERRUPT 27
  344. #define DMA_SCATTER_GATHER_DONE_INTERRUPT 25
  345. #define DMA_TRANSACTION_DONE_INTERRUPT 24
  346. #define DMA_ABORT 1
  347. #define DMA_START 0
  348. u32 _unused0 [2];
  349. // offset 0x0190, 0x01b0, 0x01d0, 0x01f0,
  350. u32 dmacount;
  351. #define VALID_BIT 31
  352. #define DMA_DIRECTION 30
  353. #define DMA_DONE_INTERRUPT_ENABLE 29
  354. #define END_OF_CHAIN 28
  355. #define DMA_BYTE_COUNT_MASK ((1<<24)-1)
  356. #define DMA_BYTE_COUNT 0
  357. u32 dmaaddr;
  358. u32 dmadesc;
  359. u32 _unused1;
  360. } __attribute__ ((packed));
  361. /* dedicated endpoint registers, BAR0 + 0x0200 */
  362. struct net2280_dep_regs { /* [11.8] */
  363. // offset 0x0200, 0x0210, 0x220, 0x230, 0x240
  364. u32 dep_cfg;
  365. // offset 0x0204, 0x0214, 0x224, 0x234, 0x244
  366. u32 dep_rsp;
  367. u32 _unused [2];
  368. } __attribute__ ((packed));
  369. /* configurable endpoint registers, BAR0 + 0x0300 ... array of seven structs
  370. * like this, for ep0 then the configurable endpoints A..F
  371. * ep0 reserved for control; E and F have only 64 bytes of fifo
  372. */
  373. struct net2280_ep_regs { /* [11.9] */
  374. // offset 0x0300, 0x0320, 0x0340, 0x0360, 0x0380, 0x03a0, 0x03c0
  375. u32 ep_cfg;
  376. #define ENDPOINT_BYTE_COUNT 16
  377. #define ENDPOINT_ENABLE 10
  378. #define ENDPOINT_TYPE 8
  379. #define ENDPOINT_DIRECTION 7
  380. #define ENDPOINT_NUMBER 0
  381. u32 ep_rsp;
  382. #define SET_NAK_OUT_PACKETS 15
  383. #define SET_EP_HIDE_STATUS_PHASE 14
  384. #define SET_EP_FORCE_CRC_ERROR 13
  385. #define SET_INTERRUPT_MODE 12
  386. #define SET_CONTROL_STATUS_PHASE_HANDSHAKE 11
  387. #define SET_NAK_OUT_PACKETS_MODE 10
  388. #define SET_ENDPOINT_TOGGLE 9
  389. #define SET_ENDPOINT_HALT 8
  390. #define CLEAR_NAK_OUT_PACKETS 7
  391. #define CLEAR_EP_HIDE_STATUS_PHASE 6
  392. #define CLEAR_EP_FORCE_CRC_ERROR 5
  393. #define CLEAR_INTERRUPT_MODE 4
  394. #define CLEAR_CONTROL_STATUS_PHASE_HANDSHAKE 3
  395. #define CLEAR_NAK_OUT_PACKETS_MODE 2
  396. #define CLEAR_ENDPOINT_TOGGLE 1
  397. #define CLEAR_ENDPOINT_HALT 0
  398. u32 ep_irqenb;
  399. #define SHORT_PACKET_OUT_DONE_INTERRUPT_ENABLE 6
  400. #define SHORT_PACKET_TRANSFERRED_INTERRUPT_ENABLE 5
  401. #define DATA_PACKET_RECEIVED_INTERRUPT_ENABLE 3
  402. #define DATA_PACKET_TRANSMITTED_INTERRUPT_ENABLE 2
  403. #define DATA_OUT_PING_TOKEN_INTERRUPT_ENABLE 1
  404. #define DATA_IN_TOKEN_INTERRUPT_ENABLE 0
  405. u32 ep_stat;
  406. #define FIFO_VALID_COUNT 24
  407. #define HIGH_BANDWIDTH_OUT_TRANSACTION_PID 22
  408. #define TIMEOUT 21
  409. #define USB_STALL_SENT 20
  410. #define USB_IN_NAK_SENT 19
  411. #define USB_IN_ACK_RCVD 18
  412. #define USB_OUT_PING_NAK_SENT 17
  413. #define USB_OUT_ACK_SENT 16
  414. #define FIFO_OVERFLOW 13
  415. #define FIFO_UNDERFLOW 12
  416. #define FIFO_FULL 11
  417. #define FIFO_EMPTY 10
  418. #define FIFO_FLUSH 9
  419. #define SHORT_PACKET_OUT_DONE_INTERRUPT 6
  420. #define SHORT_PACKET_TRANSFERRED_INTERRUPT 5
  421. #define NAK_OUT_PACKETS 4
  422. #define DATA_PACKET_RECEIVED_INTERRUPT 3
  423. #define DATA_PACKET_TRANSMITTED_INTERRUPT 2
  424. #define DATA_OUT_PING_TOKEN_INTERRUPT 1
  425. #define DATA_IN_TOKEN_INTERRUPT 0
  426. // offset 0x0310, 0x0330, 0x0350, 0x0370, 0x0390, 0x03b0, 0x03d0
  427. u32 ep_avail;
  428. u32 ep_data;
  429. u32 _unused0 [2];
  430. } __attribute__ ((packed));
  431. #endif /* __LINUX_USB_NET2280_H */