umem.h 3.8 KB

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  1. /*
  2. * This file contains defines for the
  3. * Micro Memory MM5415
  4. * family PCI Memory Module with Battery Backup.
  5. *
  6. * Copyright Micro Memory INC 2001. All rights reserved.
  7. * Release under the terms of the GNU GENERAL PUBLIC LICENSE version 2.
  8. * See the file COPYING.
  9. */
  10. #ifndef _DRIVERS_BLOCK_MM_H
  11. #define _DRIVERS_BLOCK_MM_H
  12. #define IRQ_TIMEOUT (1 * HZ)
  13. /* CSR register definition */
  14. #define MEMCTRLSTATUS_MAGIC 0x00
  15. #define MM_MAGIC_VALUE (unsigned char)0x59
  16. #define MEMCTRLSTATUS_BATTERY 0x04
  17. #define BATTERY_1_DISABLED 0x01
  18. #define BATTERY_1_FAILURE 0x02
  19. #define BATTERY_2_DISABLED 0x04
  20. #define BATTERY_2_FAILURE 0x08
  21. #define MEMCTRLSTATUS_MEMORY 0x07
  22. #define MEM_128_MB 0xfe
  23. #define MEM_256_MB 0xfc
  24. #define MEM_512_MB 0xf8
  25. #define MEM_1_GB 0xf0
  26. #define MEM_2_GB 0xe0
  27. #define MEMCTRLCMD_LEDCTRL 0x08
  28. #define LED_REMOVE 2
  29. #define LED_FAULT 4
  30. #define LED_POWER 6
  31. #define LED_FLIP 255
  32. #define LED_OFF 0x00
  33. #define LED_ON 0x01
  34. #define LED_FLASH_3_5 0x02
  35. #define LED_FLASH_7_0 0x03
  36. #define LED_POWER_ON 0x00
  37. #define LED_POWER_OFF 0x01
  38. #define USER_BIT1 0x01
  39. #define USER_BIT2 0x02
  40. #define MEMORY_INITIALIZED USER_BIT1
  41. #define MEMCTRLCMD_ERRCTRL 0x0C
  42. #define EDC_NONE_DEFAULT 0x00
  43. #define EDC_NONE 0x01
  44. #define EDC_STORE_READ 0x02
  45. #define EDC_STORE_CORRECT 0x03
  46. #define MEMCTRLCMD_ERRCNT 0x0D
  47. #define MEMCTRLCMD_ERRSTATUS 0x0E
  48. #define ERROR_DATA_LOG 0x20
  49. #define ERROR_ADDR_LOG 0x28
  50. #define ERROR_COUNT 0x3D
  51. #define ERROR_SYNDROME 0x3E
  52. #define ERROR_CHECK 0x3F
  53. #define DMA_PCI_ADDR 0x40
  54. #define DMA_LOCAL_ADDR 0x48
  55. #define DMA_TRANSFER_SIZE 0x50
  56. #define DMA_DESCRIPTOR_ADDR 0x58
  57. #define DMA_SEMAPHORE_ADDR 0x60
  58. #define DMA_STATUS_CTRL 0x68
  59. #define DMASCR_GO 0x00001
  60. #define DMASCR_TRANSFER_READ 0x00002
  61. #define DMASCR_CHAIN_EN 0x00004
  62. #define DMASCR_SEM_EN 0x00010
  63. #define DMASCR_DMA_COMP_EN 0x00020
  64. #define DMASCR_CHAIN_COMP_EN 0x00040
  65. #define DMASCR_ERR_INT_EN 0x00080
  66. #define DMASCR_PARITY_INT_EN 0x00100
  67. #define DMASCR_ANY_ERR 0x00800
  68. #define DMASCR_MBE_ERR 0x01000
  69. #define DMASCR_PARITY_ERR_REP 0x02000
  70. #define DMASCR_PARITY_ERR_DET 0x04000
  71. #define DMASCR_SYSTEM_ERR_SIG 0x08000
  72. #define DMASCR_TARGET_ABT 0x10000
  73. #define DMASCR_MASTER_ABT 0x20000
  74. #define DMASCR_DMA_COMPLETE 0x40000
  75. #define DMASCR_CHAIN_COMPLETE 0x80000
  76. /*
  77. 3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE
  78. READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA
  79. TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE
  80. TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS
  81. (31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6,
  82. AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING
  83. DMA READ OPERATIONS.
  84. */
  85. #define DMASCR_READ 0x60000000
  86. #define DMASCR_READLINE 0xE0000000
  87. #define DMASCR_READMULTI 0xC0000000
  88. #define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR)
  89. #define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR)
  90. #define WINDOWMAP_WINNUM 0x7B
  91. #define DMA_READ_FROM_HOST 0
  92. #define DMA_WRITE_TO_HOST 1
  93. struct mm_dma_desc {
  94. __le64 pci_addr;
  95. __le64 local_addr;
  96. __le32 transfer_size;
  97. u32 zero1;
  98. __le64 next_desc_addr;
  99. __le64 sem_addr;
  100. __le32 control_bits;
  101. u32 zero2;
  102. dma_addr_t data_dma_handle;
  103. /* Copy of the bits */
  104. __le64 sem_control_bits;
  105. } __attribute__((aligned(8)));
  106. #define PCI_VENDOR_ID_MICRO_MEMORY 0x1332
  107. #define PCI_DEVICE_ID_MICRO_MEMORY_5415CN 0x5415
  108. #define PCI_DEVICE_ID_MICRO_MEMORY_5425CN 0x5425
  109. #define PCI_DEVICE_ID_MICRO_MEMORY_6155 0x6155
  110. /* bits for card->flags */
  111. #define UM_FLAG_DMA_IN_REGS 1
  112. #define UM_FLAG_NO_BYTE_STATUS 2
  113. #define UM_FLAG_NO_BATTREG 4
  114. #define UM_FLAG_NO_BATT 8
  115. #endif