sc26198.h 13 KB

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  1. /*****************************************************************************/
  2. /*
  3. * sc26198.h -- SC26198 UART hardware info.
  4. *
  5. * Copyright (C) 1995-1998 Stallion Technologies
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. /*****************************************************************************/
  22. #ifndef _SC26198_H
  23. #define _SC26198_H
  24. /*****************************************************************************/
  25. /*
  26. * Define the number of async ports per sc26198 uart device.
  27. */
  28. #define SC26198_PORTS 8
  29. /*
  30. * Baud rate timing clocks. All derived from a master 14.7456 MHz clock.
  31. */
  32. #define SC26198_MASTERCLOCK 14745600L
  33. #define SC26198_DCLK (SC26198_MASTERCLOCK)
  34. #define SC26198_CCLK (SC26198_MASTERCLOCK / 2)
  35. #define SC26198_BCLK (SC26198_MASTERCLOCK / 4)
  36. /*
  37. * Define internal FIFO sizes for the 26198 ports.
  38. */
  39. #define SC26198_TXFIFOSIZE 16
  40. #define SC26198_RXFIFOSIZE 16
  41. /*****************************************************************************/
  42. /*
  43. * Global register definitions. These registers are global to each 26198
  44. * device, not specific ports on it.
  45. */
  46. #define TSTR 0x0d
  47. #define GCCR 0x0f
  48. #define ICR 0x1b
  49. #define WDTRCR 0x1d
  50. #define IVR 0x1f
  51. #define BRGTRUA 0x84
  52. #define GPOSR 0x87
  53. #define GPOC 0x8b
  54. #define UCIR 0x8c
  55. #define CIR 0x8c
  56. #define BRGTRUB 0x8d
  57. #define GRXFIFO 0x8e
  58. #define GTXFIFO 0x8e
  59. #define GCCR2 0x8f
  60. #define BRGTRLA 0x94
  61. #define GPOR 0x97
  62. #define GPOD 0x9b
  63. #define BRGTCR 0x9c
  64. #define GICR 0x9c
  65. #define BRGTRLB 0x9d
  66. #define GIBCR 0x9d
  67. #define GITR 0x9f
  68. /*
  69. * Per port channel registers. These are the register offsets within
  70. * the port address space, so need to have the port address (0 to 7)
  71. * inserted in bit positions 4:6.
  72. */
  73. #define MR0 0x00
  74. #define MR1 0x01
  75. #define IOPCR 0x02
  76. #define BCRBRK 0x03
  77. #define BCRCOS 0x04
  78. #define BCRX 0x06
  79. #define BCRA 0x07
  80. #define XONCR 0x08
  81. #define XOFFCR 0x09
  82. #define ARCR 0x0a
  83. #define RXCSR 0x0c
  84. #define TXCSR 0x0e
  85. #define MR2 0x80
  86. #define SR 0x81
  87. #define SCCR 0x81
  88. #define ISR 0x82
  89. #define IMR 0x82
  90. #define TXFIFO 0x83
  91. #define RXFIFO 0x83
  92. #define IPR 0x84
  93. #define IOPIOR 0x85
  94. #define XISR 0x86
  95. /*
  96. * For any given port calculate the address to use to access a specified
  97. * register. This is only used for unusual access, mostly this is done
  98. * through the assembler access routines.
  99. */
  100. #define SC26198_PORTREG(port,reg) ((((port) & 0x07) << 4) | (reg))
  101. /*****************************************************************************/
  102. /*
  103. * Global configuration control register bit definitions.
  104. */
  105. #define GCCR_NOACK 0x00
  106. #define GCCR_IVRACK 0x02
  107. #define GCCR_IVRCHANACK 0x04
  108. #define GCCR_IVRTYPCHANACK 0x06
  109. #define GCCR_ASYNCCYCLE 0x00
  110. #define GCCR_SYNCCYCLE 0x40
  111. /*****************************************************************************/
  112. /*
  113. * Mode register 0 bit definitions.
  114. */
  115. #define MR0_ADDRNONE 0x00
  116. #define MR0_AUTOWAKE 0x01
  117. #define MR0_AUTODOZE 0x02
  118. #define MR0_AUTOWAKEDOZE 0x03
  119. #define MR0_SWFNONE 0x00
  120. #define MR0_SWFTX 0x04
  121. #define MR0_SWFRX 0x08
  122. #define MR0_SWFRXTX 0x0c
  123. #define MR0_TXMASK 0x30
  124. #define MR0_TXEMPTY 0x00
  125. #define MR0_TXHIGH 0x10
  126. #define MR0_TXHALF 0x20
  127. #define MR0_TXRDY 0x00
  128. #define MR0_ADDRNT 0x00
  129. #define MR0_ADDRT 0x40
  130. #define MR0_SWFNT 0x00
  131. #define MR0_SWFT 0x80
  132. /*
  133. * Mode register 1 bit definitions.
  134. */
  135. #define MR1_CS5 0x00
  136. #define MR1_CS6 0x01
  137. #define MR1_CS7 0x02
  138. #define MR1_CS8 0x03
  139. #define MR1_PAREVEN 0x00
  140. #define MR1_PARODD 0x04
  141. #define MR1_PARENB 0x00
  142. #define MR1_PARFORCE 0x08
  143. #define MR1_PARNONE 0x10
  144. #define MR1_PARSPECIAL 0x18
  145. #define MR1_ERRCHAR 0x00
  146. #define MR1_ERRBLOCK 0x20
  147. #define MR1_ISRUNMASKED 0x00
  148. #define MR1_ISRMASKED 0x40
  149. #define MR1_AUTORTS 0x80
  150. /*
  151. * Mode register 2 bit definitions.
  152. */
  153. #define MR2_STOP1 0x00
  154. #define MR2_STOP15 0x01
  155. #define MR2_STOP2 0x02
  156. #define MR2_STOP916 0x03
  157. #define MR2_RXFIFORDY 0x00
  158. #define MR2_RXFIFOHALF 0x04
  159. #define MR2_RXFIFOHIGH 0x08
  160. #define MR2_RXFIFOFULL 0x0c
  161. #define MR2_AUTOCTS 0x10
  162. #define MR2_TXRTS 0x20
  163. #define MR2_MODENORM 0x00
  164. #define MR2_MODEAUTOECHO 0x40
  165. #define MR2_MODELOOP 0x80
  166. #define MR2_MODEREMECHO 0xc0
  167. /*****************************************************************************/
  168. /*
  169. * Baud Rate Generator (BRG) selector values.
  170. */
  171. #define BRG_50 0x00
  172. #define BRG_75 0x01
  173. #define BRG_150 0x02
  174. #define BRG_200 0x03
  175. #define BRG_300 0x04
  176. #define BRG_450 0x05
  177. #define BRG_600 0x06
  178. #define BRG_900 0x07
  179. #define BRG_1200 0x08
  180. #define BRG_1800 0x09
  181. #define BRG_2400 0x0a
  182. #define BRG_3600 0x0b
  183. #define BRG_4800 0x0c
  184. #define BRG_7200 0x0d
  185. #define BRG_9600 0x0e
  186. #define BRG_14400 0x0f
  187. #define BRG_19200 0x10
  188. #define BRG_28200 0x11
  189. #define BRG_38400 0x12
  190. #define BRG_57600 0x13
  191. #define BRG_115200 0x14
  192. #define BRG_230400 0x15
  193. #define BRG_GIN0 0x16
  194. #define BRG_GIN1 0x17
  195. #define BRG_CT0 0x18
  196. #define BRG_CT1 0x19
  197. #define BRG_RX2TX316 0x1b
  198. #define BRG_RX2TX31 0x1c
  199. #define SC26198_MAXBAUD 921600
  200. /*****************************************************************************/
  201. /*
  202. * Command register command definitions.
  203. */
  204. #define CR_NULL 0x04
  205. #define CR_ADDRNORMAL 0x0c
  206. #define CR_RXRESET 0x14
  207. #define CR_TXRESET 0x1c
  208. #define CR_CLEARRXERR 0x24
  209. #define CR_BREAKRESET 0x2c
  210. #define CR_TXSTARTBREAK 0x34
  211. #define CR_TXSTOPBREAK 0x3c
  212. #define CR_RTSON 0x44
  213. #define CR_RTSOFF 0x4c
  214. #define CR_ADDRINIT 0x5c
  215. #define CR_RXERRBLOCK 0x6c
  216. #define CR_TXSENDXON 0x84
  217. #define CR_TXSENDXOFF 0x8c
  218. #define CR_GANGXONSET 0x94
  219. #define CR_GANGXOFFSET 0x9c
  220. #define CR_GANGXONINIT 0xa4
  221. #define CR_GANGXOFFINIT 0xac
  222. #define CR_HOSTXON 0xb4
  223. #define CR_HOSTXOFF 0xbc
  224. #define CR_CANCELXOFF 0xc4
  225. #define CR_ADDRRESET 0xdc
  226. #define CR_RESETALLPORTS 0xf4
  227. #define CR_RESETALL 0xfc
  228. #define CR_RXENABLE 0x01
  229. #define CR_TXENABLE 0x02
  230. /*****************************************************************************/
  231. /*
  232. * Channel status register.
  233. */
  234. #define SR_RXRDY 0x01
  235. #define SR_RXFULL 0x02
  236. #define SR_TXRDY 0x04
  237. #define SR_TXEMPTY 0x08
  238. #define SR_RXOVERRUN 0x10
  239. #define SR_RXPARITY 0x20
  240. #define SR_RXFRAMING 0x40
  241. #define SR_RXBREAK 0x80
  242. #define SR_RXERRS (SR_RXPARITY | SR_RXFRAMING | SR_RXOVERRUN)
  243. /*****************************************************************************/
  244. /*
  245. * Interrupt status register and interrupt mask register bit definitions.
  246. */
  247. #define IR_TXRDY 0x01
  248. #define IR_RXRDY 0x02
  249. #define IR_RXBREAK 0x04
  250. #define IR_XONXOFF 0x10
  251. #define IR_ADDRRECOG 0x20
  252. #define IR_RXWATCHDOG 0x40
  253. #define IR_IOPORT 0x80
  254. /*****************************************************************************/
  255. /*
  256. * Interrupt vector register field definitions.
  257. */
  258. #define IVR_CHANMASK 0x07
  259. #define IVR_TYPEMASK 0x18
  260. #define IVR_CONSTMASK 0xc0
  261. #define IVR_RXDATA 0x10
  262. #define IVR_RXBADDATA 0x18
  263. #define IVR_TXDATA 0x08
  264. #define IVR_OTHER 0x00
  265. /*****************************************************************************/
  266. /*
  267. * BRG timer control register bit definitions.
  268. */
  269. #define BRGCTCR_DISABCLK0 0x00
  270. #define BRGCTCR_ENABCLK0 0x08
  271. #define BRGCTCR_DISABCLK1 0x00
  272. #define BRGCTCR_ENABCLK1 0x80
  273. #define BRGCTCR_0SCLK16 0x00
  274. #define BRGCTCR_0SCLK32 0x01
  275. #define BRGCTCR_0SCLK64 0x02
  276. #define BRGCTCR_0SCLK128 0x03
  277. #define BRGCTCR_0X1 0x04
  278. #define BRGCTCR_0X12 0x05
  279. #define BRGCTCR_0IO1A 0x06
  280. #define BRGCTCR_0GIN0 0x07
  281. #define BRGCTCR_1SCLK16 0x00
  282. #define BRGCTCR_1SCLK32 0x10
  283. #define BRGCTCR_1SCLK64 0x20
  284. #define BRGCTCR_1SCLK128 0x30
  285. #define BRGCTCR_1X1 0x40
  286. #define BRGCTCR_1X12 0x50
  287. #define BRGCTCR_1IO1B 0x60
  288. #define BRGCTCR_1GIN1 0x70
  289. /*****************************************************************************/
  290. /*
  291. * Watch dog timer enable register.
  292. */
  293. #define WDTRCR_ENABALL 0xff
  294. /*****************************************************************************/
  295. /*
  296. * XON/XOFF interrupt status register.
  297. */
  298. #define XISR_TXCHARMASK 0x03
  299. #define XISR_TXCHARNORMAL 0x00
  300. #define XISR_TXWAIT 0x01
  301. #define XISR_TXXOFFPEND 0x02
  302. #define XISR_TXXONPEND 0x03
  303. #define XISR_TXFLOWMASK 0x0c
  304. #define XISR_TXNORMAL 0x00
  305. #define XISR_TXSTOPPEND 0x04
  306. #define XISR_TXSTARTED 0x08
  307. #define XISR_TXSTOPPED 0x0c
  308. #define XISR_RXFLOWMASK 0x30
  309. #define XISR_RXFLOWNONE 0x00
  310. #define XISR_RXXONSENT 0x10
  311. #define XISR_RXXOFFSENT 0x20
  312. #define XISR_RXXONGOT 0x40
  313. #define XISR_RXXOFFGOT 0x80
  314. /*****************************************************************************/
  315. /*
  316. * Current interrupt register.
  317. */
  318. #define CIR_TYPEMASK 0xc0
  319. #define CIR_TYPEOTHER 0x00
  320. #define CIR_TYPETX 0x40
  321. #define CIR_TYPERXGOOD 0x80
  322. #define CIR_TYPERXBAD 0xc0
  323. #define CIR_RXDATA 0x80
  324. #define CIR_RXBADDATA 0x40
  325. #define CIR_TXDATA 0x40
  326. #define CIR_CHANMASK 0x07
  327. #define CIR_CNTMASK 0x38
  328. #define CIR_SUBTYPEMASK 0x38
  329. #define CIR_SUBNONE 0x00
  330. #define CIR_SUBCOS 0x08
  331. #define CIR_SUBADDR 0x10
  332. #define CIR_SUBXONXOFF 0x18
  333. #define CIR_SUBBREAK 0x28
  334. /*****************************************************************************/
  335. /*
  336. * Global interrupting channel register.
  337. */
  338. #define GICR_CHANMASK 0x07
  339. /*****************************************************************************/
  340. /*
  341. * Global interrupting byte count register.
  342. */
  343. #define GICR_COUNTMASK 0x0f
  344. /*****************************************************************************/
  345. /*
  346. * Global interrupting type register.
  347. */
  348. #define GITR_RXMASK 0xc0
  349. #define GITR_RXNONE 0x00
  350. #define GITR_RXBADDATA 0x80
  351. #define GITR_RXGOODDATA 0xc0
  352. #define GITR_TXDATA 0x20
  353. #define GITR_SUBTYPEMASK 0x07
  354. #define GITR_SUBNONE 0x00
  355. #define GITR_SUBCOS 0x01
  356. #define GITR_SUBADDR 0x02
  357. #define GITR_SUBXONXOFF 0x03
  358. #define GITR_SUBBREAK 0x05
  359. /*****************************************************************************/
  360. /*
  361. * Input port change register.
  362. */
  363. #define IPR_CTS 0x01
  364. #define IPR_DTR 0x02
  365. #define IPR_RTS 0x04
  366. #define IPR_DCD 0x08
  367. #define IPR_CTSCHANGE 0x10
  368. #define IPR_DTRCHANGE 0x20
  369. #define IPR_RTSCHANGE 0x40
  370. #define IPR_DCDCHANGE 0x80
  371. #define IPR_CHANGEMASK 0xf0
  372. /*****************************************************************************/
  373. /*
  374. * IO port interrupt and output register.
  375. */
  376. #define IOPR_CTS 0x01
  377. #define IOPR_DTR 0x02
  378. #define IOPR_RTS 0x04
  379. #define IOPR_DCD 0x08
  380. #define IOPR_CTSCOS 0x10
  381. #define IOPR_DTRCOS 0x20
  382. #define IOPR_RTSCOS 0x40
  383. #define IOPR_DCDCOS 0x80
  384. /*****************************************************************************/
  385. /*
  386. * IO port configuration register.
  387. */
  388. #define IOPCR_SETCTS 0x00
  389. #define IOPCR_SETDTR 0x04
  390. #define IOPCR_SETRTS 0x10
  391. #define IOPCR_SETDCD 0x00
  392. #define IOPCR_SETSIGS (IOPCR_SETRTS | IOPCR_SETRTS | IOPCR_SETDTR | IOPCR_SETDCD)
  393. /*****************************************************************************/
  394. /*
  395. * General purpose output select register.
  396. */
  397. #define GPORS_TXC1XA 0x08
  398. #define GPORS_TXC16XA 0x09
  399. #define GPORS_RXC16XA 0x0a
  400. #define GPORS_TXC16XB 0x0b
  401. #define GPORS_GPOR3 0x0c
  402. #define GPORS_GPOR2 0x0d
  403. #define GPORS_GPOR1 0x0e
  404. #define GPORS_GPOR0 0x0f
  405. /*****************************************************************************/
  406. /*
  407. * General purpose output register.
  408. */
  409. #define GPOR_0 0x01
  410. #define GPOR_1 0x02
  411. #define GPOR_2 0x04
  412. #define GPOR_3 0x08
  413. /*****************************************************************************/
  414. /*
  415. * General purpose output clock register.
  416. */
  417. #define GPORC_0NONE 0x00
  418. #define GPORC_0GIN0 0x01
  419. #define GPORC_0GIN1 0x02
  420. #define GPORC_0IO3A 0x02
  421. #define GPORC_1NONE 0x00
  422. #define GPORC_1GIN0 0x04
  423. #define GPORC_1GIN1 0x08
  424. #define GPORC_1IO3C 0x0c
  425. #define GPORC_2NONE 0x00
  426. #define GPORC_2GIN0 0x10
  427. #define GPORC_2GIN1 0x20
  428. #define GPORC_2IO3E 0x20
  429. #define GPORC_3NONE 0x00
  430. #define GPORC_3GIN0 0x40
  431. #define GPORC_3GIN1 0x80
  432. #define GPORC_3IO3G 0xc0
  433. /*****************************************************************************/
  434. /*
  435. * General purpose output data register.
  436. */
  437. #define GPOD_0MASK 0x03
  438. #define GPOD_0SET1 0x00
  439. #define GPOD_0SET0 0x01
  440. #define GPOD_0SETR0 0x02
  441. #define GPOD_0SETIO3B 0x03
  442. #define GPOD_1MASK 0x0c
  443. #define GPOD_1SET1 0x00
  444. #define GPOD_1SET0 0x04
  445. #define GPOD_1SETR0 0x08
  446. #define GPOD_1SETIO3D 0x0c
  447. #define GPOD_2MASK 0x30
  448. #define GPOD_2SET1 0x00
  449. #define GPOD_2SET0 0x10
  450. #define GPOD_2SETR0 0x20
  451. #define GPOD_2SETIO3F 0x30
  452. #define GPOD_3MASK 0xc0
  453. #define GPOD_3SET1 0x00
  454. #define GPOD_3SET0 0x40
  455. #define GPOD_3SETR0 0x80
  456. #define GPOD_3SETIO3H 0xc0
  457. /*****************************************************************************/
  458. #endif