pci_regs.h 24 KB

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  1. /*
  2. * pci_regs.h
  3. *
  4. * PCI standard defines
  5. * Copyright 1994, Drew Eckhardt
  6. * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
  7. *
  8. * For more information, please consult the following manuals (look at
  9. * http://www.pcisig.com/ for how to get them):
  10. *
  11. * PCI BIOS Specification
  12. * PCI Local Bus Specification
  13. * PCI to PCI Bridge Specification
  14. * PCI System Design Guide
  15. *
  16. * For hypertransport information, please consult the following manuals
  17. * from http://www.hypertransport.org
  18. *
  19. * The Hypertransport I/O Link Specification
  20. */
  21. #ifndef LINUX_PCI_REGS_H
  22. #define LINUX_PCI_REGS_H
  23. /*
  24. * Under PCI, each device has 256 bytes of configuration address space,
  25. * of which the first 64 bytes are standardized as follows:
  26. */
  27. #define PCI_VENDOR_ID 0x00 /* 16 bits */
  28. #define PCI_DEVICE_ID 0x02 /* 16 bits */
  29. #define PCI_COMMAND 0x04 /* 16 bits */
  30. #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
  31. #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
  32. #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
  33. #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
  34. #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
  35. #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
  36. #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
  37. #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
  38. #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
  39. #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
  40. #define PCI_COMMAND_INTX_DISABLE 0x400 /* INTx Emulation Disable */
  41. #define PCI_STATUS 0x06 /* 16 bits */
  42. #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
  43. #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
  44. #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
  45. #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
  46. #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
  47. #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
  48. #define PCI_STATUS_DEVSEL_FAST 0x000
  49. #define PCI_STATUS_DEVSEL_MEDIUM 0x200
  50. #define PCI_STATUS_DEVSEL_SLOW 0x400
  51. #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  52. #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  53. #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  54. #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  55. #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  56. #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8 revision */
  57. #define PCI_REVISION_ID 0x08 /* Revision ID */
  58. #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
  59. #define PCI_CLASS_DEVICE 0x0a /* Device class */
  60. #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
  61. #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
  62. #define PCI_HEADER_TYPE 0x0e /* 8 bits */
  63. #define PCI_HEADER_TYPE_NORMAL 0
  64. #define PCI_HEADER_TYPE_BRIDGE 1
  65. #define PCI_HEADER_TYPE_CARDBUS 2
  66. #define PCI_BIST 0x0f /* 8 bits */
  67. #define PCI_BIST_CODE_MASK 0x0f /* Return result */
  68. #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
  69. #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
  70. /*
  71. * Base addresses specify locations in memory or I/O space.
  72. * Decoded size can be determined by writing a value of
  73. * 0xffffffff to the register, and reading it back. Only
  74. * 1 bits are decoded.
  75. */
  76. #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
  77. #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
  78. #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
  79. #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
  80. #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
  81. #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
  82. #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
  83. #define PCI_BASE_ADDRESS_SPACE_IO 0x01
  84. #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  85. #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
  86. #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
  87. #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
  88. #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
  89. #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
  90. #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fUL)
  91. #define PCI_BASE_ADDRESS_IO_MASK (~0x03UL)
  92. /* bit 1 is reserved if address_space = 1 */
  93. /* Header type 0 (normal devices) */
  94. #define PCI_CARDBUS_CIS 0x28
  95. #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
  96. #define PCI_SUBSYSTEM_ID 0x2e
  97. #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
  98. #define PCI_ROM_ADDRESS_ENABLE 0x01
  99. #define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
  100. #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
  101. /* 0x35-0x3b are reserved */
  102. #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
  103. #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
  104. #define PCI_MIN_GNT 0x3e /* 8 bits */
  105. #define PCI_MAX_LAT 0x3f /* 8 bits */
  106. /* Header type 1 (PCI-to-PCI bridges) */
  107. #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
  108. #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
  109. #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
  110. #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
  111. #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
  112. #define PCI_IO_LIMIT 0x1d
  113. #define PCI_IO_RANGE_TYPE_MASK 0x0fUL /* I/O bridging type */
  114. #define PCI_IO_RANGE_TYPE_16 0x00
  115. #define PCI_IO_RANGE_TYPE_32 0x01
  116. #define PCI_IO_RANGE_MASK (~0x0fUL)
  117. #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
  118. #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
  119. #define PCI_MEMORY_LIMIT 0x22
  120. #define PCI_MEMORY_RANGE_TYPE_MASK 0x0fUL
  121. #define PCI_MEMORY_RANGE_MASK (~0x0fUL)
  122. #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
  123. #define PCI_PREF_MEMORY_LIMIT 0x26
  124. #define PCI_PREF_RANGE_TYPE_MASK 0x0fUL
  125. #define PCI_PREF_RANGE_TYPE_32 0x00
  126. #define PCI_PREF_RANGE_TYPE_64 0x01
  127. #define PCI_PREF_RANGE_MASK (~0x0fUL)
  128. #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
  129. #define PCI_PREF_LIMIT_UPPER32 0x2c
  130. #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
  131. #define PCI_IO_LIMIT_UPPER16 0x32
  132. /* 0x34 same as for htype 0 */
  133. /* 0x35-0x3b is reserved */
  134. #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
  135. /* 0x3c-0x3d are same as for htype 0 */
  136. #define PCI_BRIDGE_CONTROL 0x3e
  137. #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
  138. #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
  139. #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
  140. #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
  141. #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
  142. #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
  143. #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
  144. /* Header type 2 (CardBus bridges) */
  145. #define PCI_CB_CAPABILITY_LIST 0x14
  146. /* 0x15 reserved */
  147. #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
  148. #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
  149. #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
  150. #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
  151. #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
  152. #define PCI_CB_MEMORY_BASE_0 0x1c
  153. #define PCI_CB_MEMORY_LIMIT_0 0x20
  154. #define PCI_CB_MEMORY_BASE_1 0x24
  155. #define PCI_CB_MEMORY_LIMIT_1 0x28
  156. #define PCI_CB_IO_BASE_0 0x2c
  157. #define PCI_CB_IO_BASE_0_HI 0x2e
  158. #define PCI_CB_IO_LIMIT_0 0x30
  159. #define PCI_CB_IO_LIMIT_0_HI 0x32
  160. #define PCI_CB_IO_BASE_1 0x34
  161. #define PCI_CB_IO_BASE_1_HI 0x36
  162. #define PCI_CB_IO_LIMIT_1 0x38
  163. #define PCI_CB_IO_LIMIT_1_HI 0x3a
  164. #define PCI_CB_IO_RANGE_MASK (~0x03UL)
  165. /* 0x3c-0x3d are same as for htype 0 */
  166. #define PCI_CB_BRIDGE_CONTROL 0x3e
  167. #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
  168. #define PCI_CB_BRIDGE_CTL_SERR 0x02
  169. #define PCI_CB_BRIDGE_CTL_ISA 0x04
  170. #define PCI_CB_BRIDGE_CTL_VGA 0x08
  171. #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
  172. #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
  173. #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
  174. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
  175. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
  176. #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
  177. #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
  178. #define PCI_CB_SUBSYSTEM_ID 0x42
  179. #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
  180. /* 0x48-0x7f reserved */
  181. /* Capability lists */
  182. #define PCI_CAP_LIST_ID 0 /* Capability ID */
  183. #define PCI_CAP_ID_PM 0x01 /* Power Management */
  184. #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
  185. #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
  186. #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
  187. #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
  188. #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
  189. #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
  190. #define PCI_CAP_ID_HT 0x08 /* HyperTransport */
  191. #define PCI_CAP_ID_VNDR 0x09 /* Vendor specific capability */
  192. #define PCI_CAP_ID_SHPC 0x0C /* PCI Standard Hot-Plug Controller */
  193. #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
  194. #define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
  195. #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
  196. #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
  197. #define PCI_CAP_SIZEOF 4
  198. /* Power Management Registers */
  199. #define PCI_PM_PMC 2 /* PM Capabilities Register */
  200. #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
  201. #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
  202. #define PCI_PM_CAP_RESERVED 0x0010 /* Reserved field */
  203. #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
  204. #define PCI_PM_CAP_AUX_POWER 0x01C0 /* Auxilliary power support mask */
  205. #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
  206. #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
  207. #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
  208. #define PCI_PM_CAP_PME_MASK 0xF800 /* PME Mask of all supported states */
  209. #define PCI_PM_CAP_PME_D0 0x0800 /* PME# from D0 */
  210. #define PCI_PM_CAP_PME_D1 0x1000 /* PME# from D1 */
  211. #define PCI_PM_CAP_PME_D2 0x2000 /* PME# from D2 */
  212. #define PCI_PM_CAP_PME_D3 0x4000 /* PME# from D3 (hot) */
  213. #define PCI_PM_CAP_PME_D3cold 0x8000 /* PME# from D3 (cold) */
  214. #define PCI_PM_CTRL 4 /* PM control and status register */
  215. #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
  216. #define PCI_PM_CTRL_NO_SOFT_RESET 0x0004 /* No reset for D3hot->D0 */
  217. #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
  218. #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
  219. #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
  220. #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
  221. #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
  222. #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
  223. #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
  224. #define PCI_PM_DATA_REGISTER 7 /* (??) */
  225. #define PCI_PM_SIZEOF 8
  226. /* AGP registers */
  227. #define PCI_AGP_VERSION 2 /* BCD version number */
  228. #define PCI_AGP_RFU 3 /* Rest of capability flags */
  229. #define PCI_AGP_STATUS 4 /* Status register */
  230. #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
  231. #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
  232. #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
  233. #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
  234. #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
  235. #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
  236. #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
  237. #define PCI_AGP_COMMAND 8 /* Control register */
  238. #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
  239. #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
  240. #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
  241. #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
  242. #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
  243. #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
  244. #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 2x rate */
  245. #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 1x rate */
  246. #define PCI_AGP_SIZEOF 12
  247. /* Vital Product Data */
  248. #define PCI_VPD_ADDR 2 /* Address to access (15 bits!) */
  249. #define PCI_VPD_ADDR_MASK 0x7fff /* Address mask */
  250. #define PCI_VPD_ADDR_F 0x8000 /* Write 0, 1 indicates completion */
  251. #define PCI_VPD_DATA 4 /* 32-bits of data returned here */
  252. /* Slot Identification */
  253. #define PCI_SID_ESR 2 /* Expansion Slot Register */
  254. #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
  255. #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
  256. #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
  257. /* Message Signalled Interrupts registers */
  258. #define PCI_MSI_FLAGS 2 /* Various flags */
  259. #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
  260. #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
  261. #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
  262. #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
  263. #define PCI_MSI_FLAGS_MASKBIT 0x100 /* 64-bit mask bits allowed */
  264. #define PCI_MSI_RFU 3 /* Rest of capability flags */
  265. #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
  266. #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
  267. #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
  268. #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
  269. #define PCI_MSI_MASK_BIT 16 /* Mask bits register */
  270. /* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
  271. #define PCI_MSIX_FLAGS 2
  272. #define PCI_MSIX_FLAGS_QSIZE 0x7FF
  273. #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
  274. #define PCI_MSIX_FLAGS_MASKALL (1 << 14)
  275. #define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
  276. #define PCI_MSIX_FLAGS_BITMASK (1 << 0)
  277. /* CompactPCI Hotswap Register */
  278. #define PCI_CHSWP_CSR 2 /* Control and Status Register */
  279. #define PCI_CHSWP_DHA 0x01 /* Device Hiding Arm */
  280. #define PCI_CHSWP_EIM 0x02 /* ENUM# Signal Mask */
  281. #define PCI_CHSWP_PIE 0x04 /* Pending Insert or Extract */
  282. #define PCI_CHSWP_LOO 0x08 /* LED On / Off */
  283. #define PCI_CHSWP_PI 0x30 /* Programming Interface */
  284. #define PCI_CHSWP_EXT 0x40 /* ENUM# status - extraction */
  285. #define PCI_CHSWP_INS 0x80 /* ENUM# status - insertion */
  286. /* PCI-X registers */
  287. #define PCI_X_CMD 2 /* Modes & Features */
  288. #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
  289. #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
  290. #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
  291. #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
  292. #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
  293. #define PCI_X_STATUS 4 /* PCI-X capabilities */
  294. #define PCI_X_STATUS_DEVFN 0x000000ff /* A copy of devfn */
  295. #define PCI_X_STATUS_BUS 0x0000ff00 /* A copy of bus nr */
  296. #define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
  297. #define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
  298. #define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
  299. #define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
  300. #define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
  301. #define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
  302. #define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
  303. #define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
  304. #define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
  305. #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
  306. #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
  307. /* PCI Express capability registers */
  308. #define PCI_EXP_FLAGS 2 /* Capabilities register */
  309. #define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
  310. #define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
  311. #define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
  312. #define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
  313. #define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
  314. #define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
  315. #define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
  316. #define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCI/PCI-X Bridge */
  317. #define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
  318. #define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
  319. #define PCI_EXP_DEVCAP 4 /* Device capabilities */
  320. #define PCI_EXP_DEVCAP_PAYLOAD 0x07 /* Max_Payload_Size */
  321. #define PCI_EXP_DEVCAP_PHANTOM 0x18 /* Phantom functions */
  322. #define PCI_EXP_DEVCAP_EXT_TAG 0x20 /* Extended tags */
  323. #define PCI_EXP_DEVCAP_L0S 0x1c0 /* L0s Acceptable Latency */
  324. #define PCI_EXP_DEVCAP_L1 0xe00 /* L1 Acceptable Latency */
  325. #define PCI_EXP_DEVCAP_ATN_BUT 0x1000 /* Attention Button Present */
  326. #define PCI_EXP_DEVCAP_ATN_IND 0x2000 /* Attention Indicator Present */
  327. #define PCI_EXP_DEVCAP_PWR_IND 0x4000 /* Power Indicator Present */
  328. #define PCI_EXP_DEVCAP_PWR_VAL 0x3fc0000 /* Slot Power Limit Value */
  329. #define PCI_EXP_DEVCAP_PWR_SCL 0xc000000 /* Slot Power Limit Scale */
  330. #define PCI_EXP_DEVCTL 8 /* Device Control */
  331. #define PCI_EXP_DEVCTL_CERE 0x0001 /* Correctable Error Reporting En. */
  332. #define PCI_EXP_DEVCTL_NFERE 0x0002 /* Non-Fatal Error Reporting Enable */
  333. #define PCI_EXP_DEVCTL_FERE 0x0004 /* Fatal Error Reporting Enable */
  334. #define PCI_EXP_DEVCTL_URRE 0x0008 /* Unsupported Request Reporting En. */
  335. #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
  336. #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
  337. #define PCI_EXP_DEVCTL_EXT_TAG 0x0100 /* Extended Tag Field Enable */
  338. #define PCI_EXP_DEVCTL_PHANTOM 0x0200 /* Phantom Functions Enable */
  339. #define PCI_EXP_DEVCTL_AUX_PME 0x0400 /* Auxiliary Power PM Enable */
  340. #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
  341. #define PCI_EXP_DEVCTL_READRQ 0x7000 /* Max_Read_Request_Size */
  342. #define PCI_EXP_DEVSTA 10 /* Device Status */
  343. #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
  344. #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
  345. #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
  346. #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
  347. #define PCI_EXP_DEVSTA_AUXPD 0x10 /* AUX Power Detected */
  348. #define PCI_EXP_DEVSTA_TRPND 0x20 /* Transactions Pending */
  349. #define PCI_EXP_LNKCAP 12 /* Link Capabilities */
  350. #define PCI_EXP_LNKCTL 16 /* Link Control */
  351. #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
  352. #define PCI_EXP_LNKSTA 18 /* Link Status */
  353. #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */
  354. #define PCI_EXP_SLTCTL 24 /* Slot Control */
  355. #define PCI_EXP_SLTSTA 26 /* Slot Status */
  356. #define PCI_EXP_RTCTL 28 /* Root Control */
  357. #define PCI_EXP_RTCTL_SECEE 0x01 /* System Error on Correctable Error */
  358. #define PCI_EXP_RTCTL_SENFEE 0x02 /* System Error on Non-Fatal Error */
  359. #define PCI_EXP_RTCTL_SEFEE 0x04 /* System Error on Fatal Error */
  360. #define PCI_EXP_RTCTL_PMEIE 0x08 /* PME Interrupt Enable */
  361. #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
  362. #define PCI_EXP_RTCAP 30 /* Root Capabilities */
  363. #define PCI_EXP_RTSTA 32 /* Root Status */
  364. /* Extended Capabilities (PCI-X 2.0 and Express) */
  365. #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
  366. #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
  367. #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
  368. #define PCI_EXT_CAP_ID_ERR 1
  369. #define PCI_EXT_CAP_ID_VC 2
  370. #define PCI_EXT_CAP_ID_DSN 3
  371. #define PCI_EXT_CAP_ID_PWR 4
  372. /* Advanced Error Reporting */
  373. #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
  374. #define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */
  375. #define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
  376. #define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */
  377. #define PCI_ERR_UNC_FCP 0x00002000 /* Flow Control Protocol */
  378. #define PCI_ERR_UNC_COMP_TIME 0x00004000 /* Completion Timeout */
  379. #define PCI_ERR_UNC_COMP_ABORT 0x00008000 /* Completer Abort */
  380. #define PCI_ERR_UNC_UNX_COMP 0x00010000 /* Unexpected Completion */
  381. #define PCI_ERR_UNC_RX_OVER 0x00020000 /* Receiver Overflow */
  382. #define PCI_ERR_UNC_MALF_TLP 0x00040000 /* Malformed TLP */
  383. #define PCI_ERR_UNC_ECRC 0x00080000 /* ECRC Error Status */
  384. #define PCI_ERR_UNC_UNSUP 0x00100000 /* Unsupported Request */
  385. #define PCI_ERR_UNCOR_MASK 8 /* Uncorrectable Error Mask */
  386. /* Same bits as above */
  387. #define PCI_ERR_UNCOR_SEVER 12 /* Uncorrectable Error Severity */
  388. /* Same bits as above */
  389. #define PCI_ERR_COR_STATUS 16 /* Correctable Error Status */
  390. #define PCI_ERR_COR_RCVR 0x00000001 /* Receiver Error Status */
  391. #define PCI_ERR_COR_BAD_TLP 0x00000040 /* Bad TLP Status */
  392. #define PCI_ERR_COR_BAD_DLLP 0x00000080 /* Bad DLLP Status */
  393. #define PCI_ERR_COR_REP_ROLL 0x00000100 /* REPLAY_NUM Rollover */
  394. #define PCI_ERR_COR_REP_TIMER 0x00001000 /* Replay Timer Timeout */
  395. #define PCI_ERR_COR_MASK 20 /* Correctable Error Mask */
  396. /* Same bits as above */
  397. #define PCI_ERR_CAP 24 /* Advanced Error Capabilities */
  398. #define PCI_ERR_CAP_FEP(x) ((x) & 31) /* First Error Pointer */
  399. #define PCI_ERR_CAP_ECRC_GENC 0x00000020 /* ECRC Generation Capable */
  400. #define PCI_ERR_CAP_ECRC_GENE 0x00000040 /* ECRC Generation Enable */
  401. #define PCI_ERR_CAP_ECRC_CHKC 0x00000080 /* ECRC Check Capable */
  402. #define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
  403. #define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
  404. #define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
  405. /* Correctable Err Reporting Enable */
  406. #define PCI_ERR_ROOT_CMD_COR_EN 0x00000001
  407. /* Non-fatal Err Reporting Enable */
  408. #define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002
  409. /* Fatal Err Reporting Enable */
  410. #define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004
  411. #define PCI_ERR_ROOT_STATUS 48
  412. #define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
  413. /* Multi ERR_COR Received */
  414. #define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002
  415. /* ERR_FATAL/NONFATAL Recevied */
  416. #define PCI_ERR_ROOT_UNCOR_RCV 0x00000004
  417. /* Multi ERR_FATAL/NONFATAL Recevied */
  418. #define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008
  419. #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
  420. #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
  421. #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
  422. #define PCI_ERR_ROOT_COR_SRC 52
  423. #define PCI_ERR_ROOT_SRC 54
  424. /* Virtual Channel */
  425. #define PCI_VC_PORT_REG1 4
  426. #define PCI_VC_PORT_REG2 8
  427. #define PCI_VC_PORT_CTRL 12
  428. #define PCI_VC_PORT_STATUS 14
  429. #define PCI_VC_RES_CAP 16
  430. #define PCI_VC_RES_CTRL 20
  431. #define PCI_VC_RES_STATUS 26
  432. /* Power Budgeting */
  433. #define PCI_PWR_DSR 4 /* Data Select Register */
  434. #define PCI_PWR_DATA 8 /* Data Register */
  435. #define PCI_PWR_DATA_BASE(x) ((x) & 0xff) /* Base Power */
  436. #define PCI_PWR_DATA_SCALE(x) (((x) >> 8) & 3) /* Data Scale */
  437. #define PCI_PWR_DATA_PM_SUB(x) (((x) >> 10) & 7) /* PM Sub State */
  438. #define PCI_PWR_DATA_PM_STATE(x) (((x) >> 13) & 3) /* PM State */
  439. #define PCI_PWR_DATA_TYPE(x) (((x) >> 15) & 7) /* Type */
  440. #define PCI_PWR_DATA_RAIL(x) (((x) >> 18) & 7) /* Power Rail */
  441. #define PCI_PWR_CAP 12 /* Capability */
  442. #define PCI_PWR_CAP_BUDGET(x) ((x) & 1) /* Included in system budget */
  443. /*
  444. * Hypertransport sub capability types
  445. *
  446. * Unfortunately there are both 3 bit and 5 bit capability types defined
  447. * in the HT spec, catering for that is a little messy. You probably don't
  448. * want to use these directly, just use pci_find_ht_capability() and it
  449. * will do the right thing for you.
  450. */
  451. #define HT_3BIT_CAP_MASK 0xE0
  452. #define HT_CAPTYPE_SLAVE 0x00 /* Slave/Primary link configuration */
  453. #define HT_CAPTYPE_HOST 0x20 /* Host/Secondary link configuration */
  454. #define HT_5BIT_CAP_MASK 0xF8
  455. #define HT_CAPTYPE_IRQ 0x80 /* IRQ Configuration */
  456. #define HT_CAPTYPE_REMAPPING_40 0xA0 /* 40 bit address remapping */
  457. #define HT_CAPTYPE_REMAPPING_64 0xA2 /* 64 bit address remapping */
  458. #define HT_CAPTYPE_UNITID_CLUMP 0x90 /* Unit ID clumping */
  459. #define HT_CAPTYPE_EXTCONF 0x98 /* Extended Configuration Space Access */
  460. #define HT_CAPTYPE_MSI_MAPPING 0xA8 /* MSI Mapping Capability */
  461. #define HT_MSI_FLAGS 0x02 /* Offset to flags */
  462. #define HT_MSI_FLAGS_ENABLE 0x1 /* Mapping enable */
  463. #define HT_MSI_FLAGS_FIXED 0x2 /* Fixed mapping only */
  464. #define HT_MSI_FIXED_ADDR 0x00000000FEE00000ULL /* Fixed addr */
  465. #define HT_MSI_ADDR_LO 0x04 /* Offset to low addr bits */
  466. #define HT_MSI_ADDR_LO_MASK 0xFFF00000 /* Low address bit mask */
  467. #define HT_MSI_ADDR_HI 0x08 /* Offset to high addr bits */
  468. #define HT_CAPTYPE_DIRECT_ROUTE 0xB0 /* Direct routing configuration */
  469. #define HT_CAPTYPE_VCSET 0xB8 /* Virtual Channel configuration */
  470. #define HT_CAPTYPE_ERROR_RETRY 0xC0 /* Retry on error configuration */
  471. #define HT_CAPTYPE_GEN3 0xD0 /* Generation 3 hypertransport configuration */
  472. #define HT_CAPTYPE_PM 0xE0 /* Hypertransport powermanagement configuration */
  473. #endif /* LINUX_PCI_REGS_H */