mv643xx.h 71 KB

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  1. /*
  2. * mv643xx.h - MV-643XX Internal registers definition file.
  3. *
  4. * Copyright 2002 Momentum Computer, Inc.
  5. * Author: Matthew Dharm <mdharm@momenco.com>
  6. * Copyright 2002 GALILEO TECHNOLOGY, LTD.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #ifndef __ASM_MV643XX_H
  14. #define __ASM_MV643XX_H
  15. #ifdef __mips__
  16. #include <asm/addrspace.h>
  17. #include <asm/marvell.h>
  18. #endif
  19. #include <asm/types.h>
  20. /****************************************/
  21. /* Processor Address Space */
  22. /****************************************/
  23. /* DDR SDRAM BAR and size registers */
  24. #define MV64340_CS_0_BASE_ADDR 0x008
  25. #define MV64340_CS_0_SIZE 0x010
  26. #define MV64340_CS_1_BASE_ADDR 0x208
  27. #define MV64340_CS_1_SIZE 0x210
  28. #define MV64340_CS_2_BASE_ADDR 0x018
  29. #define MV64340_CS_2_SIZE 0x020
  30. #define MV64340_CS_3_BASE_ADDR 0x218
  31. #define MV64340_CS_3_SIZE 0x220
  32. /* Devices BAR and size registers */
  33. #define MV64340_DEV_CS0_BASE_ADDR 0x028
  34. #define MV64340_DEV_CS0_SIZE 0x030
  35. #define MV64340_DEV_CS1_BASE_ADDR 0x228
  36. #define MV64340_DEV_CS1_SIZE 0x230
  37. #define MV64340_DEV_CS2_BASE_ADDR 0x248
  38. #define MV64340_DEV_CS2_SIZE 0x250
  39. #define MV64340_DEV_CS3_BASE_ADDR 0x038
  40. #define MV64340_DEV_CS3_SIZE 0x040
  41. #define MV64340_BOOTCS_BASE_ADDR 0x238
  42. #define MV64340_BOOTCS_SIZE 0x240
  43. /* PCI 0 BAR and size registers */
  44. #define MV64340_PCI_0_IO_BASE_ADDR 0x048
  45. #define MV64340_PCI_0_IO_SIZE 0x050
  46. #define MV64340_PCI_0_MEMORY0_BASE_ADDR 0x058
  47. #define MV64340_PCI_0_MEMORY0_SIZE 0x060
  48. #define MV64340_PCI_0_MEMORY1_BASE_ADDR 0x080
  49. #define MV64340_PCI_0_MEMORY1_SIZE 0x088
  50. #define MV64340_PCI_0_MEMORY2_BASE_ADDR 0x258
  51. #define MV64340_PCI_0_MEMORY2_SIZE 0x260
  52. #define MV64340_PCI_0_MEMORY3_BASE_ADDR 0x280
  53. #define MV64340_PCI_0_MEMORY3_SIZE 0x288
  54. /* PCI 1 BAR and size registers */
  55. #define MV64340_PCI_1_IO_BASE_ADDR 0x090
  56. #define MV64340_PCI_1_IO_SIZE 0x098
  57. #define MV64340_PCI_1_MEMORY0_BASE_ADDR 0x0a0
  58. #define MV64340_PCI_1_MEMORY0_SIZE 0x0a8
  59. #define MV64340_PCI_1_MEMORY1_BASE_ADDR 0x0b0
  60. #define MV64340_PCI_1_MEMORY1_SIZE 0x0b8
  61. #define MV64340_PCI_1_MEMORY2_BASE_ADDR 0x2a0
  62. #define MV64340_PCI_1_MEMORY2_SIZE 0x2a8
  63. #define MV64340_PCI_1_MEMORY3_BASE_ADDR 0x2b0
  64. #define MV64340_PCI_1_MEMORY3_SIZE 0x2b8
  65. /* SRAM base address */
  66. #define MV64340_INTEGRATED_SRAM_BASE_ADDR 0x268
  67. /* internal registers space base address */
  68. #define MV64340_INTERNAL_SPACE_BASE_ADDR 0x068
  69. /* Enables the CS , DEV_CS , PCI 0 and PCI 1
  70. windows above */
  71. #define MV64340_BASE_ADDR_ENABLE 0x278
  72. /****************************************/
  73. /* PCI remap registers */
  74. /****************************************/
  75. /* PCI 0 */
  76. #define MV64340_PCI_0_IO_ADDR_REMAP 0x0f0
  77. #define MV64340_PCI_0_MEMORY0_LOW_ADDR_REMAP 0x0f8
  78. #define MV64340_PCI_0_MEMORY0_HIGH_ADDR_REMAP 0x320
  79. #define MV64340_PCI_0_MEMORY1_LOW_ADDR_REMAP 0x100
  80. #define MV64340_PCI_0_MEMORY1_HIGH_ADDR_REMAP 0x328
  81. #define MV64340_PCI_0_MEMORY2_LOW_ADDR_REMAP 0x2f8
  82. #define MV64340_PCI_0_MEMORY2_HIGH_ADDR_REMAP 0x330
  83. #define MV64340_PCI_0_MEMORY3_LOW_ADDR_REMAP 0x300
  84. #define MV64340_PCI_0_MEMORY3_HIGH_ADDR_REMAP 0x338
  85. /* PCI 1 */
  86. #define MV64340_PCI_1_IO_ADDR_REMAP 0x108
  87. #define MV64340_PCI_1_MEMORY0_LOW_ADDR_REMAP 0x110
  88. #define MV64340_PCI_1_MEMORY0_HIGH_ADDR_REMAP 0x340
  89. #define MV64340_PCI_1_MEMORY1_LOW_ADDR_REMAP 0x118
  90. #define MV64340_PCI_1_MEMORY1_HIGH_ADDR_REMAP 0x348
  91. #define MV64340_PCI_1_MEMORY2_LOW_ADDR_REMAP 0x310
  92. #define MV64340_PCI_1_MEMORY2_HIGH_ADDR_REMAP 0x350
  93. #define MV64340_PCI_1_MEMORY3_LOW_ADDR_REMAP 0x318
  94. #define MV64340_PCI_1_MEMORY3_HIGH_ADDR_REMAP 0x358
  95. #define MV64340_CPU_PCI_0_HEADERS_RETARGET_CONTROL 0x3b0
  96. #define MV64340_CPU_PCI_0_HEADERS_RETARGET_BASE 0x3b8
  97. #define MV64340_CPU_PCI_1_HEADERS_RETARGET_CONTROL 0x3c0
  98. #define MV64340_CPU_PCI_1_HEADERS_RETARGET_BASE 0x3c8
  99. #define MV64340_CPU_GE_HEADERS_RETARGET_CONTROL 0x3d0
  100. #define MV64340_CPU_GE_HEADERS_RETARGET_BASE 0x3d8
  101. #define MV64340_CPU_IDMA_HEADERS_RETARGET_CONTROL 0x3e0
  102. #define MV64340_CPU_IDMA_HEADERS_RETARGET_BASE 0x3e8
  103. /****************************************/
  104. /* CPU Control Registers */
  105. /****************************************/
  106. #define MV64340_CPU_CONFIG 0x000
  107. #define MV64340_CPU_MODE 0x120
  108. #define MV64340_CPU_MASTER_CONTROL 0x160
  109. #define MV64340_CPU_CROSS_BAR_CONTROL_LOW 0x150
  110. #define MV64340_CPU_CROSS_BAR_CONTROL_HIGH 0x158
  111. #define MV64340_CPU_CROSS_BAR_TIMEOUT 0x168
  112. /****************************************/
  113. /* SMP RegisterS */
  114. /****************************************/
  115. #define MV64340_SMP_WHO_AM_I 0x200
  116. #define MV64340_SMP_CPU0_DOORBELL 0x214
  117. #define MV64340_SMP_CPU0_DOORBELL_CLEAR 0x21C
  118. #define MV64340_SMP_CPU1_DOORBELL 0x224
  119. #define MV64340_SMP_CPU1_DOORBELL_CLEAR 0x22C
  120. #define MV64340_SMP_CPU0_DOORBELL_MASK 0x234
  121. #define MV64340_SMP_CPU1_DOORBELL_MASK 0x23C
  122. #define MV64340_SMP_SEMAPHOR0 0x244
  123. #define MV64340_SMP_SEMAPHOR1 0x24c
  124. #define MV64340_SMP_SEMAPHOR2 0x254
  125. #define MV64340_SMP_SEMAPHOR3 0x25c
  126. #define MV64340_SMP_SEMAPHOR4 0x264
  127. #define MV64340_SMP_SEMAPHOR5 0x26c
  128. #define MV64340_SMP_SEMAPHOR6 0x274
  129. #define MV64340_SMP_SEMAPHOR7 0x27c
  130. /****************************************/
  131. /* CPU Sync Barrier Register */
  132. /****************************************/
  133. #define MV64340_CPU_0_SYNC_BARRIER_TRIGGER 0x0c0
  134. #define MV64340_CPU_0_SYNC_BARRIER_VIRTUAL 0x0c8
  135. #define MV64340_CPU_1_SYNC_BARRIER_TRIGGER 0x0d0
  136. #define MV64340_CPU_1_SYNC_BARRIER_VIRTUAL 0x0d8
  137. /****************************************/
  138. /* CPU Access Protect */
  139. /****************************************/
  140. #define MV64340_CPU_PROTECT_WINDOW_0_BASE_ADDR 0x180
  141. #define MV64340_CPU_PROTECT_WINDOW_0_SIZE 0x188
  142. #define MV64340_CPU_PROTECT_WINDOW_1_BASE_ADDR 0x190
  143. #define MV64340_CPU_PROTECT_WINDOW_1_SIZE 0x198
  144. #define MV64340_CPU_PROTECT_WINDOW_2_BASE_ADDR 0x1a0
  145. #define MV64340_CPU_PROTECT_WINDOW_2_SIZE 0x1a8
  146. #define MV64340_CPU_PROTECT_WINDOW_3_BASE_ADDR 0x1b0
  147. #define MV64340_CPU_PROTECT_WINDOW_3_SIZE 0x1b8
  148. /****************************************/
  149. /* CPU Error Report */
  150. /****************************************/
  151. #define MV64340_CPU_ERROR_ADDR_LOW 0x070
  152. #define MV64340_CPU_ERROR_ADDR_HIGH 0x078
  153. #define MV64340_CPU_ERROR_DATA_LOW 0x128
  154. #define MV64340_CPU_ERROR_DATA_HIGH 0x130
  155. #define MV64340_CPU_ERROR_PARITY 0x138
  156. #define MV64340_CPU_ERROR_CAUSE 0x140
  157. #define MV64340_CPU_ERROR_MASK 0x148
  158. /****************************************/
  159. /* CPU Interface Debug Registers */
  160. /****************************************/
  161. #define MV64340_PUNIT_SLAVE_DEBUG_LOW 0x360
  162. #define MV64340_PUNIT_SLAVE_DEBUG_HIGH 0x368
  163. #define MV64340_PUNIT_MASTER_DEBUG_LOW 0x370
  164. #define MV64340_PUNIT_MASTER_DEBUG_HIGH 0x378
  165. #define MV64340_PUNIT_MMASK 0x3e4
  166. /****************************************/
  167. /* Integrated SRAM Registers */
  168. /****************************************/
  169. #define MV64340_SRAM_CONFIG 0x380
  170. #define MV64340_SRAM_TEST_MODE 0X3F4
  171. #define MV64340_SRAM_ERROR_CAUSE 0x388
  172. #define MV64340_SRAM_ERROR_ADDR 0x390
  173. #define MV64340_SRAM_ERROR_ADDR_HIGH 0X3F8
  174. #define MV64340_SRAM_ERROR_DATA_LOW 0x398
  175. #define MV64340_SRAM_ERROR_DATA_HIGH 0x3a0
  176. #define MV64340_SRAM_ERROR_DATA_PARITY 0x3a8
  177. /****************************************/
  178. /* SDRAM Configuration */
  179. /****************************************/
  180. #define MV64340_SDRAM_CONFIG 0x1400
  181. #define MV64340_D_UNIT_CONTROL_LOW 0x1404
  182. #define MV64340_D_UNIT_CONTROL_HIGH 0x1424
  183. #define MV64340_SDRAM_TIMING_CONTROL_LOW 0x1408
  184. #define MV64340_SDRAM_TIMING_CONTROL_HIGH 0x140c
  185. #define MV64340_SDRAM_ADDR_CONTROL 0x1410
  186. #define MV64340_SDRAM_OPEN_PAGES_CONTROL 0x1414
  187. #define MV64340_SDRAM_OPERATION 0x1418
  188. #define MV64340_SDRAM_MODE 0x141c
  189. #define MV64340_EXTENDED_DRAM_MODE 0x1420
  190. #define MV64340_SDRAM_CROSS_BAR_CONTROL_LOW 0x1430
  191. #define MV64340_SDRAM_CROSS_BAR_CONTROL_HIGH 0x1434
  192. #define MV64340_SDRAM_CROSS_BAR_TIMEOUT 0x1438
  193. #define MV64340_SDRAM_ADDR_CTRL_PADS_CALIBRATION 0x14c0
  194. #define MV64340_SDRAM_DATA_PADS_CALIBRATION 0x14c4
  195. /****************************************/
  196. /* SDRAM Error Report */
  197. /****************************************/
  198. #define MV64340_SDRAM_ERROR_DATA_LOW 0x1444
  199. #define MV64340_SDRAM_ERROR_DATA_HIGH 0x1440
  200. #define MV64340_SDRAM_ERROR_ADDR 0x1450
  201. #define MV64340_SDRAM_RECEIVED_ECC 0x1448
  202. #define MV64340_SDRAM_CALCULATED_ECC 0x144c
  203. #define MV64340_SDRAM_ECC_CONTROL 0x1454
  204. #define MV64340_SDRAM_ECC_ERROR_COUNTER 0x1458
  205. /******************************************/
  206. /* Controlled Delay Line (CDL) Registers */
  207. /******************************************/
  208. #define MV64340_DFCDL_CONFIG0 0x1480
  209. #define MV64340_DFCDL_CONFIG1 0x1484
  210. #define MV64340_DLL_WRITE 0x1488
  211. #define MV64340_DLL_READ 0x148c
  212. #define MV64340_SRAM_ADDR 0x1490
  213. #define MV64340_SRAM_DATA0 0x1494
  214. #define MV64340_SRAM_DATA1 0x1498
  215. #define MV64340_SRAM_DATA2 0x149c
  216. #define MV64340_DFCL_PROBE 0x14a0
  217. /******************************************/
  218. /* Debug Registers */
  219. /******************************************/
  220. #define MV64340_DUNIT_DEBUG_LOW 0x1460
  221. #define MV64340_DUNIT_DEBUG_HIGH 0x1464
  222. #define MV64340_DUNIT_MMASK 0X1b40
  223. /****************************************/
  224. /* Device Parameters */
  225. /****************************************/
  226. #define MV64340_DEVICE_BANK0_PARAMETERS 0x45c
  227. #define MV64340_DEVICE_BANK1_PARAMETERS 0x460
  228. #define MV64340_DEVICE_BANK2_PARAMETERS 0x464
  229. #define MV64340_DEVICE_BANK3_PARAMETERS 0x468
  230. #define MV64340_DEVICE_BOOT_BANK_PARAMETERS 0x46c
  231. #define MV64340_DEVICE_INTERFACE_CONTROL 0x4c0
  232. #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_LOW 0x4c8
  233. #define MV64340_DEVICE_INTERFACE_CROSS_BAR_CONTROL_HIGH 0x4cc
  234. #define MV64340_DEVICE_INTERFACE_CROSS_BAR_TIMEOUT 0x4c4
  235. /****************************************/
  236. /* Device interrupt registers */
  237. /****************************************/
  238. #define MV64340_DEVICE_INTERRUPT_CAUSE 0x4d0
  239. #define MV64340_DEVICE_INTERRUPT_MASK 0x4d4
  240. #define MV64340_DEVICE_ERROR_ADDR 0x4d8
  241. #define MV64340_DEVICE_ERROR_DATA 0x4dc
  242. #define MV64340_DEVICE_ERROR_PARITY 0x4e0
  243. /****************************************/
  244. /* Device debug registers */
  245. /****************************************/
  246. #define MV64340_DEVICE_DEBUG_LOW 0x4e4
  247. #define MV64340_DEVICE_DEBUG_HIGH 0x4e8
  248. #define MV64340_RUNIT_MMASK 0x4f0
  249. /****************************************/
  250. /* PCI Slave Address Decoding registers */
  251. /****************************************/
  252. #define MV64340_PCI_0_CS_0_BANK_SIZE 0xc08
  253. #define MV64340_PCI_1_CS_0_BANK_SIZE 0xc88
  254. #define MV64340_PCI_0_CS_1_BANK_SIZE 0xd08
  255. #define MV64340_PCI_1_CS_1_BANK_SIZE 0xd88
  256. #define MV64340_PCI_0_CS_2_BANK_SIZE 0xc0c
  257. #define MV64340_PCI_1_CS_2_BANK_SIZE 0xc8c
  258. #define MV64340_PCI_0_CS_3_BANK_SIZE 0xd0c
  259. #define MV64340_PCI_1_CS_3_BANK_SIZE 0xd8c
  260. #define MV64340_PCI_0_DEVCS_0_BANK_SIZE 0xc10
  261. #define MV64340_PCI_1_DEVCS_0_BANK_SIZE 0xc90
  262. #define MV64340_PCI_0_DEVCS_1_BANK_SIZE 0xd10
  263. #define MV64340_PCI_1_DEVCS_1_BANK_SIZE 0xd90
  264. #define MV64340_PCI_0_DEVCS_2_BANK_SIZE 0xd18
  265. #define MV64340_PCI_1_DEVCS_2_BANK_SIZE 0xd98
  266. #define MV64340_PCI_0_DEVCS_3_BANK_SIZE 0xc14
  267. #define MV64340_PCI_1_DEVCS_3_BANK_SIZE 0xc94
  268. #define MV64340_PCI_0_DEVCS_BOOT_BANK_SIZE 0xd14
  269. #define MV64340_PCI_1_DEVCS_BOOT_BANK_SIZE 0xd94
  270. #define MV64340_PCI_0_P2P_MEM0_BAR_SIZE 0xd1c
  271. #define MV64340_PCI_1_P2P_MEM0_BAR_SIZE 0xd9c
  272. #define MV64340_PCI_0_P2P_MEM1_BAR_SIZE 0xd20
  273. #define MV64340_PCI_1_P2P_MEM1_BAR_SIZE 0xda0
  274. #define MV64340_PCI_0_P2P_I_O_BAR_SIZE 0xd24
  275. #define MV64340_PCI_1_P2P_I_O_BAR_SIZE 0xda4
  276. #define MV64340_PCI_0_CPU_BAR_SIZE 0xd28
  277. #define MV64340_PCI_1_CPU_BAR_SIZE 0xda8
  278. #define MV64340_PCI_0_INTERNAL_SRAM_BAR_SIZE 0xe00
  279. #define MV64340_PCI_1_INTERNAL_SRAM_BAR_SIZE 0xe80
  280. #define MV64340_PCI_0_EXPANSION_ROM_BAR_SIZE 0xd2c
  281. #define MV64340_PCI_1_EXPANSION_ROM_BAR_SIZE 0xd9c
  282. #define MV64340_PCI_0_BASE_ADDR_REG_ENABLE 0xc3c
  283. #define MV64340_PCI_1_BASE_ADDR_REG_ENABLE 0xcbc
  284. #define MV64340_PCI_0_CS_0_BASE_ADDR_REMAP 0xc48
  285. #define MV64340_PCI_1_CS_0_BASE_ADDR_REMAP 0xcc8
  286. #define MV64340_PCI_0_CS_1_BASE_ADDR_REMAP 0xd48
  287. #define MV64340_PCI_1_CS_1_BASE_ADDR_REMAP 0xdc8
  288. #define MV64340_PCI_0_CS_2_BASE_ADDR_REMAP 0xc4c
  289. #define MV64340_PCI_1_CS_2_BASE_ADDR_REMAP 0xccc
  290. #define MV64340_PCI_0_CS_3_BASE_ADDR_REMAP 0xd4c
  291. #define MV64340_PCI_1_CS_3_BASE_ADDR_REMAP 0xdcc
  292. #define MV64340_PCI_0_CS_0_BASE_HIGH_ADDR_REMAP 0xF04
  293. #define MV64340_PCI_1_CS_0_BASE_HIGH_ADDR_REMAP 0xF84
  294. #define MV64340_PCI_0_CS_1_BASE_HIGH_ADDR_REMAP 0xF08
  295. #define MV64340_PCI_1_CS_1_BASE_HIGH_ADDR_REMAP 0xF88
  296. #define MV64340_PCI_0_CS_2_BASE_HIGH_ADDR_REMAP 0xF0C
  297. #define MV64340_PCI_1_CS_2_BASE_HIGH_ADDR_REMAP 0xF8C
  298. #define MV64340_PCI_0_CS_3_BASE_HIGH_ADDR_REMAP 0xF10
  299. #define MV64340_PCI_1_CS_3_BASE_HIGH_ADDR_REMAP 0xF90
  300. #define MV64340_PCI_0_DEVCS_0_BASE_ADDR_REMAP 0xc50
  301. #define MV64340_PCI_1_DEVCS_0_BASE_ADDR_REMAP 0xcd0
  302. #define MV64340_PCI_0_DEVCS_1_BASE_ADDR_REMAP 0xd50
  303. #define MV64340_PCI_1_DEVCS_1_BASE_ADDR_REMAP 0xdd0
  304. #define MV64340_PCI_0_DEVCS_2_BASE_ADDR_REMAP 0xd58
  305. #define MV64340_PCI_1_DEVCS_2_BASE_ADDR_REMAP 0xdd8
  306. #define MV64340_PCI_0_DEVCS_3_BASE_ADDR_REMAP 0xc54
  307. #define MV64340_PCI_1_DEVCS_3_BASE_ADDR_REMAP 0xcd4
  308. #define MV64340_PCI_0_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xd54
  309. #define MV64340_PCI_1_DEVCS_BOOTCS_BASE_ADDR_REMAP 0xdd4
  310. #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xd5c
  311. #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_LOW 0xddc
  312. #define MV64340_PCI_0_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xd60
  313. #define MV64340_PCI_1_P2P_MEM0_BASE_ADDR_REMAP_HIGH 0xde0
  314. #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xd64
  315. #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_LOW 0xde4
  316. #define MV64340_PCI_0_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xd68
  317. #define MV64340_PCI_1_P2P_MEM1_BASE_ADDR_REMAP_HIGH 0xde8
  318. #define MV64340_PCI_0_P2P_I_O_BASE_ADDR_REMAP 0xd6c
  319. #define MV64340_PCI_1_P2P_I_O_BASE_ADDR_REMAP 0xdec
  320. #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_LOW 0xd70
  321. #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_LOW 0xdf0
  322. #define MV64340_PCI_0_CPU_BASE_ADDR_REMAP_HIGH 0xd74
  323. #define MV64340_PCI_1_CPU_BASE_ADDR_REMAP_HIGH 0xdf4
  324. #define MV64340_PCI_0_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf00
  325. #define MV64340_PCI_1_INTEGRATED_SRAM_BASE_ADDR_REMAP 0xf80
  326. #define MV64340_PCI_0_EXPANSION_ROM_BASE_ADDR_REMAP 0xf38
  327. #define MV64340_PCI_1_EXPANSION_ROM_BASE_ADDR_REMAP 0xfb8
  328. #define MV64340_PCI_0_ADDR_DECODE_CONTROL 0xd3c
  329. #define MV64340_PCI_1_ADDR_DECODE_CONTROL 0xdbc
  330. #define MV64340_PCI_0_HEADERS_RETARGET_CONTROL 0xF40
  331. #define MV64340_PCI_1_HEADERS_RETARGET_CONTROL 0xFc0
  332. #define MV64340_PCI_0_HEADERS_RETARGET_BASE 0xF44
  333. #define MV64340_PCI_1_HEADERS_RETARGET_BASE 0xFc4
  334. #define MV64340_PCI_0_HEADERS_RETARGET_HIGH 0xF48
  335. #define MV64340_PCI_1_HEADERS_RETARGET_HIGH 0xFc8
  336. /***********************************/
  337. /* PCI Control Register Map */
  338. /***********************************/
  339. #define MV64340_PCI_0_DLL_STATUS_AND_COMMAND 0x1d20
  340. #define MV64340_PCI_1_DLL_STATUS_AND_COMMAND 0x1da0
  341. #define MV64340_PCI_0_MPP_PADS_DRIVE_CONTROL 0x1d1C
  342. #define MV64340_PCI_1_MPP_PADS_DRIVE_CONTROL 0x1d9C
  343. #define MV64340_PCI_0_COMMAND 0xc00
  344. #define MV64340_PCI_1_COMMAND 0xc80
  345. #define MV64340_PCI_0_MODE 0xd00
  346. #define MV64340_PCI_1_MODE 0xd80
  347. #define MV64340_PCI_0_RETRY 0xc04
  348. #define MV64340_PCI_1_RETRY 0xc84
  349. #define MV64340_PCI_0_READ_BUFFER_DISCARD_TIMER 0xd04
  350. #define MV64340_PCI_1_READ_BUFFER_DISCARD_TIMER 0xd84
  351. #define MV64340_PCI_0_MSI_TRIGGER_TIMER 0xc38
  352. #define MV64340_PCI_1_MSI_TRIGGER_TIMER 0xcb8
  353. #define MV64340_PCI_0_ARBITER_CONTROL 0x1d00
  354. #define MV64340_PCI_1_ARBITER_CONTROL 0x1d80
  355. #define MV64340_PCI_0_CROSS_BAR_CONTROL_LOW 0x1d08
  356. #define MV64340_PCI_1_CROSS_BAR_CONTROL_LOW 0x1d88
  357. #define MV64340_PCI_0_CROSS_BAR_CONTROL_HIGH 0x1d0c
  358. #define MV64340_PCI_1_CROSS_BAR_CONTROL_HIGH 0x1d8c
  359. #define MV64340_PCI_0_CROSS_BAR_TIMEOUT 0x1d04
  360. #define MV64340_PCI_1_CROSS_BAR_TIMEOUT 0x1d84
  361. #define MV64340_PCI_0_SYNC_BARRIER_TRIGGER_REG 0x1D18
  362. #define MV64340_PCI_1_SYNC_BARRIER_TRIGGER_REG 0x1D98
  363. #define MV64340_PCI_0_SYNC_BARRIER_VIRTUAL_REG 0x1d10
  364. #define MV64340_PCI_1_SYNC_BARRIER_VIRTUAL_REG 0x1d90
  365. #define MV64340_PCI_0_P2P_CONFIG 0x1d14
  366. #define MV64340_PCI_1_P2P_CONFIG 0x1d94
  367. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_LOW 0x1e00
  368. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_0_HIGH 0x1e04
  369. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_0 0x1e08
  370. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_LOW 0x1e10
  371. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_1_HIGH 0x1e14
  372. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_1 0x1e18
  373. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_LOW 0x1e20
  374. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_2_HIGH 0x1e24
  375. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_2 0x1e28
  376. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_LOW 0x1e30
  377. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_3_HIGH 0x1e34
  378. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_3 0x1e38
  379. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_LOW 0x1e40
  380. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_4_HIGH 0x1e44
  381. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_4 0x1e48
  382. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_LOW 0x1e50
  383. #define MV64340_PCI_0_ACCESS_CONTROL_BASE_5_HIGH 0x1e54
  384. #define MV64340_PCI_0_ACCESS_CONTROL_SIZE_5 0x1e58
  385. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_LOW 0x1e80
  386. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_0_HIGH 0x1e84
  387. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_0 0x1e88
  388. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_LOW 0x1e90
  389. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_1_HIGH 0x1e94
  390. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_1 0x1e98
  391. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_LOW 0x1ea0
  392. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
  393. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_2 0x1ea8
  394. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_LOW 0x1eb0
  395. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
  396. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_3 0x1eb8
  397. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_LOW 0x1ec0
  398. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
  399. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_4 0x1ec8
  400. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_LOW 0x1ed0
  401. #define MV64340_PCI_1_ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
  402. #define MV64340_PCI_1_ACCESS_CONTROL_SIZE_5 0x1ed8
  403. /****************************************/
  404. /* PCI Configuration Access Registers */
  405. /****************************************/
  406. #define MV64340_PCI_0_CONFIG_ADDR 0xcf8
  407. #define MV64340_PCI_0_CONFIG_DATA_VIRTUAL_REG 0xcfc
  408. #define MV64340_PCI_1_CONFIG_ADDR 0xc78
  409. #define MV64340_PCI_1_CONFIG_DATA_VIRTUAL_REG 0xc7c
  410. #define MV64340_PCI_0_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xc34
  411. #define MV64340_PCI_1_INTERRUPT_ACKNOWLEDGE_VIRTUAL_REG 0xcb4
  412. /****************************************/
  413. /* PCI Error Report Registers */
  414. /****************************************/
  415. #define MV64340_PCI_0_SERR_MASK 0xc28
  416. #define MV64340_PCI_1_SERR_MASK 0xca8
  417. #define MV64340_PCI_0_ERROR_ADDR_LOW 0x1d40
  418. #define MV64340_PCI_1_ERROR_ADDR_LOW 0x1dc0
  419. #define MV64340_PCI_0_ERROR_ADDR_HIGH 0x1d44
  420. #define MV64340_PCI_1_ERROR_ADDR_HIGH 0x1dc4
  421. #define MV64340_PCI_0_ERROR_ATTRIBUTE 0x1d48
  422. #define MV64340_PCI_1_ERROR_ATTRIBUTE 0x1dc8
  423. #define MV64340_PCI_0_ERROR_COMMAND 0x1d50
  424. #define MV64340_PCI_1_ERROR_COMMAND 0x1dd0
  425. #define MV64340_PCI_0_ERROR_CAUSE 0x1d58
  426. #define MV64340_PCI_1_ERROR_CAUSE 0x1dd8
  427. #define MV64340_PCI_0_ERROR_MASK 0x1d5c
  428. #define MV64340_PCI_1_ERROR_MASK 0x1ddc
  429. /****************************************/
  430. /* PCI Debug Registers */
  431. /****************************************/
  432. #define MV64340_PCI_0_MMASK 0X1D24
  433. #define MV64340_PCI_1_MMASK 0X1DA4
  434. /*********************************************/
  435. /* PCI Configuration, Function 0, Registers */
  436. /*********************************************/
  437. #define MV64340_PCI_DEVICE_AND_VENDOR_ID 0x000
  438. #define MV64340_PCI_STATUS_AND_COMMAND 0x004
  439. #define MV64340_PCI_CLASS_CODE_AND_REVISION_ID 0x008
  440. #define MV64340_PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
  441. #define MV64340_PCI_SCS_0_BASE_ADDR_LOW 0x010
  442. #define MV64340_PCI_SCS_0_BASE_ADDR_HIGH 0x014
  443. #define MV64340_PCI_SCS_1_BASE_ADDR_LOW 0x018
  444. #define MV64340_PCI_SCS_1_BASE_ADDR_HIGH 0x01C
  445. #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_LOW 0x020
  446. #define MV64340_PCI_INTERNAL_REG_MEM_MAPPED_BASE_ADDR_HIGH 0x024
  447. #define MV64340_PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02c
  448. #define MV64340_PCI_EXPANSION_ROM_BASE_ADDR_REG 0x030
  449. #define MV64340_PCI_CAPABILTY_LIST_POINTER 0x034
  450. #define MV64340_PCI_INTERRUPT_PIN_AND_LINE 0x03C
  451. /* capability list */
  452. #define MV64340_PCI_POWER_MANAGEMENT_CAPABILITY 0x040
  453. #define MV64340_PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
  454. #define MV64340_PCI_VPD_ADDR 0x048
  455. #define MV64340_PCI_VPD_DATA 0x04c
  456. #define MV64340_PCI_MSI_MESSAGE_CONTROL 0x050
  457. #define MV64340_PCI_MSI_MESSAGE_ADDR 0x054
  458. #define MV64340_PCI_MSI_MESSAGE_UPPER_ADDR 0x058
  459. #define MV64340_PCI_MSI_MESSAGE_DATA 0x05c
  460. #define MV64340_PCI_X_COMMAND 0x060
  461. #define MV64340_PCI_X_STATUS 0x064
  462. #define MV64340_PCI_COMPACT_PCI_HOT_SWAP 0x068
  463. /***********************************************/
  464. /* PCI Configuration, Function 1, Registers */
  465. /***********************************************/
  466. #define MV64340_PCI_SCS_2_BASE_ADDR_LOW 0x110
  467. #define MV64340_PCI_SCS_2_BASE_ADDR_HIGH 0x114
  468. #define MV64340_PCI_SCS_3_BASE_ADDR_LOW 0x118
  469. #define MV64340_PCI_SCS_3_BASE_ADDR_HIGH 0x11c
  470. #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_LOW 0x120
  471. #define MV64340_PCI_INTERNAL_SRAM_BASE_ADDR_HIGH 0x124
  472. /***********************************************/
  473. /* PCI Configuration, Function 2, Registers */
  474. /***********************************************/
  475. #define MV64340_PCI_DEVCS_0_BASE_ADDR_LOW 0x210
  476. #define MV64340_PCI_DEVCS_0_BASE_ADDR_HIGH 0x214
  477. #define MV64340_PCI_DEVCS_1_BASE_ADDR_LOW 0x218
  478. #define MV64340_PCI_DEVCS_1_BASE_ADDR_HIGH 0x21c
  479. #define MV64340_PCI_DEVCS_2_BASE_ADDR_LOW 0x220
  480. #define MV64340_PCI_DEVCS_2_BASE_ADDR_HIGH 0x224
  481. /***********************************************/
  482. /* PCI Configuration, Function 3, Registers */
  483. /***********************************************/
  484. #define MV64340_PCI_DEVCS_3_BASE_ADDR_LOW 0x310
  485. #define MV64340_PCI_DEVCS_3_BASE_ADDR_HIGH 0x314
  486. #define MV64340_PCI_BOOT_CS_BASE_ADDR_LOW 0x318
  487. #define MV64340_PCI_BOOT_CS_BASE_ADDR_HIGH 0x31c
  488. #define MV64340_PCI_CPU_BASE_ADDR_LOW 0x220
  489. #define MV64340_PCI_CPU_BASE_ADDR_HIGH 0x224
  490. /***********************************************/
  491. /* PCI Configuration, Function 4, Registers */
  492. /***********************************************/
  493. #define MV64340_PCI_P2P_MEM0_BASE_ADDR_LOW 0x410
  494. #define MV64340_PCI_P2P_MEM0_BASE_ADDR_HIGH 0x414
  495. #define MV64340_PCI_P2P_MEM1_BASE_ADDR_LOW 0x418
  496. #define MV64340_PCI_P2P_MEM1_BASE_ADDR_HIGH 0x41c
  497. #define MV64340_PCI_P2P_I_O_BASE_ADDR 0x420
  498. #define MV64340_PCI_INTERNAL_REGS_I_O_MAPPED_BASE_ADDR 0x424
  499. /****************************************/
  500. /* Messaging Unit Registers (I20) */
  501. /****************************************/
  502. #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_0_SIDE 0x010
  503. #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_0_SIDE 0x014
  504. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_0_SIDE 0x018
  505. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_0_SIDE 0x01C
  506. #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_0_SIDE 0x020
  507. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x024
  508. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x028
  509. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_0_SIDE 0x02C
  510. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_0_SIDE 0x030
  511. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_0_SIDE 0x034
  512. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x040
  513. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_0_SIDE 0x044
  514. #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_0_SIDE 0x050
  515. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_0_SIDE 0x054
  516. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x060
  517. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x064
  518. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x068
  519. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x06C
  520. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_0_SIDE 0x070
  521. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_0_SIDE 0x074
  522. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_0_SIDE 0x0F8
  523. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_0_SIDE 0x0FC
  524. #define MV64340_I2O_INBOUND_MESSAGE_REG0_PCI_1_SIDE 0x090
  525. #define MV64340_I2O_INBOUND_MESSAGE_REG1_PCI_1_SIDE 0x094
  526. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_PCI_1_SIDE 0x098
  527. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_PCI_1_SIDE 0x09C
  528. #define MV64340_I2O_INBOUND_DOORBELL_REG_PCI_1_SIDE 0x0A0
  529. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0A4
  530. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0A8
  531. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_PCI_1_SIDE 0x0AC
  532. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_PCI_1_SIDE 0x0B0
  533. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_PCI_1_SIDE 0x0B4
  534. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C0
  535. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_PCI_1_SIDE 0x0C4
  536. #define MV64340_I2O_QUEUE_CONTROL_REG_PCI_1_SIDE 0x0D0
  537. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_PCI_1_SIDE 0x0D4
  538. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0E0
  539. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0E4
  540. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x0E8
  541. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x0EC
  542. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_PCI_1_SIDE 0x0F0
  543. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_PCI_1_SIDE 0x0F4
  544. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_PCI_1_SIDE 0x078
  545. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_PCI_1_SIDE 0x07C
  546. #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C10
  547. #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C14
  548. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU0_SIDE 0x1C18
  549. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU0_SIDE 0x1C1C
  550. #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU0_SIDE 0x1C20
  551. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C24
  552. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C28
  553. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU0_SIDE 0x1C2C
  554. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU0_SIDE 0x1C30
  555. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU0_SIDE 0x1C34
  556. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C40
  557. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU0_SIDE 0x1C44
  558. #define MV64340_I2O_QUEUE_CONTROL_REG_CPU0_SIDE 0x1C50
  559. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU0_SIDE 0x1C54
  560. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C60
  561. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C64
  562. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1C68
  563. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1C6C
  564. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU0_SIDE 0x1C70
  565. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU0_SIDE 0x1C74
  566. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU0_SIDE 0x1CF8
  567. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU0_SIDE 0x1CFC
  568. #define MV64340_I2O_INBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C90
  569. #define MV64340_I2O_INBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C94
  570. #define MV64340_I2O_OUTBOUND_MESSAGE_REG0_CPU1_SIDE 0x1C98
  571. #define MV64340_I2O_OUTBOUND_MESSAGE_REG1_CPU1_SIDE 0x1C9C
  572. #define MV64340_I2O_INBOUND_DOORBELL_REG_CPU1_SIDE 0x1CA0
  573. #define MV64340_I2O_INBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CA4
  574. #define MV64340_I2O_INBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CA8
  575. #define MV64340_I2O_OUTBOUND_DOORBELL_REG_CPU1_SIDE 0x1CAC
  576. #define MV64340_I2O_OUTBOUND_INTERRUPT_CAUSE_REG_CPU1_SIDE 0x1CB0
  577. #define MV64340_I2O_OUTBOUND_INTERRUPT_MASK_REG_CPU1_SIDE 0x1CB4
  578. #define MV64340_I2O_INBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC0
  579. #define MV64340_I2O_OUTBOUND_QUEUE_PORT_VIRTUAL_REG_CPU1_SIDE 0x1CC4
  580. #define MV64340_I2O_QUEUE_CONTROL_REG_CPU1_SIDE 0x1CD0
  581. #define MV64340_I2O_QUEUE_BASE_ADDR_REG_CPU1_SIDE 0x1CD4
  582. #define MV64340_I2O_INBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CE0
  583. #define MV64340_I2O_INBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CE4
  584. #define MV64340_I2O_INBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1CE8
  585. #define MV64340_I2O_INBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1CEC
  586. #define MV64340_I2O_OUTBOUND_FREE_HEAD_POINTER_REG_CPU1_SIDE 0x1CF0
  587. #define MV64340_I2O_OUTBOUND_FREE_TAIL_POINTER_REG_CPU1_SIDE 0x1CF4
  588. #define MV64340_I2O_OUTBOUND_POST_HEAD_POINTER_REG_CPU1_SIDE 0x1C78
  589. #define MV64340_I2O_OUTBOUND_POST_TAIL_POINTER_REG_CPU1_SIDE 0x1C7C
  590. /****************************************/
  591. /* Ethernet Unit Registers */
  592. /****************************************/
  593. #define MV643XX_ETH_SHARED_REGS 0x2000
  594. #define MV643XX_ETH_SHARED_REGS_SIZE 0x2000
  595. #define MV643XX_ETH_PHY_ADDR_REG 0x2000
  596. #define MV643XX_ETH_SMI_REG 0x2004
  597. #define MV643XX_ETH_UNIT_DEFAULT_ADDR_REG 0x2008
  598. #define MV643XX_ETH_UNIT_DEFAULTID_REG 0x200c
  599. #define MV643XX_ETH_UNIT_INTERRUPT_CAUSE_REG 0x2080
  600. #define MV643XX_ETH_UNIT_INTERRUPT_MASK_REG 0x2084
  601. #define MV643XX_ETH_UNIT_INTERNAL_USE_REG 0x24fc
  602. #define MV643XX_ETH_UNIT_ERROR_ADDR_REG 0x2094
  603. #define MV643XX_ETH_BAR_0 0x2200
  604. #define MV643XX_ETH_BAR_1 0x2208
  605. #define MV643XX_ETH_BAR_2 0x2210
  606. #define MV643XX_ETH_BAR_3 0x2218
  607. #define MV643XX_ETH_BAR_4 0x2220
  608. #define MV643XX_ETH_BAR_5 0x2228
  609. #define MV643XX_ETH_SIZE_REG_0 0x2204
  610. #define MV643XX_ETH_SIZE_REG_1 0x220c
  611. #define MV643XX_ETH_SIZE_REG_2 0x2214
  612. #define MV643XX_ETH_SIZE_REG_3 0x221c
  613. #define MV643XX_ETH_SIZE_REG_4 0x2224
  614. #define MV643XX_ETH_SIZE_REG_5 0x222c
  615. #define MV643XX_ETH_HEADERS_RETARGET_BASE_REG 0x2230
  616. #define MV643XX_ETH_HEADERS_RETARGET_CONTROL_REG 0x2234
  617. #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_0 0x2280
  618. #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_1 0x2284
  619. #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_2 0x2288
  620. #define MV643XX_ETH_HIGH_ADDR_REMAP_REG_3 0x228c
  621. #define MV643XX_ETH_BASE_ADDR_ENABLE_REG 0x2290
  622. #define MV643XX_ETH_ACCESS_PROTECTION_REG(port) (0x2294 + (port<<2))
  623. #define MV643XX_ETH_MIB_COUNTERS_BASE(port) (0x3000 + (port<<7))
  624. #define MV643XX_ETH_PORT_CONFIG_REG(port) (0x2400 + (port<<10))
  625. #define MV643XX_ETH_PORT_CONFIG_EXTEND_REG(port) (0x2404 + (port<<10))
  626. #define MV643XX_ETH_MII_SERIAL_PARAMETRS_REG(port) (0x2408 + (port<<10))
  627. #define MV643XX_ETH_GMII_SERIAL_PARAMETRS_REG(port) (0x240c + (port<<10))
  628. #define MV643XX_ETH_VLAN_ETHERTYPE_REG(port) (0x2410 + (port<<10))
  629. #define MV643XX_ETH_MAC_ADDR_LOW(port) (0x2414 + (port<<10))
  630. #define MV643XX_ETH_MAC_ADDR_HIGH(port) (0x2418 + (port<<10))
  631. #define MV643XX_ETH_SDMA_CONFIG_REG(port) (0x241c + (port<<10))
  632. #define MV643XX_ETH_DSCP_0(port) (0x2420 + (port<<10))
  633. #define MV643XX_ETH_DSCP_1(port) (0x2424 + (port<<10))
  634. #define MV643XX_ETH_DSCP_2(port) (0x2428 + (port<<10))
  635. #define MV643XX_ETH_DSCP_3(port) (0x242c + (port<<10))
  636. #define MV643XX_ETH_DSCP_4(port) (0x2430 + (port<<10))
  637. #define MV643XX_ETH_DSCP_5(port) (0x2434 + (port<<10))
  638. #define MV643XX_ETH_DSCP_6(port) (0x2438 + (port<<10))
  639. #define MV643XX_ETH_PORT_SERIAL_CONTROL_REG(port) (0x243c + (port<<10))
  640. #define MV643XX_ETH_VLAN_PRIORITY_TAG_TO_PRIORITY(port) (0x2440 + (port<<10))
  641. #define MV643XX_ETH_PORT_STATUS_REG(port) (0x2444 + (port<<10))
  642. #define MV643XX_ETH_TRANSMIT_QUEUE_COMMAND_REG(port) (0x2448 + (port<<10))
  643. #define MV643XX_ETH_TX_QUEUE_FIXED_PRIORITY(port) (0x244c + (port<<10))
  644. #define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_RATE_CONFIG(port) (0x2450 + (port<<10))
  645. #define MV643XX_ETH_MAXIMUM_TRANSMIT_UNIT(port) (0x2458 + (port<<10))
  646. #define MV643XX_ETH_PORT_MAXIMUM_TOKEN_BUCKET_SIZE(port) (0x245c + (port<<10))
  647. #define MV643XX_ETH_INTERRUPT_CAUSE_REG(port) (0x2460 + (port<<10))
  648. #define MV643XX_ETH_INTERRUPT_CAUSE_EXTEND_REG(port) (0x2464 + (port<<10))
  649. #define MV643XX_ETH_INTERRUPT_MASK_REG(port) (0x2468 + (port<<10))
  650. #define MV643XX_ETH_INTERRUPT_EXTEND_MASK_REG(port) (0x246c + (port<<10))
  651. #define MV643XX_ETH_RX_FIFO_URGENT_THRESHOLD_REG(port) (0x2470 + (port<<10))
  652. #define MV643XX_ETH_TX_FIFO_URGENT_THRESHOLD_REG(port) (0x2474 + (port<<10))
  653. #define MV643XX_ETH_RX_MINIMAL_FRAME_SIZE_REG(port) (0x247c + (port<<10))
  654. #define MV643XX_ETH_RX_DISCARDED_FRAMES_COUNTER(port) (0x2484 + (port<<10))
  655. #define MV643XX_ETH_PORT_DEBUG_0_REG(port) (0x248c + (port<<10))
  656. #define MV643XX_ETH_PORT_DEBUG_1_REG(port) (0x2490 + (port<<10))
  657. #define MV643XX_ETH_PORT_INTERNAL_ADDR_ERROR_REG(port) (0x2494 + (port<<10))
  658. #define MV643XX_ETH_INTERNAL_USE_REG(port) (0x24fc + (port<<10))
  659. #define MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port) (0x2680 + (port<<10))
  660. #define MV643XX_ETH_CURRENT_SERVED_TX_DESC_PTR(port) (0x2684 + (port<<10))
  661. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_0(port) (0x260c + (port<<10))
  662. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port) (0x261c + (port<<10))
  663. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port) (0x262c + (port<<10))
  664. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port) (0x263c + (port<<10))
  665. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port) (0x264c + (port<<10))
  666. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port) (0x265c + (port<<10))
  667. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port) (0x266c + (port<<10))
  668. #define MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port) (0x267c + (port<<10))
  669. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_0(port) (0x26c0 + (port<<10))
  670. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_1(port) (0x26c4 + (port<<10))
  671. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_2(port) (0x26c8 + (port<<10))
  672. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_3(port) (0x26cc + (port<<10))
  673. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_4(port) (0x26d0 + (port<<10))
  674. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_5(port) (0x26d4 + (port<<10))
  675. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_6(port) (0x26d8 + (port<<10))
  676. #define MV643XX_ETH_TX_CURRENT_QUEUE_DESC_PTR_7(port) (0x26dc + (port<<10))
  677. #define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT(port) (0x2700 + (port<<10))
  678. #define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_COUNT(port) (0x2710 + (port<<10))
  679. #define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_COUNT(port) (0x2720 + (port<<10))
  680. #define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_COUNT(port) (0x2730 + (port<<10))
  681. #define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_COUNT(port) (0x2740 + (port<<10))
  682. #define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_COUNT(port) (0x2750 + (port<<10))
  683. #define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_COUNT(port) (0x2760 + (port<<10))
  684. #define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_COUNT(port) (0x2770 + (port<<10))
  685. #define MV643XX_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG(port) (0x2704 + (port<<10))
  686. #define MV643XX_ETH_TX_QUEUE_1_TOKEN_BUCKET_CONFIG(port) (0x2714 + (port<<10))
  687. #define MV643XX_ETH_TX_QUEUE_2_TOKEN_BUCKET_CONFIG(port) (0x2724 + (port<<10))
  688. #define MV643XX_ETH_TX_QUEUE_3_TOKEN_BUCKET_CONFIG(port) (0x2734 + (port<<10))
  689. #define MV643XX_ETH_TX_QUEUE_4_TOKEN_BUCKET_CONFIG(port) (0x2744 + (port<<10))
  690. #define MV643XX_ETH_TX_QUEUE_5_TOKEN_BUCKET_CONFIG(port) (0x2754 + (port<<10))
  691. #define MV643XX_ETH_TX_QUEUE_6_TOKEN_BUCKET_CONFIG(port) (0x2764 + (port<<10))
  692. #define MV643XX_ETH_TX_QUEUE_7_TOKEN_BUCKET_CONFIG(port) (0x2774 + (port<<10))
  693. #define MV643XX_ETH_TX_QUEUE_0_ARBITER_CONFIG(port) (0x2708 + (port<<10))
  694. #define MV643XX_ETH_TX_QUEUE_1_ARBITER_CONFIG(port) (0x2718 + (port<<10))
  695. #define MV643XX_ETH_TX_QUEUE_2_ARBITER_CONFIG(port) (0x2728 + (port<<10))
  696. #define MV643XX_ETH_TX_QUEUE_3_ARBITER_CONFIG(port) (0x2738 + (port<<10))
  697. #define MV643XX_ETH_TX_QUEUE_4_ARBITER_CONFIG(port) (0x2748 + (port<<10))
  698. #define MV643XX_ETH_TX_QUEUE_5_ARBITER_CONFIG(port) (0x2758 + (port<<10))
  699. #define MV643XX_ETH_TX_QUEUE_6_ARBITER_CONFIG(port) (0x2768 + (port<<10))
  700. #define MV643XX_ETH_TX_QUEUE_7_ARBITER_CONFIG(port) (0x2778 + (port<<10))
  701. #define MV643XX_ETH_PORT_TX_TOKEN_BUCKET_COUNT(port) (0x2780 + (port<<10))
  702. #define MV643XX_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE(port) (0x3400 + (port<<10))
  703. #define MV643XX_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE(port) (0x3500 + (port<<10))
  704. #define MV643XX_ETH_DA_FILTER_UNICAST_TABLE_BASE(port) (0x3600 + (port<<10))
  705. /*******************************************/
  706. /* CUNIT Registers */
  707. /*******************************************/
  708. /* Address Decoding Register Map */
  709. #define MV64340_CUNIT_BASE_ADDR_REG0 0xf200
  710. #define MV64340_CUNIT_BASE_ADDR_REG1 0xf208
  711. #define MV64340_CUNIT_BASE_ADDR_REG2 0xf210
  712. #define MV64340_CUNIT_BASE_ADDR_REG3 0xf218
  713. #define MV64340_CUNIT_SIZE0 0xf204
  714. #define MV64340_CUNIT_SIZE1 0xf20c
  715. #define MV64340_CUNIT_SIZE2 0xf214
  716. #define MV64340_CUNIT_SIZE3 0xf21c
  717. #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG0 0xf240
  718. #define MV64340_CUNIT_HIGH_ADDR_REMAP_REG1 0xf244
  719. #define MV64340_CUNIT_BASE_ADDR_ENABLE_REG 0xf250
  720. #define MV64340_MPSC0_ACCESS_PROTECTION_REG 0xf254
  721. #define MV64340_MPSC1_ACCESS_PROTECTION_REG 0xf258
  722. #define MV64340_CUNIT_INTERNAL_SPACE_BASE_ADDR_REG 0xf25C
  723. /* Error Report Registers */
  724. #define MV64340_CUNIT_INTERRUPT_CAUSE_REG 0xf310
  725. #define MV64340_CUNIT_INTERRUPT_MASK_REG 0xf314
  726. #define MV64340_CUNIT_ERROR_ADDR 0xf318
  727. /* Cunit Control Registers */
  728. #define MV64340_CUNIT_ARBITER_CONTROL_REG 0xf300
  729. #define MV64340_CUNIT_CONFIG_REG 0xb40c
  730. #define MV64340_CUNIT_CRROSBAR_TIMEOUT_REG 0xf304
  731. /* Cunit Debug Registers */
  732. #define MV64340_CUNIT_DEBUG_LOW 0xf340
  733. #define MV64340_CUNIT_DEBUG_HIGH 0xf344
  734. #define MV64340_CUNIT_MMASK 0xf380
  735. /* MPSCs Clocks Routing Registers */
  736. #define MV64340_MPSC_ROUTING_REG 0xb400
  737. #define MV64340_MPSC_RX_CLOCK_ROUTING_REG 0xb404
  738. #define MV64340_MPSC_TX_CLOCK_ROUTING_REG 0xb408
  739. /* MPSCs Interrupts Registers */
  740. #define MV64340_MPSC_CAUSE_REG(port) (0xb804 + (port<<3))
  741. #define MV64340_MPSC_MASK_REG(port) (0xb884 + (port<<3))
  742. #define MV64340_MPSC_MAIN_CONFIG_LOW(port) (0x8000 + (port<<12))
  743. #define MV64340_MPSC_MAIN_CONFIG_HIGH(port) (0x8004 + (port<<12))
  744. #define MV64340_MPSC_PROTOCOL_CONFIG(port) (0x8008 + (port<<12))
  745. #define MV64340_MPSC_CHANNEL_REG1(port) (0x800c + (port<<12))
  746. #define MV64340_MPSC_CHANNEL_REG2(port) (0x8010 + (port<<12))
  747. #define MV64340_MPSC_CHANNEL_REG3(port) (0x8014 + (port<<12))
  748. #define MV64340_MPSC_CHANNEL_REG4(port) (0x8018 + (port<<12))
  749. #define MV64340_MPSC_CHANNEL_REG5(port) (0x801c + (port<<12))
  750. #define MV64340_MPSC_CHANNEL_REG6(port) (0x8020 + (port<<12))
  751. #define MV64340_MPSC_CHANNEL_REG7(port) (0x8024 + (port<<12))
  752. #define MV64340_MPSC_CHANNEL_REG8(port) (0x8028 + (port<<12))
  753. #define MV64340_MPSC_CHANNEL_REG9(port) (0x802c + (port<<12))
  754. #define MV64340_MPSC_CHANNEL_REG10(port) (0x8030 + (port<<12))
  755. /* MPSC0 Registers */
  756. /***************************************/
  757. /* SDMA Registers */
  758. /***************************************/
  759. #define MV64340_SDMA_CONFIG_REG(channel) (0x4000 + (channel<<13))
  760. #define MV64340_SDMA_COMMAND_REG(channel) (0x4008 + (channel<<13))
  761. #define MV64340_SDMA_CURRENT_RX_DESCRIPTOR_POINTER(channel) (0x4810 + (channel<<13))
  762. #define MV64340_SDMA_CURRENT_TX_DESCRIPTOR_POINTER(channel) (0x4c10 + (channel<<13))
  763. #define MV64340_SDMA_FIRST_TX_DESCRIPTOR_POINTER(channel) (0x4c14 + (channel<<13))
  764. #define MV64340_SDMA_CAUSE_REG 0xb800
  765. #define MV64340_SDMA_MASK_REG 0xb880
  766. /* BRG Interrupts */
  767. #define MV64340_BRG_CONFIG_REG(brg) (0xb200 + (brg<<3))
  768. #define MV64340_BRG_BAUDE_TUNING_REG(brg) (0xb208 + (brg<<3))
  769. #define MV64340_BRG_CAUSE_REG 0xb834
  770. #define MV64340_BRG_MASK_REG 0xb8b4
  771. /****************************************/
  772. /* DMA Channel Control */
  773. /****************************************/
  774. #define MV64340_DMA_CHANNEL0_CONTROL 0x840
  775. #define MV64340_DMA_CHANNEL0_CONTROL_HIGH 0x880
  776. #define MV64340_DMA_CHANNEL1_CONTROL 0x844
  777. #define MV64340_DMA_CHANNEL1_CONTROL_HIGH 0x884
  778. #define MV64340_DMA_CHANNEL2_CONTROL 0x848
  779. #define MV64340_DMA_CHANNEL2_CONTROL_HIGH 0x888
  780. #define MV64340_DMA_CHANNEL3_CONTROL 0x84C
  781. #define MV64340_DMA_CHANNEL3_CONTROL_HIGH 0x88C
  782. /****************************************/
  783. /* IDMA Registers */
  784. /****************************************/
  785. #define MV64340_DMA_CHANNEL0_BYTE_COUNT 0x800
  786. #define MV64340_DMA_CHANNEL1_BYTE_COUNT 0x804
  787. #define MV64340_DMA_CHANNEL2_BYTE_COUNT 0x808
  788. #define MV64340_DMA_CHANNEL3_BYTE_COUNT 0x80C
  789. #define MV64340_DMA_CHANNEL0_SOURCE_ADDR 0x810
  790. #define MV64340_DMA_CHANNEL1_SOURCE_ADDR 0x814
  791. #define MV64340_DMA_CHANNEL2_SOURCE_ADDR 0x818
  792. #define MV64340_DMA_CHANNEL3_SOURCE_ADDR 0x81c
  793. #define MV64340_DMA_CHANNEL0_DESTINATION_ADDR 0x820
  794. #define MV64340_DMA_CHANNEL1_DESTINATION_ADDR 0x824
  795. #define MV64340_DMA_CHANNEL2_DESTINATION_ADDR 0x828
  796. #define MV64340_DMA_CHANNEL3_DESTINATION_ADDR 0x82C
  797. #define MV64340_DMA_CHANNEL0_NEXT_DESCRIPTOR_POINTER 0x830
  798. #define MV64340_DMA_CHANNEL1_NEXT_DESCRIPTOR_POINTER 0x834
  799. #define MV64340_DMA_CHANNEL2_NEXT_DESCRIPTOR_POINTER 0x838
  800. #define MV64340_DMA_CHANNEL3_NEXT_DESCRIPTOR_POINTER 0x83C
  801. #define MV64340_DMA_CHANNEL0_CURRENT_DESCRIPTOR_POINTER 0x870
  802. #define MV64340_DMA_CHANNEL1_CURRENT_DESCRIPTOR_POINTER 0x874
  803. #define MV64340_DMA_CHANNEL2_CURRENT_DESCRIPTOR_POINTER 0x878
  804. #define MV64340_DMA_CHANNEL3_CURRENT_DESCRIPTOR_POINTER 0x87C
  805. /* IDMA Address Decoding Base Address Registers */
  806. #define MV64340_DMA_BASE_ADDR_REG0 0xa00
  807. #define MV64340_DMA_BASE_ADDR_REG1 0xa08
  808. #define MV64340_DMA_BASE_ADDR_REG2 0xa10
  809. #define MV64340_DMA_BASE_ADDR_REG3 0xa18
  810. #define MV64340_DMA_BASE_ADDR_REG4 0xa20
  811. #define MV64340_DMA_BASE_ADDR_REG5 0xa28
  812. #define MV64340_DMA_BASE_ADDR_REG6 0xa30
  813. #define MV64340_DMA_BASE_ADDR_REG7 0xa38
  814. /* IDMA Address Decoding Size Address Register */
  815. #define MV64340_DMA_SIZE_REG0 0xa04
  816. #define MV64340_DMA_SIZE_REG1 0xa0c
  817. #define MV64340_DMA_SIZE_REG2 0xa14
  818. #define MV64340_DMA_SIZE_REG3 0xa1c
  819. #define MV64340_DMA_SIZE_REG4 0xa24
  820. #define MV64340_DMA_SIZE_REG5 0xa2c
  821. #define MV64340_DMA_SIZE_REG6 0xa34
  822. #define MV64340_DMA_SIZE_REG7 0xa3C
  823. /* IDMA Address Decoding High Address Remap and Access
  824. Protection Registers */
  825. #define MV64340_DMA_HIGH_ADDR_REMAP_REG0 0xa60
  826. #define MV64340_DMA_HIGH_ADDR_REMAP_REG1 0xa64
  827. #define MV64340_DMA_HIGH_ADDR_REMAP_REG2 0xa68
  828. #define MV64340_DMA_HIGH_ADDR_REMAP_REG3 0xa6C
  829. #define MV64340_DMA_BASE_ADDR_ENABLE_REG 0xa80
  830. #define MV64340_DMA_CHANNEL0_ACCESS_PROTECTION_REG 0xa70
  831. #define MV64340_DMA_CHANNEL1_ACCESS_PROTECTION_REG 0xa74
  832. #define MV64340_DMA_CHANNEL2_ACCESS_PROTECTION_REG 0xa78
  833. #define MV64340_DMA_CHANNEL3_ACCESS_PROTECTION_REG 0xa7c
  834. #define MV64340_DMA_ARBITER_CONTROL 0x860
  835. #define MV64340_DMA_CROSS_BAR_TIMEOUT 0x8d0
  836. /* IDMA Headers Retarget Registers */
  837. #define MV64340_DMA_HEADERS_RETARGET_CONTROL 0xa84
  838. #define MV64340_DMA_HEADERS_RETARGET_BASE 0xa88
  839. /* IDMA Interrupt Register */
  840. #define MV64340_DMA_INTERRUPT_CAUSE_REG 0x8c0
  841. #define MV64340_DMA_INTERRUPT_CAUSE_MASK 0x8c4
  842. #define MV64340_DMA_ERROR_ADDR 0x8c8
  843. #define MV64340_DMA_ERROR_SELECT 0x8cc
  844. /* IDMA Debug Register ( for internal use ) */
  845. #define MV64340_DMA_DEBUG_LOW 0x8e0
  846. #define MV64340_DMA_DEBUG_HIGH 0x8e4
  847. #define MV64340_DMA_SPARE 0xA8C
  848. /****************************************/
  849. /* Timer_Counter */
  850. /****************************************/
  851. #define MV64340_TIMER_COUNTER0 0x850
  852. #define MV64340_TIMER_COUNTER1 0x854
  853. #define MV64340_TIMER_COUNTER2 0x858
  854. #define MV64340_TIMER_COUNTER3 0x85C
  855. #define MV64340_TIMER_COUNTER_0_3_CONTROL 0x864
  856. #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
  857. #define MV64340_TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
  858. /****************************************/
  859. /* Watchdog registers */
  860. /****************************************/
  861. #define MV64340_WATCHDOG_CONFIG_REG 0xb410
  862. #define MV64340_WATCHDOG_VALUE_REG 0xb414
  863. /****************************************/
  864. /* I2C Registers */
  865. /****************************************/
  866. #define MV64XXX_I2C_CTLR_NAME "mv64xxx_i2c"
  867. #define MV64XXX_I2C_OFFSET 0xc000
  868. #define MV64XXX_I2C_REG_BLOCK_SIZE 0x0020
  869. /****************************************/
  870. /* GPP Interface Registers */
  871. /****************************************/
  872. #define MV64340_GPP_IO_CONTROL 0xf100
  873. #define MV64340_GPP_LEVEL_CONTROL 0xf110
  874. #define MV64340_GPP_VALUE 0xf104
  875. #define MV64340_GPP_INTERRUPT_CAUSE 0xf108
  876. #define MV64340_GPP_INTERRUPT_MASK0 0xf10c
  877. #define MV64340_GPP_INTERRUPT_MASK1 0xf114
  878. #define MV64340_GPP_VALUE_SET 0xf118
  879. #define MV64340_GPP_VALUE_CLEAR 0xf11c
  880. /****************************************/
  881. /* Interrupt Controller Registers */
  882. /****************************************/
  883. /****************************************/
  884. /* Interrupts */
  885. /****************************************/
  886. #define MV64340_MAIN_INTERRUPT_CAUSE_LOW 0x004
  887. #define MV64340_MAIN_INTERRUPT_CAUSE_HIGH 0x00c
  888. #define MV64340_CPU_INTERRUPT0_MASK_LOW 0x014
  889. #define MV64340_CPU_INTERRUPT0_MASK_HIGH 0x01c
  890. #define MV64340_CPU_INTERRUPT0_SELECT_CAUSE 0x024
  891. #define MV64340_CPU_INTERRUPT1_MASK_LOW 0x034
  892. #define MV64340_CPU_INTERRUPT1_MASK_HIGH 0x03c
  893. #define MV64340_CPU_INTERRUPT1_SELECT_CAUSE 0x044
  894. #define MV64340_INTERRUPT0_MASK_0_LOW 0x054
  895. #define MV64340_INTERRUPT0_MASK_0_HIGH 0x05c
  896. #define MV64340_INTERRUPT0_SELECT_CAUSE 0x064
  897. #define MV64340_INTERRUPT1_MASK_0_LOW 0x074
  898. #define MV64340_INTERRUPT1_MASK_0_HIGH 0x07c
  899. #define MV64340_INTERRUPT1_SELECT_CAUSE 0x084
  900. /****************************************/
  901. /* MPP Interface Registers */
  902. /****************************************/
  903. #define MV64340_MPP_CONTROL0 0xf000
  904. #define MV64340_MPP_CONTROL1 0xf004
  905. #define MV64340_MPP_CONTROL2 0xf008
  906. #define MV64340_MPP_CONTROL3 0xf00c
  907. /****************************************/
  908. /* Serial Initialization registers */
  909. /****************************************/
  910. #define MV64340_SERIAL_INIT_LAST_DATA 0xf324
  911. #define MV64340_SERIAL_INIT_CONTROL 0xf328
  912. #define MV64340_SERIAL_INIT_STATUS 0xf32c
  913. extern void mv64340_irq_init(unsigned int base);
  914. /* MPSC Platform Device, Driver Data (Shared register regions) */
  915. #define MPSC_SHARED_NAME "mpsc_shared"
  916. #define MPSC_ROUTING_BASE_ORDER 0
  917. #define MPSC_SDMA_INTR_BASE_ORDER 1
  918. #define MPSC_ROUTING_REG_BLOCK_SIZE 0x000c
  919. #define MPSC_SDMA_INTR_REG_BLOCK_SIZE 0x0084
  920. struct mpsc_shared_pdata {
  921. u32 mrr_val;
  922. u32 rcrr_val;
  923. u32 tcrr_val;
  924. u32 intr_cause_val;
  925. u32 intr_mask_val;
  926. };
  927. /* MPSC Platform Device, Driver Data */
  928. #define MPSC_CTLR_NAME "mpsc"
  929. #define MPSC_BASE_ORDER 0
  930. #define MPSC_SDMA_BASE_ORDER 1
  931. #define MPSC_BRG_BASE_ORDER 2
  932. #define MPSC_REG_BLOCK_SIZE 0x0038
  933. #define MPSC_SDMA_REG_BLOCK_SIZE 0x0c18
  934. #define MPSC_BRG_REG_BLOCK_SIZE 0x0008
  935. struct mpsc_pdata {
  936. u8 mirror_regs;
  937. u8 cache_mgmt;
  938. u8 max_idle;
  939. int default_baud;
  940. int default_bits;
  941. int default_parity;
  942. int default_flow;
  943. u32 chr_1_val;
  944. u32 chr_2_val;
  945. u32 chr_10_val;
  946. u32 mpcr_val;
  947. u32 bcr_val;
  948. u8 brg_can_tune;
  949. u8 brg_clk_src;
  950. u32 brg_clk_freq;
  951. };
  952. /* i2c Platform Device, Driver Data */
  953. struct mv64xxx_i2c_pdata {
  954. u32 freq_m;
  955. u32 freq_n;
  956. u32 timeout; /* In milliseconds */
  957. u32 retries;
  958. };
  959. /* These macros describe Ethernet Port configuration reg (Px_cR) bits */
  960. #define MV643XX_ETH_UNICAST_NORMAL_MODE 0
  961. #define MV643XX_ETH_UNICAST_PROMISCUOUS_MODE (1<<0)
  962. #define MV643XX_ETH_DEFAULT_RX_QUEUE_0 0
  963. #define MV643XX_ETH_DEFAULT_RX_QUEUE_1 (1<<1)
  964. #define MV643XX_ETH_DEFAULT_RX_QUEUE_2 (1<<2)
  965. #define MV643XX_ETH_DEFAULT_RX_QUEUE_3 ((1<<2) | (1<<1))
  966. #define MV643XX_ETH_DEFAULT_RX_QUEUE_4 (1<<3)
  967. #define MV643XX_ETH_DEFAULT_RX_QUEUE_5 ((1<<3) | (1<<1))
  968. #define MV643XX_ETH_DEFAULT_RX_QUEUE_6 ((1<<3) | (1<<2))
  969. #define MV643XX_ETH_DEFAULT_RX_QUEUE_7 ((1<<3) | (1<<2) | (1<<1))
  970. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 0
  971. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_1 (1<<4)
  972. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_2 (1<<5)
  973. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_3 ((1<<5) | (1<<4))
  974. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_4 (1<<6)
  975. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_5 ((1<<6) | (1<<4))
  976. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_6 ((1<<6) | (1<<5))
  977. #define MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_7 ((1<<6) | (1<<5) | (1<<4))
  978. #define MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP 0
  979. #define MV643XX_ETH_REJECT_BC_IF_NOT_IP_OR_ARP (1<<7)
  980. #define MV643XX_ETH_RECEIVE_BC_IF_IP 0
  981. #define MV643XX_ETH_REJECT_BC_IF_IP (1<<8)
  982. #define MV643XX_ETH_RECEIVE_BC_IF_ARP 0
  983. #define MV643XX_ETH_REJECT_BC_IF_ARP (1<<9)
  984. #define MV643XX_ETH_TX_AM_NO_UPDATE_ERROR_SUMMARY (1<<12)
  985. #define MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS 0
  986. #define MV643XX_ETH_CAPTURE_TCP_FRAMES_EN (1<<14)
  987. #define MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS 0
  988. #define MV643XX_ETH_CAPTURE_UDP_FRAMES_EN (1<<15)
  989. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 0
  990. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_1 (1<<16)
  991. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_2 (1<<17)
  992. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_3 ((1<<17) | (1<<16))
  993. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_4 (1<<18)
  994. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_5 ((1<<18) | (1<<16))
  995. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_6 ((1<<18) | (1<<17))
  996. #define MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_7 ((1<<18) | (1<<17) | (1<<16))
  997. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 0
  998. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_1 (1<<19)
  999. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_2 (1<<20)
  1000. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_3 ((1<<20) | (1<<19))
  1001. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_4 (1<<21)
  1002. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_5 ((1<<21) | (1<<19))
  1003. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_6 ((1<<21) | (1<<20))
  1004. #define MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_7 ((1<<21) | (1<<20) | (1<<19))
  1005. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0 0
  1006. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_1 (1<<22)
  1007. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_2 (1<<23)
  1008. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_3 ((1<<23) | (1<<22))
  1009. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_4 (1<<24)
  1010. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_5 ((1<<24) | (1<<22))
  1011. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_6 ((1<<24) | (1<<23))
  1012. #define MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_7 ((1<<24) | (1<<23) | (1<<22))
  1013. #define MV643XX_ETH_PORT_CONFIG_DEFAULT_VALUE \
  1014. MV643XX_ETH_UNICAST_NORMAL_MODE | \
  1015. MV643XX_ETH_DEFAULT_RX_QUEUE_0 | \
  1016. MV643XX_ETH_DEFAULT_RX_ARP_QUEUE_0 | \
  1017. MV643XX_ETH_RECEIVE_BC_IF_NOT_IP_OR_ARP | \
  1018. MV643XX_ETH_RECEIVE_BC_IF_IP | \
  1019. MV643XX_ETH_RECEIVE_BC_IF_ARP | \
  1020. MV643XX_ETH_CAPTURE_TCP_FRAMES_DIS | \
  1021. MV643XX_ETH_CAPTURE_UDP_FRAMES_DIS | \
  1022. MV643XX_ETH_DEFAULT_RX_TCP_QUEUE_0 | \
  1023. MV643XX_ETH_DEFAULT_RX_UDP_QUEUE_0 | \
  1024. MV643XX_ETH_DEFAULT_RX_BPDU_QUEUE_0
  1025. /* These macros describe Ethernet Port configuration extend reg (Px_cXR) bits*/
  1026. #define MV643XX_ETH_CLASSIFY_EN (1<<0)
  1027. #define MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL 0
  1028. #define MV643XX_ETH_SPAN_BPDU_PACKETS_TO_RX_QUEUE_7 (1<<1)
  1029. #define MV643XX_ETH_PARTITION_DISABLE 0
  1030. #define MV643XX_ETH_PARTITION_ENABLE (1<<2)
  1031. #define MV643XX_ETH_PORT_CONFIG_EXTEND_DEFAULT_VALUE \
  1032. MV643XX_ETH_SPAN_BPDU_PACKETS_AS_NORMAL | \
  1033. MV643XX_ETH_PARTITION_DISABLE
  1034. /* These macros describe Ethernet Port Sdma configuration reg (SDCR) bits */
  1035. #define MV643XX_ETH_RIFB (1<<0)
  1036. #define MV643XX_ETH_RX_BURST_SIZE_1_64BIT 0
  1037. #define MV643XX_ETH_RX_BURST_SIZE_2_64BIT (1<<1)
  1038. #define MV643XX_ETH_RX_BURST_SIZE_4_64BIT (1<<2)
  1039. #define MV643XX_ETH_RX_BURST_SIZE_8_64BIT ((1<<2) | (1<<1))
  1040. #define MV643XX_ETH_RX_BURST_SIZE_16_64BIT (1<<3)
  1041. #define MV643XX_ETH_BLM_RX_NO_SWAP (1<<4)
  1042. #define MV643XX_ETH_BLM_RX_BYTE_SWAP 0
  1043. #define MV643XX_ETH_BLM_TX_NO_SWAP (1<<5)
  1044. #define MV643XX_ETH_BLM_TX_BYTE_SWAP 0
  1045. #define MV643XX_ETH_DESCRIPTORS_BYTE_SWAP (1<<6)
  1046. #define MV643XX_ETH_DESCRIPTORS_NO_SWAP 0
  1047. #define MV643XX_ETH_TX_BURST_SIZE_1_64BIT 0
  1048. #define MV643XX_ETH_TX_BURST_SIZE_2_64BIT (1<<22)
  1049. #define MV643XX_ETH_TX_BURST_SIZE_4_64BIT (1<<23)
  1050. #define MV643XX_ETH_TX_BURST_SIZE_8_64BIT ((1<<23) | (1<<22))
  1051. #define MV643XX_ETH_TX_BURST_SIZE_16_64BIT (1<<24)
  1052. #define MV643XX_ETH_IPG_INT_RX(value) ((value & 0x3fff) << 8)
  1053. #define MV643XX_ETH_PORT_SDMA_CONFIG_DEFAULT_VALUE \
  1054. MV643XX_ETH_RX_BURST_SIZE_4_64BIT | \
  1055. MV643XX_ETH_IPG_INT_RX(0) | \
  1056. MV643XX_ETH_TX_BURST_SIZE_4_64BIT
  1057. /* These macros describe Ethernet Port serial control reg (PSCR) bits */
  1058. #define MV643XX_ETH_SERIAL_PORT_DISABLE 0
  1059. #define MV643XX_ETH_SERIAL_PORT_ENABLE (1<<0)
  1060. #define MV643XX_ETH_FORCE_LINK_PASS (1<<1)
  1061. #define MV643XX_ETH_DO_NOT_FORCE_LINK_PASS 0
  1062. #define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX 0
  1063. #define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_DUPLX (1<<2)
  1064. #define MV643XX_ETH_ENABLE_AUTO_NEG_FOR_FLOW_CTRL 0
  1065. #define MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1<<3)
  1066. #define MV643XX_ETH_ADV_NO_FLOW_CTRL 0
  1067. #define MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL (1<<4)
  1068. #define MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX 0
  1069. #define MV643XX_ETH_FORCE_FC_MODE_TX_PAUSE_DIS (1<<5)
  1070. #define MV643XX_ETH_FORCE_BP_MODE_NO_JAM 0
  1071. #define MV643XX_ETH_FORCE_BP_MODE_JAM_TX (1<<7)
  1072. #define MV643XX_ETH_FORCE_BP_MODE_JAM_TX_ON_RX_ERR (1<<8)
  1073. #define MV643XX_ETH_SERIAL_PORT_CONTROL_RESERVED (1<<9)
  1074. #define MV643XX_ETH_FORCE_LINK_FAIL 0
  1075. #define MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL (1<<10)
  1076. #define MV643XX_ETH_RETRANSMIT_16_ATTEMPTS 0
  1077. #define MV643XX_ETH_RETRANSMIT_FOREVER (1<<11)
  1078. #define MV643XX_ETH_DISABLE_AUTO_NEG_SPEED_GMII (1<<13)
  1079. #define MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII 0
  1080. #define MV643XX_ETH_DTE_ADV_0 0
  1081. #define MV643XX_ETH_DTE_ADV_1 (1<<14)
  1082. #define MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS 0
  1083. #define MV643XX_ETH_ENABLE_AUTO_NEG_BYPASS (1<<15)
  1084. #define MV643XX_ETH_AUTO_NEG_NO_CHANGE 0
  1085. #define MV643XX_ETH_RESTART_AUTO_NEG (1<<16)
  1086. #define MV643XX_ETH_MAX_RX_PACKET_1518BYTE 0
  1087. #define MV643XX_ETH_MAX_RX_PACKET_1522BYTE (1<<17)
  1088. #define MV643XX_ETH_MAX_RX_PACKET_1552BYTE (1<<18)
  1089. #define MV643XX_ETH_MAX_RX_PACKET_9022BYTE ((1<<18) | (1<<17))
  1090. #define MV643XX_ETH_MAX_RX_PACKET_9192BYTE (1<<19)
  1091. #define MV643XX_ETH_MAX_RX_PACKET_9700BYTE ((1<<19) | (1<<17))
  1092. #define MV643XX_ETH_SET_EXT_LOOPBACK (1<<20)
  1093. #define MV643XX_ETH_CLR_EXT_LOOPBACK 0
  1094. #define MV643XX_ETH_SET_FULL_DUPLEX_MODE (1<<21)
  1095. #define MV643XX_ETH_SET_HALF_DUPLEX_MODE 0
  1096. #define MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX (1<<22)
  1097. #define MV643XX_ETH_DISABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX 0
  1098. #define MV643XX_ETH_SET_GMII_SPEED_TO_10_100 0
  1099. #define MV643XX_ETH_SET_GMII_SPEED_TO_1000 (1<<23)
  1100. #define MV643XX_ETH_SET_MII_SPEED_TO_10 0
  1101. #define MV643XX_ETH_SET_MII_SPEED_TO_100 (1<<24)
  1102. #define MV643XX_ETH_MAX_RX_PACKET_MASK (0x7<<17)
  1103. #define MV643XX_ETH_PORT_SERIAL_CONTROL_DEFAULT_VALUE \
  1104. MV643XX_ETH_DO_NOT_FORCE_LINK_PASS | \
  1105. MV643XX_ETH_ENABLE_AUTO_NEG_FOR_DUPLX | \
  1106. MV643XX_ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL | \
  1107. MV643XX_ETH_ADV_SYMMETRIC_FLOW_CTRL | \
  1108. MV643XX_ETH_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
  1109. MV643XX_ETH_FORCE_BP_MODE_NO_JAM | \
  1110. (1<<9) /* reserved */ | \
  1111. MV643XX_ETH_DO_NOT_FORCE_LINK_FAIL | \
  1112. MV643XX_ETH_RETRANSMIT_16_ATTEMPTS | \
  1113. MV643XX_ETH_ENABLE_AUTO_NEG_SPEED_GMII | \
  1114. MV643XX_ETH_DTE_ADV_0 | \
  1115. MV643XX_ETH_DISABLE_AUTO_NEG_BYPASS | \
  1116. MV643XX_ETH_AUTO_NEG_NO_CHANGE | \
  1117. MV643XX_ETH_MAX_RX_PACKET_9700BYTE | \
  1118. MV643XX_ETH_CLR_EXT_LOOPBACK | \
  1119. MV643XX_ETH_SET_FULL_DUPLEX_MODE | \
  1120. MV643XX_ETH_ENABLE_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX
  1121. /* These macros describe Ethernet Serial Status reg (PSR) bits */
  1122. #define MV643XX_ETH_PORT_STATUS_MODE_10_BIT (1<<0)
  1123. #define MV643XX_ETH_PORT_STATUS_LINK_UP (1<<1)
  1124. #define MV643XX_ETH_PORT_STATUS_FULL_DUPLEX (1<<2)
  1125. #define MV643XX_ETH_PORT_STATUS_FLOW_CONTROL (1<<3)
  1126. #define MV643XX_ETH_PORT_STATUS_GMII_1000 (1<<4)
  1127. #define MV643XX_ETH_PORT_STATUS_MII_100 (1<<5)
  1128. /* PSR bit 6 is undocumented */
  1129. #define MV643XX_ETH_PORT_STATUS_TX_IN_PROGRESS (1<<7)
  1130. #define MV643XX_ETH_PORT_STATUS_AUTONEG_BYPASSED (1<<8)
  1131. #define MV643XX_ETH_PORT_STATUS_PARTITION (1<<9)
  1132. #define MV643XX_ETH_PORT_STATUS_TX_FIFO_EMPTY (1<<10)
  1133. /* PSR bits 11-31 are reserved */
  1134. #define MV643XX_ETH_PORT_DEFAULT_TRANSMIT_QUEUE_SIZE 800
  1135. #define MV643XX_ETH_PORT_DEFAULT_RECEIVE_QUEUE_SIZE 400
  1136. #define MV643XX_ETH_DESC_SIZE 64
  1137. #define MV643XX_ETH_SHARED_NAME "mv643xx_eth_shared"
  1138. #define MV643XX_ETH_NAME "mv643xx_eth"
  1139. struct mv643xx_eth_platform_data {
  1140. int port_number;
  1141. u16 force_phy_addr; /* force override if phy_addr == 0 */
  1142. u16 phy_addr;
  1143. /* If speed is 0, then speed and duplex are autonegotiated. */
  1144. int speed; /* 0, SPEED_10, SPEED_100, SPEED_1000 */
  1145. int duplex; /* DUPLEX_HALF or DUPLEX_FULL */
  1146. /* non-zero values of the following fields override defaults */
  1147. u32 tx_queue_size;
  1148. u32 rx_queue_size;
  1149. u32 tx_sram_addr;
  1150. u32 tx_sram_size;
  1151. u32 rx_sram_addr;
  1152. u32 rx_sram_size;
  1153. u8 mac_addr[6]; /* mac address if non-zero*/
  1154. };
  1155. #endif /* __ASM_MV643XX_H */