nand.h 21 KB

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  1. /*
  2. * linux/include/linux/mtd/nand.h
  3. *
  4. * Copyright (c) 2000 David Woodhouse <dwmw2@mvhi.com>
  5. * Steven J. Hill <sjhill@realitydiluted.com>
  6. * Thomas Gleixner <tglx@linutronix.de>
  7. *
  8. * $Id: nand.h,v 1.1.1.1 2007/06/12 07:27:16 eyryu Exp $
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. *
  14. * Info:
  15. * Contains standard defines and IDs for NAND flash devices
  16. *
  17. * Changelog:
  18. * See git changelog.
  19. */
  20. #ifndef __LINUX_MTD_NAND_H
  21. #define __LINUX_MTD_NAND_H
  22. #include <linux/wait.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/mtd/mtd.h>
  25. struct mtd_info;
  26. /* Scan and identify a NAND device */
  27. extern int nand_scan (struct mtd_info *mtd, int max_chips);
  28. /* Separate phases of nand_scan(), allowing board driver to intervene
  29. * and override command or ECC setup according to flash type */
  30. extern int nand_scan_ident(struct mtd_info *mtd, int max_chips);
  31. extern int nand_scan_tail(struct mtd_info *mtd);
  32. /* Free resources held by the NAND device */
  33. extern void nand_release (struct mtd_info *mtd);
  34. /* Internal helper for board drivers which need to override command function */
  35. extern void nand_wait_ready(struct mtd_info *mtd);
  36. /* The maximum number of NAND chips in an array */
  37. #define NAND_MAX_CHIPS 8
  38. /* This constant declares the max. oobsize / page, which
  39. * is supported now. If you add a chip with bigger oobsize/page
  40. * adjust this accordingly.
  41. */
  42. #define NAND_MAX_OOBSIZE 64
  43. #define NAND_MAX_PAGESIZE 2048
  44. /*
  45. * Constants for hardware specific CLE/ALE/NCE function
  46. *
  47. * These are bits which can be or'ed to set/clear multiple
  48. * bits in one go.
  49. */
  50. /* Select the chip by setting nCE to low */
  51. #define NAND_NCE 0x01
  52. /* Select the command latch by setting CLE to high */
  53. #define NAND_CLE 0x02
  54. /* Select the address latch by setting ALE to high */
  55. #define NAND_ALE 0x04
  56. #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
  57. #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
  58. #define NAND_CTRL_CHANGE 0x80
  59. /*
  60. * Standard NAND flash commands
  61. */
  62. #define NAND_CMD_READ0 0
  63. #define NAND_CMD_READ1 1
  64. #define NAND_CMD_RNDOUT 5
  65. #define NAND_CMD_PAGEPROG 0x10
  66. #define NAND_CMD_READOOB 0x50
  67. #define NAND_CMD_ERASE1 0x60
  68. #define NAND_CMD_STATUS 0x70
  69. #define NAND_CMD_STATUS_MULTI 0x71
  70. #define NAND_CMD_SEQIN 0x80
  71. #define NAND_CMD_RNDIN 0x85
  72. #define NAND_CMD_READID 0x90
  73. #define NAND_CMD_ERASE2 0xd0
  74. #define NAND_CMD_RESET 0xff
  75. /* Extended commands for large page devices */
  76. #define NAND_CMD_READSTART 0x30
  77. #define NAND_CMD_RNDOUTSTART 0xE0
  78. #define NAND_CMD_CACHEDPROG 0x15
  79. /* Extended commands for AG-AND device */
  80. /*
  81. * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
  82. * there is no way to distinguish that from NAND_CMD_READ0
  83. * until the remaining sequence of commands has been completed
  84. * so add a high order bit and mask it off in the command.
  85. */
  86. #define NAND_CMD_DEPLETE1 0x100
  87. #define NAND_CMD_DEPLETE2 0x38
  88. #define NAND_CMD_STATUS_MULTI 0x71
  89. #define NAND_CMD_STATUS_ERROR 0x72
  90. /* multi-bank error status (banks 0-3) */
  91. #define NAND_CMD_STATUS_ERROR0 0x73
  92. #define NAND_CMD_STATUS_ERROR1 0x74
  93. #define NAND_CMD_STATUS_ERROR2 0x75
  94. #define NAND_CMD_STATUS_ERROR3 0x76
  95. #define NAND_CMD_STATUS_RESET 0x7f
  96. #define NAND_CMD_STATUS_CLEAR 0xff
  97. #define NAND_CMD_NONE -1
  98. /* Status bits */
  99. #define NAND_STATUS_FAIL 0x01
  100. #define NAND_STATUS_FAIL_N1 0x02
  101. #define NAND_STATUS_TRUE_READY 0x20
  102. #define NAND_STATUS_READY 0x40
  103. #define NAND_STATUS_WP 0x80
  104. /*
  105. * Constants for ECC_MODES
  106. */
  107. typedef enum {
  108. NAND_ECC_NONE,
  109. NAND_ECC_SOFT,
  110. NAND_ECC_HW,
  111. NAND_ECC_HW_SYNDROME,
  112. } nand_ecc_modes_t;
  113. /*
  114. * Constants for Hardware ECC
  115. */
  116. /* Reset Hardware ECC for read */
  117. #define NAND_ECC_READ 0
  118. /* Reset Hardware ECC for write */
  119. #define NAND_ECC_WRITE 1
  120. /* Enable Hardware ECC before syndrom is read back from flash */
  121. #define NAND_ECC_READSYN 2
  122. /* Bit mask for flags passed to do_nand_read_ecc */
  123. #define NAND_GET_DEVICE 0x80
  124. /* Option constants for bizarre disfunctionality and real
  125. * features
  126. */
  127. /* Chip can not auto increment pages */
  128. #define NAND_NO_AUTOINCR 0x00000001
  129. /* Buswitdh is 16 bit */
  130. #define NAND_BUSWIDTH_16 0x00000002
  131. /* Device supports partial programming without padding */
  132. #define NAND_NO_PADDING 0x00000004
  133. /* Chip has cache program function */
  134. #define NAND_CACHEPRG 0x00000008
  135. /* Chip has copy back function */
  136. #define NAND_COPYBACK 0x00000010
  137. /* AND Chip which has 4 banks and a confusing page / block
  138. * assignment. See Renesas datasheet for further information */
  139. #define NAND_IS_AND 0x00000020
  140. /* Chip has a array of 4 pages which can be read without
  141. * additional ready /busy waits */
  142. #define NAND_4PAGE_ARRAY 0x00000040
  143. /* Chip requires that BBT is periodically rewritten to prevent
  144. * bits from adjacent blocks from 'leaking' in altering data.
  145. * This happens with the Renesas AG-AND chips, possibly others. */
  146. #define BBT_AUTO_REFRESH 0x00000080
  147. /* Chip does not require ready check on read. True
  148. * for all large page devices, as they do not support
  149. * autoincrement.*/
  150. #define NAND_NO_READRDY 0x00000100
  151. /* Chip does not allow subpage writes */
  152. #define NAND_NO_SUBPAGE_WRITE 0x00000200
  153. /* Options valid for Samsung large page devices */
  154. #define NAND_SAMSUNG_LP_OPTIONS \
  155. (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
  156. /* Macros to identify the above */
  157. #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
  158. #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
  159. #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
  160. #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
  161. /* Mask to zero out the chip options, which come from the id table */
  162. #define NAND_CHIPOPTIONS_MSK (0x0000ffff & ~NAND_NO_AUTOINCR)
  163. /* Non chip related options */
  164. /* Use a flash based bad block table. This option is passed to the
  165. * default bad block table function. */
  166. #define NAND_USE_FLASH_BBT 0x00010000
  167. /* This option skips the bbt scan during initialization. */
  168. #define NAND_SKIP_BBTSCAN 0x00020000
  169. /* This option is defined if the board driver allocates its own buffers
  170. (e.g. because it needs them DMA-coherent */
  171. #define NAND_OWN_BUFFERS 0x00040000
  172. /* Options set by nand scan */
  173. /* Nand scan has allocated controller struct */
  174. #define NAND_CONTROLLER_ALLOC 0x80000000
  175. /* Cell info constants */
  176. #define NAND_CI_CHIPNR_MSK 0x03
  177. #define NAND_CI_CELLTYPE_MSK 0x0C
  178. /*
  179. * nand_state_t - chip states
  180. * Enumeration for NAND flash chip state
  181. */
  182. typedef enum {
  183. FL_READY,
  184. FL_READING,
  185. FL_WRITING,
  186. FL_ERASING,
  187. FL_SYNCING,
  188. FL_CACHEDPRG,
  189. FL_PM_SUSPENDED,
  190. } nand_state_t;
  191. /* Keep gcc happy */
  192. struct nand_chip;
  193. /**
  194. * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
  195. * @lock: protection lock
  196. * @active: the mtd device which holds the controller currently
  197. * @wq: wait queue to sleep on if a NAND operation is in progress
  198. * used instead of the per chip wait queue when a hw controller is available
  199. */
  200. struct nand_hw_control {
  201. spinlock_t lock;
  202. struct nand_chip *active;
  203. wait_queue_head_t wq;
  204. };
  205. /**
  206. * struct nand_ecc_ctrl - Control structure for ecc
  207. * @mode: ecc mode
  208. * @steps: number of ecc steps per page
  209. * @size: data bytes per ecc step
  210. * @bytes: ecc bytes per step
  211. * @total: total number of ecc bytes per page
  212. * @prepad: padding information for syndrome based ecc generators
  213. * @postpad: padding information for syndrome based ecc generators
  214. * @layout: ECC layout control struct pointer
  215. * @hwctl: function to control hardware ecc generator. Must only
  216. * be provided if an hardware ECC is available
  217. * @calculate: function for ecc calculation or readback from ecc hardware
  218. * @correct: function for ecc correction, matching to ecc generator (sw/hw)
  219. * @read_page_raw: function to read a raw page without ECC
  220. * @write_page_raw: function to write a raw page without ECC
  221. * @read_page: function to read a page according to the ecc generator requirements
  222. * @write_page: function to write a page according to the ecc generator requirements
  223. * @read_oob: function to read chip OOB data
  224. * @write_oob: function to write chip OOB data
  225. */
  226. struct nand_ecc_ctrl {
  227. nand_ecc_modes_t mode;
  228. int steps;
  229. int size;
  230. int bytes;
  231. int total;
  232. int prepad;
  233. int postpad;
  234. struct nand_ecclayout *layout;
  235. void (*hwctl)(struct mtd_info *mtd, int mode);
  236. int (*calculate)(struct mtd_info *mtd,
  237. const uint8_t *dat,
  238. uint8_t *ecc_code);
  239. int (*correct)(struct mtd_info *mtd, uint8_t *dat,
  240. uint8_t *read_ecc,
  241. uint8_t *calc_ecc);
  242. int (*read_page_raw)(struct mtd_info *mtd,
  243. struct nand_chip *chip,
  244. uint8_t *buf);
  245. void (*write_page_raw)(struct mtd_info *mtd,
  246. struct nand_chip *chip,
  247. const uint8_t *buf);
  248. int (*read_page)(struct mtd_info *mtd,
  249. struct nand_chip *chip,
  250. uint8_t *buf);
  251. void (*write_page)(struct mtd_info *mtd,
  252. struct nand_chip *chip,
  253. const uint8_t *buf);
  254. int (*read_oob)(struct mtd_info *mtd,
  255. struct nand_chip *chip,
  256. int page,
  257. int sndcmd);
  258. int (*write_oob)(struct mtd_info *mtd,
  259. struct nand_chip *chip,
  260. int page);
  261. };
  262. /**
  263. * struct nand_buffers - buffer structure for read/write
  264. * @ecccalc: buffer for calculated ecc
  265. * @ecccode: buffer for ecc read from flash
  266. * @databuf: buffer for data - dynamically sized
  267. *
  268. * Do not change the order of buffers. databuf and oobrbuf must be in
  269. * consecutive order.
  270. */
  271. struct nand_buffers {
  272. uint8_t ecccalc[NAND_MAX_OOBSIZE];
  273. uint8_t ecccode[NAND_MAX_OOBSIZE];
  274. uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
  275. };
  276. /**
  277. * struct nand_chip - NAND Private Flash Chip Data
  278. * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the flash device
  279. * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the flash device
  280. * @read_byte: [REPLACEABLE] read one byte from the chip
  281. * @read_word: [REPLACEABLE] read one word from the chip
  282. * @write_buf: [REPLACEABLE] write data from the buffer to the chip
  283. * @read_buf: [REPLACEABLE] read data from the chip into the buffer
  284. * @verify_buf: [REPLACEABLE] verify buffer contents against the chip data
  285. * @select_chip: [REPLACEABLE] select chip nr
  286. * @block_bad: [REPLACEABLE] check, if the block is bad
  287. * @block_markbad: [REPLACEABLE] mark the block bad
  288. * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific funtion for controlling
  289. * ALE/CLE/nCE. Also used to write command and address
  290. * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accesing device ready/busy line
  291. * If set to NULL no access to ready/busy is available and the ready/busy information
  292. * is read from the chip status register
  293. * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing commands to the chip
  294. * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on ready
  295. * @ecc: [BOARDSPECIFIC] ecc control ctructure
  296. * @buffers: buffer structure for read/write
  297. * @hwcontrol: platform-specific hardware control structure
  298. * @ops: oob operation operands
  299. * @erase_cmd: [INTERN] erase command write function, selectable due to AND support
  300. * @scan_bbt: [REPLACEABLE] function to scan bad block table
  301. * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transfering data from array to read regs (tR)
  302. * @wq: [INTERN] wait queue to sleep on if a NAND operation is in progress
  303. * @state: [INTERN] the current state of the NAND device
  304. * @oob_poi: poison value buffer
  305. * @page_shift: [INTERN] number of address bits in a page (column address bits)
  306. * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
  307. * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
  308. * @chip_shift: [INTERN] number of address bits in one chip
  309. * @datbuf: [INTERN] internal buffer for one page + oob
  310. * @oobbuf: [INTERN] oob buffer for one eraseblock
  311. * @oobdirty: [INTERN] indicates that oob_buf must be reinitialized
  312. * @data_poi: [INTERN] pointer to a data buffer
  313. * @options: [BOARDSPECIFIC] various chip options. They can partly be set to inform nand_scan about
  314. * special functionality. See the defines for further explanation
  315. * @badblockpos: [INTERN] position of the bad block marker in the oob area
  316. * @cellinfo: [INTERN] MLC/multichip data from chip ident
  317. * @numchips: [INTERN] number of physical chips
  318. * @chipsize: [INTERN] the size of one chip for multichip arrays
  319. * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
  320. * @pagebuf: [INTERN] holds the pagenumber which is currently in data_buf
  321. * @subpagesize: [INTERN] holds the subpagesize
  322. * @ecclayout: [REPLACEABLE] the default ecc placement scheme
  323. * @bbt: [INTERN] bad block table pointer
  324. * @bbt_td: [REPLACEABLE] bad block table descriptor for flash lookup
  325. * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
  326. * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial bad block scan
  327. * @controller: [REPLACEABLE] a pointer to a hardware controller structure
  328. * which is shared among multiple independend devices
  329. * @priv: [OPTIONAL] pointer to private chip date
  330. * @errstat: [OPTIONAL] hardware specific function to perform additional error status checks
  331. * (determine if errors are correctable)
  332. * @write_page: [REPLACEABLE] High-level page write function
  333. */
  334. struct nand_chip {
  335. void __iomem *IO_ADDR_R;
  336. void __iomem *IO_ADDR_W;
  337. uint8_t (*read_byte)(struct mtd_info *mtd);
  338. u16 (*read_word)(struct mtd_info *mtd);
  339. void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  340. void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
  341. int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
  342. void (*select_chip)(struct mtd_info *mtd, int chip);
  343. int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
  344. int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
  345. void (*cmd_ctrl)(struct mtd_info *mtd, int dat,
  346. unsigned int ctrl);
  347. int (*dev_ready)(struct mtd_info *mtd);
  348. void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column, int page_addr);
  349. int (*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
  350. void (*erase_cmd)(struct mtd_info *mtd, int page);
  351. int (*scan_bbt)(struct mtd_info *mtd);
  352. int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page);
  353. int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
  354. const uint8_t *buf, int page, int cached, int raw);
  355. int chip_delay;
  356. unsigned int options;
  357. int page_shift;
  358. int phys_erase_shift;
  359. int bbt_erase_shift;
  360. int chip_shift;
  361. int numchips;
  362. unsigned long chipsize;
  363. int pagemask;
  364. int pagebuf;
  365. int subpagesize;
  366. uint8_t cellinfo;
  367. int badblockpos;
  368. nand_state_t state;
  369. uint8_t *oob_poi;
  370. struct nand_hw_control *controller;
  371. struct nand_ecclayout *ecclayout;
  372. struct nand_ecc_ctrl ecc;
  373. struct nand_buffers *buffers;
  374. struct nand_hw_control hwcontrol;
  375. struct mtd_oob_ops ops;
  376. uint8_t *bbt;
  377. struct nand_bbt_descr *bbt_td;
  378. struct nand_bbt_descr *bbt_md;
  379. struct nand_bbt_descr *badblock_pattern;
  380. void *priv;
  381. };
  382. /*
  383. * NAND Flash Manufacturer ID Codes
  384. */
  385. #define NAND_MFR_TOSHIBA 0x98
  386. #define NAND_MFR_SAMSUNG 0xec
  387. #define NAND_MFR_FUJITSU 0x04
  388. #define NAND_MFR_NATIONAL 0x8f
  389. #define NAND_MFR_RENESAS 0x07
  390. #define NAND_MFR_STMICRO 0x20
  391. #define NAND_MFR_HYNIX 0xad
  392. /**
  393. * struct nand_flash_dev - NAND Flash Device ID Structure
  394. * @name: Identify the device type
  395. * @id: device ID code
  396. * @pagesize: Pagesize in bytes. Either 256 or 512 or 0
  397. * If the pagesize is 0, then the real pagesize
  398. * and the eraseize are determined from the
  399. * extended id bytes in the chip
  400. * @erasesize: Size of an erase block in the flash device.
  401. * @chipsize: Total chipsize in Mega Bytes
  402. * @options: Bitfield to store chip relevant options
  403. */
  404. struct nand_flash_dev {
  405. char *name;
  406. int id;
  407. unsigned long pagesize;
  408. unsigned long chipsize;
  409. unsigned long erasesize;
  410. unsigned long options;
  411. };
  412. /**
  413. * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
  414. * @name: Manufacturer name
  415. * @id: manufacturer ID code of device.
  416. */
  417. struct nand_manufacturers {
  418. int id;
  419. char * name;
  420. };
  421. extern struct nand_flash_dev nand_flash_ids[];
  422. extern struct nand_manufacturers nand_manuf_ids[];
  423. /**
  424. * struct nand_bbt_descr - bad block table descriptor
  425. * @options: options for this descriptor
  426. * @pages: the page(s) where we find the bbt, used with option BBT_ABSPAGE
  427. * when bbt is searched, then we store the found bbts pages here.
  428. * Its an array and supports up to 8 chips now
  429. * @offs: offset of the pattern in the oob area of the page
  430. * @veroffs: offset of the bbt version counter in the oob are of the page
  431. * @version: version read from the bbt page during scan
  432. * @len: length of the pattern, if 0 no pattern check is performed
  433. * @maxblocks: maximum number of blocks to search for a bbt. This number of
  434. * blocks is reserved at the end of the device where the tables are
  435. * written.
  436. * @reserved_block_code: if non-0, this pattern denotes a reserved (rather than
  437. * bad) block in the stored bbt
  438. * @pattern: pattern to identify bad block table or factory marked good /
  439. * bad blocks, can be NULL, if len = 0
  440. *
  441. * Descriptor for the bad block table marker and the descriptor for the
  442. * pattern which identifies good and bad blocks. The assumption is made
  443. * that the pattern and the version count are always located in the oob area
  444. * of the first block.
  445. */
  446. struct nand_bbt_descr {
  447. int options;
  448. int pages[NAND_MAX_CHIPS];
  449. int offs;
  450. int veroffs;
  451. uint8_t version[NAND_MAX_CHIPS];
  452. int len;
  453. int maxblocks;
  454. int reserved_block_code;
  455. uint8_t *pattern;
  456. };
  457. /* Options for the bad block table descriptors */
  458. /* The number of bits used per block in the bbt on the device */
  459. #define NAND_BBT_NRBITS_MSK 0x0000000F
  460. #define NAND_BBT_1BIT 0x00000001
  461. #define NAND_BBT_2BIT 0x00000002
  462. #define NAND_BBT_4BIT 0x00000004
  463. #define NAND_BBT_8BIT 0x00000008
  464. /* The bad block table is in the last good block of the device */
  465. #define NAND_BBT_LASTBLOCK 0x00000010
  466. /* The bbt is at the given page, else we must scan for the bbt */
  467. #define NAND_BBT_ABSPAGE 0x00000020
  468. /* The bbt is at the given page, else we must scan for the bbt */
  469. #define NAND_BBT_SEARCH 0x00000040
  470. /* bbt is stored per chip on multichip devices */
  471. #define NAND_BBT_PERCHIP 0x00000080
  472. /* bbt has a version counter at offset veroffs */
  473. #define NAND_BBT_VERSION 0x00000100
  474. /* Create a bbt if none axists */
  475. #define NAND_BBT_CREATE 0x00000200
  476. /* Search good / bad pattern through all pages of a block */
  477. #define NAND_BBT_SCANALLPAGES 0x00000400
  478. /* Scan block empty during good / bad block scan */
  479. #define NAND_BBT_SCANEMPTY 0x00000800
  480. /* Write bbt if neccecary */
  481. #define NAND_BBT_WRITE 0x00001000
  482. /* Read and write back block contents when writing bbt */
  483. #define NAND_BBT_SAVECONTENT 0x00002000
  484. /* Search good / bad pattern on the first and the second page */
  485. #define NAND_BBT_SCAN2NDPAGE 0x00004000
  486. /* The maximum number of blocks to scan for a bbt */
  487. #define NAND_BBT_SCAN_MAXBLOCKS 4
  488. extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
  489. extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
  490. extern int nand_default_bbt(struct mtd_info *mtd);
  491. extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
  492. extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  493. int allowbbt);
  494. extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
  495. size_t * retlen, uint8_t * buf);
  496. /*
  497. * Constants for oob configuration
  498. */
  499. #define NAND_SMALL_BADBLOCK_POS 5
  500. #define NAND_LARGE_BADBLOCK_POS 0
  501. /**
  502. * struct platform_nand_chip - chip level device structure
  503. * @nr_chips: max. number of chips to scan for
  504. * @chip_offset: chip number offset
  505. * @nr_partitions: number of partitions pointed to by partitions (or zero)
  506. * @partitions: mtd partition list
  507. * @chip_delay: R/B delay value in us
  508. * @options: Option flags, e.g. 16bit buswidth
  509. * @ecclayout: ecc layout info structure
  510. * @priv: hardware controller specific settings
  511. */
  512. struct platform_nand_chip {
  513. int nr_chips;
  514. int chip_offset;
  515. int nr_partitions;
  516. struct mtd_partition *partitions;
  517. struct nand_ecclayout *ecclayout;
  518. int chip_delay;
  519. unsigned int options;
  520. void *priv;
  521. };
  522. /**
  523. * struct platform_nand_ctrl - controller level device structure
  524. * @hwcontrol: platform specific hardware control structure
  525. * @dev_ready: platform specific function to read ready/busy pin
  526. * @select_chip: platform specific chip select function
  527. * @priv: private data to transport driver specific settings
  528. *
  529. * All fields are optional and depend on the hardware driver requirements
  530. */
  531. struct platform_nand_ctrl {
  532. void (*hwcontrol)(struct mtd_info *mtd, int cmd);
  533. int (*dev_ready)(struct mtd_info *mtd);
  534. void (*select_chip)(struct mtd_info *mtd, int chip);
  535. void *priv;
  536. };
  537. /* Some helpers to access the data structures */
  538. static inline
  539. struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
  540. {
  541. struct nand_chip *chip = mtd->priv;
  542. return chip->priv;
  543. }
  544. #endif /* __LINUX_MTD_NAND_H */