iflash.h 3.3 KB

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  1. /* $Id: iflash.h,v 1.1.1.1 2007/06/12 07:27:16 eyryu Exp $ */
  2. #ifndef __MTD_IFLASH_H__
  3. #define __MTD_IFLASH_H__
  4. /* Extended CIS registers for Series 2 and 2+ cards */
  5. /* The registers are all offsets from 0x4000 */
  6. #define CISREG_CSR 0x0100
  7. #define CISREG_WP 0x0104
  8. #define CISREG_RDYBSY 0x0140
  9. /* Extended CIS registers for Series 2 cards */
  10. #define CISREG_SLEEP 0x0118
  11. #define CISREG_RDY_MASK 0x0120
  12. #define CISREG_RDY_STATUS 0x0130
  13. /* Extended CIS registers for Series 2+ cards */
  14. #define CISREG_VCR 0x010c
  15. /* Card Status Register */
  16. #define CSR_SRESET 0x20 /* Soft reset */
  17. #define CSR_CMWP 0x10 /* Common memory write protect */
  18. #define CSR_PWRDOWN 0x08 /* Power down status */
  19. #define CSR_CISWP 0x04 /* Common memory CIS WP */
  20. #define CSR_WP 0x02 /* Mechanical write protect */
  21. #define CSR_READY 0x01 /* Ready/busy status */
  22. /* Write Protection Register */
  23. #define WP_BLKEN 0x04 /* Enable block locking */
  24. #define WP_CMWP 0x02 /* Common memory write protect */
  25. #define WP_CISWP 0x01 /* Common memory CIS WP */
  26. /* Voltage Control Register */
  27. #define VCR_VCC_LEVEL 0x80 /* 0 = 5V, 1 = 3.3V */
  28. #define VCR_VPP_VALID 0x02 /* Vpp Valid */
  29. #define VCR_VPP_GEN 0x01 /* Integrated Vpp generator */
  30. /* Ready/Busy Mode Register */
  31. #define RDYBSY_RACK 0x02 /* Ready acknowledge */
  32. #define RDYBSY_MODE 0x01 /* 1 = high performance */
  33. #define LOW(x) ((x) & 0xff)
  34. /* 28F008SA-Compatible Command Set */
  35. #define IF_READ_ARRAY 0xffff
  36. #define IF_INTEL_ID 0x9090
  37. #define IF_READ_CSR 0x7070
  38. #define IF_CLEAR_CSR 0x5050
  39. #define IF_WRITE 0x4040
  40. #define IF_BLOCK_ERASE 0x2020
  41. #define IF_ERASE_SUSPEND 0xb0b0
  42. #define IF_CONFIRM 0xd0d0
  43. /* 28F016SA Performance Enhancement Commands */
  44. #define IF_READ_PAGE 0x7575
  45. #define IF_PAGE_SWAP 0x7272
  46. #define IF_SINGLE_LOAD 0x7474
  47. #define IF_SEQ_LOAD 0xe0e0
  48. #define IF_PAGE_WRITE 0x0c0c
  49. #define IF_RDY_MODE 0x9696
  50. #define IF_RDY_LEVEL 0x0101
  51. #define IF_RDY_PULSE_WRITE 0x0202
  52. #define IF_RDY_PULSE_ERASE 0x0303
  53. #define IF_RDY_DISABLE 0x0404
  54. #define IF_LOCK_BLOCK 0x7777
  55. #define IF_UPLOAD_STATUS 0x9797
  56. #define IF_READ_ESR 0x7171
  57. #define IF_ERASE_UNLOCKED 0xa7a7
  58. #define IF_SLEEP 0xf0f0
  59. #define IF_ABORT 0x8080
  60. #define IF_UPLOAD_DEVINFO 0x9999
  61. /* Definitions for Compatible Status Register */
  62. #define CSR_WR_READY 0x8080 /* Write state machine status */
  63. #define CSR_ERA_SUSPEND 0x4040 /* Erase suspend status */
  64. #define CSR_ERA_ERR 0x2020 /* Erase status */
  65. #define CSR_WR_ERR 0x1010 /* Data write status */
  66. #define CSR_VPP_LOW 0x0808 /* Vpp status */
  67. /* Definitions for Global Status Register */
  68. #define GSR_WR_READY 0x8080 /* Write state machine status */
  69. #define GSR_OP_SUSPEND 0x4040 /* Operation suspend status */
  70. #define GSR_OP_ERR 0x2020 /* Device operation status */
  71. #define GSR_SLEEP 0x1010 /* Device sleep status */
  72. #define GSR_QUEUE_FULL 0x0808 /* Queue status */
  73. #define GSR_PAGE_AVAIL 0x0404 /* Page buffer available status */
  74. #define GSR_PAGE_READY 0x0202 /* Page buffer status */
  75. #define GSR_PAGE_SELECT 0x0101 /* Page buffer select status */
  76. /* Definitions for Block Status Register */
  77. #define BSR_READY 0x8080 /* Block status */
  78. #define BSR_UNLOCK 0x4040 /* Block lock status */
  79. #define BSR_FAILED 0x2020 /* Block operation status */
  80. #define BSR_ABORTED 0x1010 /* Operation abort status */
  81. #define BSR_QUEUE_FULL 0x0808 /* Queue status */
  82. #define BSR_VPP_LOW 0x0404 /* Vpp status */
  83. #endif /* __MTD_IFLASH_H__ */