m41t00.h 1.5 KB

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  1. /*
  2. * Definitions for the ST M41T00 family of i2c rtc chips.
  3. *
  4. * Author: Mark A. Greer <mgreer@mvista.com>
  5. *
  6. * 2005, 2006 (c) MontaVista Software, Inc. This file is licensed under
  7. * the terms of the GNU General Public License version 2. This program
  8. * is licensed "as is" without any warranty of any kind, whether express
  9. * or implied.
  10. */
  11. #ifndef _M41T00_H
  12. #define _M41T00_H
  13. #define M41T00_DRV_NAME "m41t00"
  14. #define M41T00_I2C_ADDR 0x68
  15. #define M41T00_TYPE_M41T00 0
  16. #define M41T00_TYPE_M41T81 81
  17. #define M41T00_TYPE_M41T85 85
  18. struct m41t00_platform_data {
  19. u8 type;
  20. u8 i2c_addr;
  21. u8 sqw_freq;
  22. };
  23. /* SQW output disabled, this is default value by power on */
  24. #define M41T00_SQW_DISABLE (0)
  25. #define M41T00_SQW_32KHZ (1<<4) /* 32.768 KHz */
  26. #define M41T00_SQW_8KHZ (2<<4) /* 8.192 KHz */
  27. #define M41T00_SQW_4KHZ (3<<4) /* 4.096 KHz */
  28. #define M41T00_SQW_2KHZ (4<<4) /* 2.048 KHz */
  29. #define M41T00_SQW_1KHZ (5<<4) /* 1.024 KHz */
  30. #define M41T00_SQW_512HZ (6<<4) /* 512 Hz */
  31. #define M41T00_SQW_256HZ (7<<4) /* 256 Hz */
  32. #define M41T00_SQW_128HZ (8<<4) /* 128 Hz */
  33. #define M41T00_SQW_64HZ (9<<4) /* 64 Hz */
  34. #define M41T00_SQW_32HZ (10<<4) /* 32 Hz */
  35. #define M41T00_SQW_16HZ (11<<4) /* 16 Hz */
  36. #define M41T00_SQW_8HZ (12<<4) /* 8 Hz */
  37. #define M41T00_SQW_4HZ (13<<4) /* 4 Hz */
  38. #define M41T00_SQW_2HZ (14<<4) /* 2 Hz */
  39. #define M41T00_SQW_1HZ (15<<4) /* 1 Hz */
  40. extern ulong m41t00_get_rtc_time(void);
  41. extern int m41t00_set_rtc_time(ulong nowtime);
  42. #endif /* _M41T00_H */