fsl_devices.h 4.6 KB

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  1. /*
  2. * include/linux/fsl_devices.h
  3. *
  4. * Definitions for any platform device related flags or structures for
  5. * Freescale processor devices
  6. *
  7. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  8. *
  9. * Copyright 2004 Freescale Semiconductor, Inc
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. #ifdef __KERNEL__
  17. #ifndef _FSL_DEVICE_H_
  18. #define _FSL_DEVICE_H_
  19. #include <linux/types.h>
  20. #include <linux/phy.h>
  21. /*
  22. * Some conventions on how we handle peripherals on Freescale chips
  23. *
  24. * unique device: a platform_device entry in fsl_plat_devs[] plus
  25. * associated device information in its platform_data structure.
  26. *
  27. * A chip is described by a set of unique devices.
  28. *
  29. * Each sub-arch has its own master list of unique devices and
  30. * enumerates them by enum fsl_devices in a sub-arch specific header
  31. *
  32. * The platform data structure is broken into two parts. The
  33. * first is device specific information that help identify any
  34. * unique features of a peripheral. The second is any
  35. * information that may be defined by the board or how the device
  36. * is connected externally of the chip.
  37. *
  38. * naming conventions:
  39. * - platform data structures: <driver>_platform_data
  40. * - platform data device flags: FSL_<driver>_DEV_<FLAG>
  41. * - platform data board flags: FSL_<driver>_BRD_<FLAG>
  42. *
  43. */
  44. struct gianfar_platform_data {
  45. /* device specific information */
  46. u32 device_flags;
  47. /* board specific information */
  48. u32 board_flags;
  49. u32 bus_id;
  50. u32 phy_id;
  51. u8 mac_addr[6];
  52. };
  53. struct gianfar_mdio_data {
  54. /* board specific information */
  55. int irq[32];
  56. };
  57. /* Flags related to gianfar device features */
  58. #define FSL_GIANFAR_DEV_HAS_GIGABIT 0x00000001
  59. #define FSL_GIANFAR_DEV_HAS_COALESCE 0x00000002
  60. #define FSL_GIANFAR_DEV_HAS_RMON 0x00000004
  61. #define FSL_GIANFAR_DEV_HAS_MULTI_INTR 0x00000008
  62. #define FSL_GIANFAR_DEV_HAS_CSUM 0x00000010
  63. #define FSL_GIANFAR_DEV_HAS_VLAN 0x00000020
  64. #define FSL_GIANFAR_DEV_HAS_EXTENDED_HASH 0x00000040
  65. #define FSL_GIANFAR_DEV_HAS_PADDING 0x00000080
  66. /* Flags in gianfar_platform_data */
  67. #define FSL_GIANFAR_BRD_HAS_PHY_INTR 0x00000001 /* set or use a timer */
  68. #define FSL_GIANFAR_BRD_IS_REDUCED 0x00000002 /* Set if RGMII, RMII */
  69. struct fsl_i2c_platform_data {
  70. /* device specific information */
  71. u32 device_flags;
  72. };
  73. /* Flags related to I2C device features */
  74. #define FSL_I2C_DEV_SEPARATE_DFSRR 0x00000001
  75. #define FSL_I2C_DEV_CLOCK_5200 0x00000002
  76. enum fsl_usb2_operating_modes {
  77. FSL_USB2_MPH_HOST,
  78. FSL_USB2_DR_HOST,
  79. FSL_USB2_DR_DEVICE,
  80. FSL_USB2_DR_OTG,
  81. };
  82. enum fsl_usb2_phy_modes {
  83. FSL_USB2_PHY_NONE,
  84. FSL_USB2_PHY_ULPI,
  85. FSL_USB2_PHY_UTMI,
  86. FSL_USB2_PHY_UTMI_WIDE,
  87. FSL_USB2_PHY_SERIAL,
  88. };
  89. struct fsl_usb2_platform_data {
  90. /* board specific information */
  91. enum fsl_usb2_operating_modes operating_mode;
  92. enum fsl_usb2_phy_modes phy_mode;
  93. unsigned int port_enables;
  94. };
  95. /* Flags in fsl_usb2_mph_platform_data */
  96. #define FSL_USB2_PORT0_ENABLED 0x00000001
  97. #define FSL_USB2_PORT1_ENABLED 0x00000002
  98. struct fsl_spi_platform_data {
  99. u32 initial_spmode; /* initial SPMODE value */
  100. u16 bus_num;
  101. /* board specific information */
  102. u16 max_chipselect;
  103. void (*activate_cs)(u8 cs, u8 polarity);
  104. void (*deactivate_cs)(u8 cs, u8 polarity);
  105. u32 sysclk;
  106. };
  107. /* Ethernet interface (phy management and speed)
  108. */
  109. enum enet_interface {
  110. ENET_10_MII, /* 10 Base T, MII interface */
  111. ENET_10_RMII, /* 10 Base T, RMII interface */
  112. ENET_10_RGMII, /* 10 Base T, RGMII interface */
  113. ENET_100_MII, /* 100 Base T, MII interface */
  114. ENET_100_RMII, /* 100 Base T, RMII interface */
  115. ENET_100_RGMII, /* 100 Base T, RGMII interface */
  116. ENET_1000_GMII, /* 1000 Base T, GMII interface */
  117. ENET_1000_RGMII, /* 1000 Base T, RGMII interface */
  118. ENET_1000_TBI, /* 1000 Base T, TBI interface */
  119. ENET_1000_RTBI /* 1000 Base T, RTBI interface */
  120. };
  121. struct ucc_geth_platform_data {
  122. /* device specific information */
  123. u32 device_flags;
  124. u32 phy_reg_addr;
  125. /* board specific information */
  126. u32 board_flags;
  127. u8 rx_clock;
  128. u8 tx_clock;
  129. u32 phy_id;
  130. enum enet_interface phy_interface;
  131. u32 phy_interrupt;
  132. u8 mac_addr[6];
  133. };
  134. /* Flags related to UCC Gigabit Ethernet device features */
  135. #define FSL_UGETH_DEV_HAS_GIGABIT 0x00000001
  136. #define FSL_UGETH_DEV_HAS_COALESCE 0x00000002
  137. #define FSL_UGETH_DEV_HAS_RMON 0x00000004
  138. /* Flags in ucc_geth_platform_data */
  139. #define FSL_UGETH_BRD_HAS_PHY_INTR 0x00000001
  140. /* if not set use a timer */
  141. #endif /* _FSL_DEVICE_H_ */
  142. #endif /* __KERNEL__ */