fd1772.h 3.2 KB

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  1. #ifndef _LINUX_FD1772REG_H
  2. #define _LINUX_FD1772REG_H
  3. /*
  4. ** WD1772 stuff - originally from the M68K Linux
  5. * Modified for Archimedes by Dave Gilbert (gilbertd@cs.man.ac.uk)
  6. */
  7. /* register codes */
  8. #define FDC1772SELREG_STP (0x80) /* command/status register */
  9. #define FDC1772SELREG_TRA (0x82) /* track register */
  10. #define FDC1772SELREG_SEC (0x84) /* sector register */
  11. #define FDC1772SELREG_DTA (0x86) /* data register */
  12. /* register names for FDC1772_READ/WRITE macros */
  13. #define FDC1772REG_CMD 0
  14. #define FDC1772REG_STATUS 0
  15. #define FDC1772REG_TRACK 2
  16. #define FDC1772REG_SECTOR 4
  17. #define FDC1772REG_DATA 6
  18. /* command opcodes */
  19. #define FDC1772CMD_RESTORE (0x00) /* - */
  20. #define FDC1772CMD_SEEK (0x10) /* | */
  21. #define FDC1772CMD_STEP (0x20) /* | TYP 1 Commands */
  22. #define FDC1772CMD_STIN (0x40) /* | */
  23. #define FDC1772CMD_STOT (0x60) /* - */
  24. #define FDC1772CMD_RDSEC (0x80) /* - TYP 2 Commands */
  25. #define FDC1772CMD_WRSEC (0xa0) /* - " */
  26. #define FDC1772CMD_RDADR (0xc0) /* - */
  27. #define FDC1772CMD_RDTRA (0xe0) /* | TYP 3 Commands */
  28. #define FDC1772CMD_WRTRA (0xf0) /* - */
  29. #define FDC1772CMD_FORCI (0xd0) /* - TYP 4 Command */
  30. /* command modifier bits */
  31. #define FDC1772CMDADD_SR6 (0x00) /* step rate settings */
  32. #define FDC1772CMDADD_SR12 (0x01)
  33. #define FDC1772CMDADD_SR2 (0x02)
  34. #define FDC1772CMDADD_SR3 (0x03)
  35. #define FDC1772CMDADD_V (0x04) /* verify */
  36. #define FDC1772CMDADD_H (0x08) /* wait for spin-up */
  37. #define FDC1772CMDADD_U (0x10) /* update track register */
  38. #define FDC1772CMDADD_M (0x10) /* multiple sector access */
  39. #define FDC1772CMDADD_E (0x04) /* head settling flag */
  40. #define FDC1772CMDADD_P (0x02) /* precompensation */
  41. #define FDC1772CMDADD_A0 (0x01) /* DAM flag */
  42. /* status register bits */
  43. #define FDC1772STAT_MOTORON (0x80) /* motor on */
  44. #define FDC1772STAT_WPROT (0x40) /* write protected (FDC1772CMD_WR*) */
  45. #define FDC1772STAT_SPINUP (0x20) /* motor speed stable (Type I) */
  46. #define FDC1772STAT_DELDAM (0x20) /* sector has deleted DAM (Type II+III) */
  47. #define FDC1772STAT_RECNF (0x10) /* record not found */
  48. #define FDC1772STAT_CRC (0x08) /* CRC error */
  49. #define FDC1772STAT_TR00 (0x04) /* Track 00 flag (Type I) */
  50. #define FDC1772STAT_LOST (0x04) /* Lost Data (Type II+III) */
  51. #define FDC1772STAT_IDX (0x02) /* Index status (Type I) */
  52. #define FDC1772STAT_DRQ (0x02) /* DRQ status (Type II+III) */
  53. #define FDC1772STAT_BUSY (0x01) /* FDC1772 is busy */
  54. /* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
  55. #define DSKSIDE (0x01)
  56. #define DSKDRVNONE (0x06)
  57. #define DSKDRV0 (0x02)
  58. #define DSKDRV1 (0x04)
  59. /* step rates */
  60. #define FDC1772STEP_6 0x00
  61. #define FDC1772STEP_12 0x01
  62. #define FDC1772STEP_2 0x02
  63. #define FDC1772STEP_3 0x03
  64. #endif