cyclades.h 26 KB

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  1. /* $Revision: 1.1.1.1 $$Date: 2007/06/12 07:27:16 $
  2. * linux/include/linux/cyclades.h
  3. *
  4. * This file was initially written by
  5. * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
  6. * Ivan Passos <ivan@cyclades.com>.
  7. *
  8. * This file contains the general definitions for the cyclades.c driver
  9. *$Log: cyclades.h,v $
  10. *Revision 1.1.1.1 2007/06/12 07:27:16 eyryu
  11. *s3c-linux-2.6.21.5
  12. *
  13. *Revision 3.1 2002/01/29 11:36:16 henrique
  14. *added throttle field on struct cyclades_port to indicate whether the
  15. *port is throttled or not
  16. *
  17. *Revision 3.1 2000/04/19 18:52:52 ivan
  18. *converted address fields to unsigned long and added fields for physical
  19. *addresses on cyclades_card structure;
  20. *
  21. *Revision 3.0 1998/11/02 14:20:59 ivan
  22. *added nports field on cyclades_card structure;
  23. *
  24. *Revision 2.5 1998/08/03 16:57:01 ivan
  25. *added cyclades_idle_stats structure;
  26. *
  27. *Revision 2.4 1998/06/01 12:09:53 ivan
  28. *removed closing_wait2 from cyclades_port structure;
  29. *
  30. *Revision 2.3 1998/03/16 18:01:12 ivan
  31. *changes in the cyclades_port structure to get it closer to the
  32. *standard serial port structure;
  33. *added constants for new ioctls;
  34. *
  35. *Revision 2.2 1998/02/17 16:50:00 ivan
  36. *changes in the cyclades_port structure (addition of shutdown_wait and
  37. *chip_rev variables);
  38. *added constants for new ioctls and for CD1400 rev. numbers.
  39. *
  40. *Revision 2.1 1997/10/24 16:03:00 ivan
  41. *added rflow (which allows enabling the CD1400 special flow control
  42. *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to
  43. *cyclades_port structure;
  44. *added Alpha support
  45. *
  46. *Revision 2.0 1997/06/30 10:30:00 ivan
  47. *added some new doorbell command constants related to IOCTLW and
  48. *UART error signaling
  49. *
  50. *Revision 1.8 1997/06/03 15:30:00 ivan
  51. *added constant ZFIRM_HLT
  52. *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
  53. *
  54. *Revision 1.7 1997/03/26 10:30:00 daniel
  55. *new entries at the end of cyclades_port struct to reallocate
  56. *variables illegally allocated within card memory.
  57. *
  58. *Revision 1.6 1996/09/09 18:35:30 bentson
  59. *fold in changes for Cyclom-Z -- including structures for
  60. *communicating with board as well modest changes to original
  61. *structures to support new features.
  62. *
  63. *Revision 1.5 1995/11/13 21:13:31 bentson
  64. *changes suggested by Michael Chastain <mec@duracef.shout.net>
  65. *to support use of this file in non-kernel applications
  66. *
  67. *
  68. */
  69. #ifndef _LINUX_CYCLADES_H
  70. #define _LINUX_CYCLADES_H
  71. struct cyclades_monitor {
  72. unsigned long int_count;
  73. unsigned long char_count;
  74. unsigned long char_max;
  75. unsigned long char_last;
  76. };
  77. /*
  78. * These stats all reflect activity since the device was last initialized.
  79. * (i.e., since the port was opened with no other processes already having it
  80. * open)
  81. */
  82. struct cyclades_idle_stats {
  83. time_t in_use; /* Time device has been in use (secs) */
  84. time_t recv_idle; /* Time since last char received (secs) */
  85. time_t xmit_idle; /* Time since last char transmitted (secs) */
  86. unsigned long recv_bytes; /* Bytes received */
  87. unsigned long xmit_bytes; /* Bytes transmitted */
  88. unsigned long overruns; /* Input overruns */
  89. unsigned long frame_errs; /* Input framing errors */
  90. unsigned long parity_errs; /* Input parity errors */
  91. };
  92. #define CYCLADES_MAGIC 0x4359
  93. #define CYGETMON 0x435901
  94. #define CYGETTHRESH 0x435902
  95. #define CYSETTHRESH 0x435903
  96. #define CYGETDEFTHRESH 0x435904
  97. #define CYSETDEFTHRESH 0x435905
  98. #define CYGETTIMEOUT 0x435906
  99. #define CYSETTIMEOUT 0x435907
  100. #define CYGETDEFTIMEOUT 0x435908
  101. #define CYSETDEFTIMEOUT 0x435909
  102. #define CYSETRFLOW 0x43590a
  103. #define CYGETRFLOW 0x43590b
  104. #define CYSETRTSDTR_INV 0x43590c
  105. #define CYGETRTSDTR_INV 0x43590d
  106. #define CYZSETPOLLCYCLE 0x43590e
  107. #define CYZGETPOLLCYCLE 0x43590f
  108. #define CYGETCD1400VER 0x435910
  109. #define CYGETCARDINFO 0x435911
  110. #define CYSETWAIT 0x435912
  111. #define CYGETWAIT 0x435913
  112. /*************** CYCLOM-Z ADDITIONS ***************/
  113. #define CZIOC ('M' << 8)
  114. #define CZ_NBOARDS (CZIOC|0xfa)
  115. #define CZ_BOOT_START (CZIOC|0xfb)
  116. #define CZ_BOOT_DATA (CZIOC|0xfc)
  117. #define CZ_BOOT_END (CZIOC|0xfd)
  118. #define CZ_TEST (CZIOC|0xfe)
  119. #define CZ_DEF_POLL (HZ/25)
  120. #define MAX_BOARD 4 /* Max number of boards */
  121. #define MAX_DEV 256 /* Max number of ports total */
  122. #define CYZ_MAX_SPEED 921600
  123. #define CYZ_FIFO_SIZE 16
  124. #define CYZ_BOOT_NWORDS 0x100
  125. struct CYZ_BOOT_CTRL {
  126. unsigned short nboard;
  127. int status[MAX_BOARD];
  128. int nchannel[MAX_BOARD];
  129. int fw_rev[MAX_BOARD];
  130. unsigned long offset;
  131. unsigned long data[CYZ_BOOT_NWORDS];
  132. };
  133. #ifndef DP_WINDOW_SIZE
  134. /* #include "cyclomz.h" */
  135. /****************** ****************** *******************/
  136. /*
  137. * The data types defined below are used in all ZFIRM interface
  138. * data structures. They accomodate differences between HW
  139. * architectures and compilers.
  140. */
  141. #if defined(__alpha__)
  142. typedef unsigned long ucdouble; /* 64 bits, unsigned */
  143. typedef unsigned int uclong; /* 32 bits, unsigned */
  144. #else
  145. typedef unsigned long uclong; /* 32 bits, unsigned */
  146. #endif
  147. typedef unsigned short ucshort; /* 16 bits, unsigned */
  148. typedef unsigned char ucchar; /* 8 bits, unsigned */
  149. /*
  150. * Memory Window Sizes
  151. */
  152. #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */
  153. #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and
  154. 8Zo V.2 */
  155. #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */
  156. /*
  157. * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver
  158. * normally will access only interested on the fpga_id, fpga_version,
  159. * start_cpu and stop_cpu.
  160. */
  161. struct CUSTOM_REG {
  162. uclong fpga_id; /* FPGA Identification Register */
  163. uclong fpga_version; /* FPGA Version Number Register */
  164. uclong cpu_start; /* CPU start Register (write) */
  165. uclong cpu_stop; /* CPU stop Register (write) */
  166. uclong misc_reg; /* Miscelaneous Register */
  167. uclong idt_mode; /* IDT mode Register */
  168. uclong uart_irq_status; /* UART IRQ status Register */
  169. uclong clear_timer0_irq; /* Clear timer interrupt Register */
  170. uclong clear_timer1_irq; /* Clear timer interrupt Register */
  171. uclong clear_timer2_irq; /* Clear timer interrupt Register */
  172. uclong test_register; /* Test Register */
  173. uclong test_count; /* Test Count Register */
  174. uclong timer_select; /* Timer select register */
  175. uclong pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */
  176. uclong ram_wait_state; /* RAM wait-state Register */
  177. uclong uart_wait_state; /* UART wait-state Register */
  178. uclong timer_wait_state; /* timer wait-state Register */
  179. uclong ack_wait_state; /* ACK wait State Register */
  180. };
  181. /*
  182. * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
  183. * registers. This structure can be used to access the 9060 registers
  184. * (memory mapped).
  185. */
  186. struct RUNTIME_9060 {
  187. uclong loc_addr_range; /* 00h - Local Address Range */
  188. uclong loc_addr_base; /* 04h - Local Address Base */
  189. uclong loc_arbitr; /* 08h - Local Arbitration */
  190. uclong endian_descr; /* 0Ch - Big/Little Endian Descriptor */
  191. uclong loc_rom_range; /* 10h - Local ROM Range */
  192. uclong loc_rom_base; /* 14h - Local ROM Base */
  193. uclong loc_bus_descr; /* 18h - Local Bus descriptor */
  194. uclong loc_range_mst; /* 1Ch - Local Range for Master to PCI */
  195. uclong loc_base_mst; /* 20h - Local Base for Master PCI */
  196. uclong loc_range_io; /* 24h - Local Range for Master IO */
  197. uclong pci_base_mst; /* 28h - PCI Base for Master PCI */
  198. uclong pci_conf_io; /* 2Ch - PCI configuration for Master IO */
  199. uclong filler1; /* 30h */
  200. uclong filler2; /* 34h */
  201. uclong filler3; /* 38h */
  202. uclong filler4; /* 3Ch */
  203. uclong mail_box_0; /* 40h - Mail Box 0 */
  204. uclong mail_box_1; /* 44h - Mail Box 1 */
  205. uclong mail_box_2; /* 48h - Mail Box 2 */
  206. uclong mail_box_3; /* 4Ch - Mail Box 3 */
  207. uclong filler5; /* 50h */
  208. uclong filler6; /* 54h */
  209. uclong filler7; /* 58h */
  210. uclong filler8; /* 5Ch */
  211. uclong pci_doorbell; /* 60h - PCI to Local Doorbell */
  212. uclong loc_doorbell; /* 64h - Local to PCI Doorbell */
  213. uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */
  214. uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
  215. };
  216. /* Values for the Local Base Address re-map register */
  217. #define WIN_RAM 0x00000001L /* set the sliding window to RAM */
  218. #define WIN_CREG 0x14000001L /* set the window to custom Registers */
  219. /* Values timer select registers */
  220. #define TIMER_BY_1M 0x00 /* clock divided by 1M */
  221. #define TIMER_BY_256K 0x01 /* clock divided by 256k */
  222. #define TIMER_BY_128K 0x02 /* clock divided by 128k */
  223. #define TIMER_BY_32K 0x03 /* clock divided by 32k */
  224. /****************** ****************** *******************/
  225. #endif
  226. #ifndef ZFIRM_ID
  227. /* #include "zfwint.h" */
  228. /****************** ****************** *******************/
  229. /*
  230. * This file contains the definitions for interfacing with the
  231. * Cyclom-Z ZFIRM Firmware.
  232. */
  233. /* General Constant definitions */
  234. #define MAX_CHAN 64 /* max number of channels per board */
  235. /* firmware id structure (set after boot) */
  236. #define ID_ADDRESS 0x00000180L /* signature/pointer address */
  237. #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */
  238. #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */
  239. #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */
  240. #define ZF_TINACT_DEF 1000 /* default inactivity timeout
  241. (1000 ms) */
  242. #define ZF_TINACT ZF_TINACT_DEF
  243. struct FIRM_ID {
  244. uclong signature; /* ZFIRM/U signature */
  245. uclong zfwctrl_addr; /* pointer to ZFW_CTRL structure */
  246. };
  247. /* Op. System id */
  248. #define C_OS_LINUX 0x00000030 /* generic Linux system */
  249. /* channel op_mode */
  250. #define C_CH_DISABLE 0x00000000 /* channel is disabled */
  251. #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
  252. #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
  253. #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
  254. #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */
  255. /* comm_parity - parity */
  256. #define C_PR_NONE 0x00000000 /* None */
  257. #define C_PR_ODD 0x00000001 /* Odd */
  258. #define C_PR_EVEN 0x00000002 /* Even */
  259. #define C_PR_MARK 0x00000004 /* Mark */
  260. #define C_PR_SPACE 0x00000008 /* Space */
  261. #define C_PR_PARITY 0x000000ff
  262. #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */
  263. #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */
  264. /* comm_data_l - data length and stop bits */
  265. #define C_DL_CS5 0x00000001
  266. #define C_DL_CS6 0x00000002
  267. #define C_DL_CS7 0x00000004
  268. #define C_DL_CS8 0x00000008
  269. #define C_DL_CS 0x0000000f
  270. #define C_DL_1STOP 0x00000010
  271. #define C_DL_15STOP 0x00000020
  272. #define C_DL_2STOP 0x00000040
  273. #define C_DL_STOP 0x000000f0
  274. /* interrupt enabling/status */
  275. #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */
  276. #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */
  277. #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */
  278. #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */
  279. #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */
  280. #define C_IN_MDCD 0x00000100 /* modem DCD change */
  281. #define C_IN_MDSR 0x00000200 /* modem DSR change */
  282. #define C_IN_MRI 0x00000400 /* modem RI change */
  283. #define C_IN_MCTS 0x00000800 /* modem CTS change */
  284. #define C_IN_RXBRK 0x00001000 /* Break received */
  285. #define C_IN_PR_ERROR 0x00002000 /* parity error */
  286. #define C_IN_FR_ERROR 0x00004000 /* frame error */
  287. #define C_IN_OVR_ERROR 0x00008000 /* overrun error */
  288. #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */
  289. #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */
  290. #define C_IN_MRTS 0x00040000 /* modem RTS drop */
  291. #define C_IN_ICHAR 0x00080000
  292. /* flow control */
  293. #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */
  294. #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */
  295. #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */
  296. #define C_FL_SWFLOW 0x0000000f
  297. /* flow status */
  298. #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */
  299. #define C_FS_SENDING 0x00000001 /* UART is sending data */
  300. #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */
  301. /* rs_control/rs_status RS-232 signals */
  302. #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in
  303. IOCTLM command */
  304. #define C_RS_RTS 0x00000001 /* RTS */
  305. #define C_RS_DTR 0x00000004 /* DTR */
  306. #define C_RS_DCD 0x00000100 /* CD */
  307. #define C_RS_DSR 0x00000200 /* DSR */
  308. #define C_RS_RI 0x00000400 /* RI */
  309. #define C_RS_CTS 0x00000800 /* CTS */
  310. /* commands Host <-> Board */
  311. #define C_CM_RESET 0x01 /* reset/flush buffers */
  312. #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */
  313. #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */
  314. #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
  315. #define C_CM_SENDXOFF 0x10 /* send Xoff */
  316. #define C_CM_SENDXON 0x11 /* send Xon */
  317. #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */
  318. #define C_CM_SENDBRK 0x41 /* send break */
  319. #define C_CM_INTBACK 0x42 /* Interrupt back */
  320. #define C_CM_SET_BREAK 0x43 /* Tx break on */
  321. #define C_CM_CLR_BREAK 0x44 /* Tx break off */
  322. #define C_CM_CMD_DONE 0x45 /* Previous command done */
  323. #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */
  324. #define C_CM_TINACT 0x51 /* set inactivity detection */
  325. #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */
  326. #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */
  327. #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */
  328. #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */
  329. #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */
  330. #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */
  331. #define C_CM_Q_ENABLE 0x58 /* enables queue access from the
  332. driver */
  333. #define C_CM_Q_DISABLE 0x59 /* disables queue access from the
  334. driver */
  335. #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */
  336. #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */
  337. #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */
  338. #define C_CM_RXNNDT 0x63 /* rx no new data timeout */
  339. #define C_CM_TXFEMPTY 0x64
  340. #define C_CM_ICHAR 0x65
  341. #define C_CM_MDCD 0x70 /* modem DCD change */
  342. #define C_CM_MDSR 0x71 /* modem DSR change */
  343. #define C_CM_MRI 0x72 /* modem RI change */
  344. #define C_CM_MCTS 0x73 /* modem CTS change */
  345. #define C_CM_MRTS 0x74 /* modem RTS drop */
  346. #define C_CM_RXBRK 0x84 /* Break received */
  347. #define C_CM_PR_ERROR 0x85 /* Parity error */
  348. #define C_CM_FR_ERROR 0x86 /* Frame error */
  349. #define C_CM_OVR_ERROR 0x87 /* Overrun error */
  350. #define C_CM_RXOFL 0x88 /* RX buffer overflow */
  351. #define C_CM_CMDERROR 0x90 /* command error */
  352. #define C_CM_FATAL 0x91 /* fatal error */
  353. #define C_CM_HW_RESET 0x92 /* reset board */
  354. /*
  355. * CH_CTRL - This per port structure contains all parameters
  356. * that control an specific port. It can be seen as the
  357. * configuration registers of a "super-serial-controller".
  358. */
  359. struct CH_CTRL {
  360. uclong op_mode; /* operation mode */
  361. uclong intr_enable; /* interrupt masking */
  362. uclong sw_flow; /* SW flow control */
  363. uclong flow_status; /* output flow status */
  364. uclong comm_baud; /* baud rate - numerically specified */
  365. uclong comm_parity; /* parity */
  366. uclong comm_data_l; /* data length/stop */
  367. uclong comm_flags; /* other flags */
  368. uclong hw_flow; /* HW flow control */
  369. uclong rs_control; /* RS-232 outputs */
  370. uclong rs_status; /* RS-232 inputs */
  371. uclong flow_xon; /* xon char */
  372. uclong flow_xoff; /* xoff char */
  373. uclong hw_overflow; /* hw overflow counter */
  374. uclong sw_overflow; /* sw overflow counter */
  375. uclong comm_error; /* frame/parity error counter */
  376. uclong ichar;
  377. uclong filler[7];
  378. };
  379. /*
  380. * BUF_CTRL - This per channel structure contains
  381. * all Tx and Rx buffer control for a given channel.
  382. */
  383. struct BUF_CTRL {
  384. uclong flag_dma; /* buffers are in Host memory */
  385. uclong tx_bufaddr; /* address of the tx buffer */
  386. uclong tx_bufsize; /* tx buffer size */
  387. uclong tx_threshold; /* tx low water mark */
  388. uclong tx_get; /* tail index tx buf */
  389. uclong tx_put; /* head index tx buf */
  390. uclong rx_bufaddr; /* address of the rx buffer */
  391. uclong rx_bufsize; /* rx buffer size */
  392. uclong rx_threshold; /* rx high water mark */
  393. uclong rx_get; /* tail index rx buf */
  394. uclong rx_put; /* head index rx buf */
  395. uclong filler[5]; /* filler to align structures */
  396. };
  397. /*
  398. * BOARD_CTRL - This per board structure contains all global
  399. * control fields related to the board.
  400. */
  401. struct BOARD_CTRL {
  402. /* static info provided by the on-board CPU */
  403. uclong n_channel; /* number of channels */
  404. uclong fw_version; /* firmware version */
  405. /* static info provided by the driver */
  406. uclong op_system; /* op_system id */
  407. uclong dr_version; /* driver version */
  408. /* board control area */
  409. uclong inactivity; /* inactivity control */
  410. /* host to FW commands */
  411. uclong hcmd_channel; /* channel number */
  412. uclong hcmd_param; /* pointer to parameters */
  413. /* FW to Host commands */
  414. uclong fwcmd_channel; /* channel number */
  415. uclong fwcmd_param; /* pointer to parameters */
  416. uclong zf_int_queue_addr; /* offset for INT_QUEUE structure */
  417. /* filler so the structures are aligned */
  418. uclong filler[6];
  419. };
  420. /* Host Interrupt Queue */
  421. #define QUEUE_SIZE (10*MAX_CHAN)
  422. struct INT_QUEUE {
  423. unsigned char intr_code[QUEUE_SIZE];
  424. unsigned long channel[QUEUE_SIZE];
  425. unsigned long param[QUEUE_SIZE];
  426. unsigned long put;
  427. unsigned long get;
  428. };
  429. /*
  430. * ZFW_CTRL - This is the data structure that includes all other
  431. * data structures used by the Firmware.
  432. */
  433. struct ZFW_CTRL {
  434. struct BOARD_CTRL board_ctrl;
  435. struct CH_CTRL ch_ctrl[MAX_CHAN];
  436. struct BUF_CTRL buf_ctrl[MAX_CHAN];
  437. };
  438. /****************** ****************** *******************/
  439. #endif
  440. /* Per card data structure */
  441. struct resource;
  442. struct cyclades_card {
  443. unsigned long base_phys;
  444. unsigned long ctl_phys;
  445. void __iomem *base_addr;
  446. void __iomem *ctl_addr;
  447. int irq;
  448. int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */
  449. int first_line; /* minor number of first channel on card */
  450. int nports; /* Number of ports in the card */
  451. int bus_index; /* address shift - 0 for ISA, 1 for PCI */
  452. int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */
  453. struct pci_dev *pdev;
  454. #ifdef __KERNEL__
  455. spinlock_t card_lock;
  456. #else
  457. unsigned long filler;
  458. #endif
  459. };
  460. struct cyclades_chip {
  461. int filler;
  462. };
  463. #ifdef __KERNEL__
  464. /***************************************
  465. * Memory access functions/macros *
  466. * (required to support Alpha systems) *
  467. ***************************************/
  468. #define cy_writeb(port,val) {writeb((val),(port)); mb();}
  469. #define cy_writew(port,val) {writew((val),(port)); mb();}
  470. #define cy_writel(port,val) {writel((val),(port)); mb();}
  471. #define cy_readb(port) readb(port)
  472. #define cy_readw(port) readw(port)
  473. #define cy_readl(port) readl(port)
  474. /*
  475. * Statistics counters
  476. */
  477. struct cyclades_icount {
  478. __u32 cts, dsr, rng, dcd, tx, rx;
  479. __u32 frame, parity, overrun, brk;
  480. __u32 buf_overrun;
  481. };
  482. /*
  483. * This is our internal structure for each serial port's state.
  484. *
  485. * Many fields are paralleled by the structure used by the serial_struct
  486. * structure.
  487. *
  488. * For definitions of the flags field, see tty.h
  489. */
  490. struct cyclades_port {
  491. int magic;
  492. int card;
  493. int line;
  494. int flags; /* defined in tty.h */
  495. int type; /* UART type */
  496. struct tty_struct *tty;
  497. int read_status_mask;
  498. int ignore_status_mask;
  499. int timeout;
  500. int xmit_fifo_size;
  501. int cor1,cor2,cor3,cor4,cor5;
  502. int tbpr,tco,rbpr,rco;
  503. int baud;
  504. int rflow;
  505. int rtsdtr_inv;
  506. int chip_rev;
  507. int custom_divisor;
  508. int x_char; /* to be pushed out ASAP */
  509. int close_delay;
  510. unsigned short closing_wait;
  511. unsigned long event;
  512. unsigned long last_active;
  513. int count; /* # of fd on device */
  514. int breakon;
  515. int breakoff;
  516. int blocked_open; /* # of blocked opens */
  517. unsigned char *xmit_buf;
  518. int xmit_head;
  519. int xmit_tail;
  520. int xmit_cnt;
  521. int default_threshold;
  522. int default_timeout;
  523. unsigned long jiffies[3];
  524. unsigned long rflush_count;
  525. struct cyclades_monitor mon;
  526. struct cyclades_idle_stats idle_stats;
  527. struct cyclades_icount icount;
  528. struct work_struct tqueue;
  529. wait_queue_head_t open_wait;
  530. wait_queue_head_t close_wait;
  531. wait_queue_head_t shutdown_wait;
  532. wait_queue_head_t delta_msr_wait;
  533. int throttle;
  534. };
  535. /*
  536. * Events are used to schedule things to happen at timer-interrupt
  537. * time, instead of at cy interrupt time.
  538. */
  539. #define Cy_EVENT_READ_PROCESS 0
  540. #define Cy_EVENT_WRITE_WAKEUP 1
  541. #define Cy_EVENT_HANGUP 2
  542. #define Cy_EVENT_BREAK 3
  543. #define Cy_EVENT_OPEN_WAKEUP 4
  544. #define Cy_EVENT_SHUTDOWN_WAKEUP 5
  545. #define Cy_EVENT_DELTA_WAKEUP 6
  546. #define Cy_EVENT_Z_RX_FULL 7
  547. #define CLOSING_WAIT_DELAY 30*HZ
  548. #define CY_CLOSING_WAIT_NONE 65535
  549. #define CY_CLOSING_WAIT_INF 0
  550. #define CyMAX_CHIPS_PER_CARD 8
  551. #define CyMAX_CHAR_FIFO 12
  552. #define CyPORTS_PER_CHIP 4
  553. #define CD1400_MAX_SPEED 115200
  554. #define CyISA_Ywin 0x2000
  555. #define CyPCI_Ywin 0x4000
  556. #define CyPCI_Yctl 0x80
  557. #define CyPCI_Zctl CTRL_WINDOW_SIZE
  558. #define CyPCI_Zwin 0x80000
  559. #define CyPCI_Ze_win (2 * CyPCI_Zwin)
  560. #define PCI_DEVICE_ID_MASK 0x06
  561. /**** CD1400 registers ****/
  562. #define CD1400_REV_G 0x46
  563. #define CD1400_REV_J 0x48
  564. #define CyRegSize 0x0400
  565. #define Cy_HwReset 0x1400
  566. #define Cy_ClrIntr 0x1800
  567. #define Cy_EpldRev 0x1e00
  568. /* Global Registers */
  569. #define CyGFRCR (0x40*2)
  570. #define CyRevE (44)
  571. #define CyCAR (0x68*2)
  572. #define CyCHAN_0 (0x00)
  573. #define CyCHAN_1 (0x01)
  574. #define CyCHAN_2 (0x02)
  575. #define CyCHAN_3 (0x03)
  576. #define CyGCR (0x4B*2)
  577. #define CyCH0_SERIAL (0x00)
  578. #define CyCH0_PARALLEL (0x80)
  579. #define CySVRR (0x67*2)
  580. #define CySRModem (0x04)
  581. #define CySRTransmit (0x02)
  582. #define CySRReceive (0x01)
  583. #define CyRICR (0x44*2)
  584. #define CyTICR (0x45*2)
  585. #define CyMICR (0x46*2)
  586. #define CyICR0 (0x00)
  587. #define CyICR1 (0x01)
  588. #define CyICR2 (0x02)
  589. #define CyICR3 (0x03)
  590. #define CyRIR (0x6B*2)
  591. #define CyTIR (0x6A*2)
  592. #define CyMIR (0x69*2)
  593. #define CyIRDirEq (0x80)
  594. #define CyIRBusy (0x40)
  595. #define CyIRUnfair (0x20)
  596. #define CyIRContext (0x1C)
  597. #define CyIRChannel (0x03)
  598. #define CyPPR (0x7E*2)
  599. #define CyCLOCK_20_1MS (0x27)
  600. #define CyCLOCK_25_1MS (0x31)
  601. #define CyCLOCK_25_5MS (0xf4)
  602. #define CyCLOCK_60_1MS (0x75)
  603. #define CyCLOCK_60_2MS (0xea)
  604. /* Virtual Registers */
  605. #define CyRIVR (0x43*2)
  606. #define CyTIVR (0x42*2)
  607. #define CyMIVR (0x41*2)
  608. #define CyIVRMask (0x07)
  609. #define CyIVRRxEx (0x07)
  610. #define CyIVRRxOK (0x03)
  611. #define CyIVRTxOK (0x02)
  612. #define CyIVRMdmOK (0x01)
  613. #define CyTDR (0x63*2)
  614. #define CyRDSR (0x62*2)
  615. #define CyTIMEOUT (0x80)
  616. #define CySPECHAR (0x70)
  617. #define CyBREAK (0x08)
  618. #define CyPARITY (0x04)
  619. #define CyFRAME (0x02)
  620. #define CyOVERRUN (0x01)
  621. #define CyMISR (0x4C*2)
  622. /* see CyMCOR_ and CyMSVR_ for bits*/
  623. #define CyEOSRR (0x60*2)
  624. /* Channel Registers */
  625. #define CyLIVR (0x18*2)
  626. #define CyMscsr (0x01)
  627. #define CyTdsr (0x02)
  628. #define CyRgdsr (0x03)
  629. #define CyRedsr (0x07)
  630. #define CyCCR (0x05*2)
  631. /* Format 1 */
  632. #define CyCHAN_RESET (0x80)
  633. #define CyCHIP_RESET (0x81)
  634. #define CyFlushTransFIFO (0x82)
  635. /* Format 2 */
  636. #define CyCOR_CHANGE (0x40)
  637. #define CyCOR1ch (0x02)
  638. #define CyCOR2ch (0x04)
  639. #define CyCOR3ch (0x08)
  640. /* Format 3 */
  641. #define CySEND_SPEC_1 (0x21)
  642. #define CySEND_SPEC_2 (0x22)
  643. #define CySEND_SPEC_3 (0x23)
  644. #define CySEND_SPEC_4 (0x24)
  645. /* Format 4 */
  646. #define CyCHAN_CTL (0x10)
  647. #define CyDIS_RCVR (0x01)
  648. #define CyENB_RCVR (0x02)
  649. #define CyDIS_XMTR (0x04)
  650. #define CyENB_XMTR (0x08)
  651. #define CySRER (0x06*2)
  652. #define CyMdmCh (0x80)
  653. #define CyRxData (0x10)
  654. #define CyTxRdy (0x04)
  655. #define CyTxMpty (0x02)
  656. #define CyNNDT (0x01)
  657. #define CyCOR1 (0x08*2)
  658. #define CyPARITY_NONE (0x00)
  659. #define CyPARITY_0 (0x20)
  660. #define CyPARITY_1 (0xA0)
  661. #define CyPARITY_E (0x40)
  662. #define CyPARITY_O (0xC0)
  663. #define Cy_1_STOP (0x00)
  664. #define Cy_1_5_STOP (0x04)
  665. #define Cy_2_STOP (0x08)
  666. #define Cy_5_BITS (0x00)
  667. #define Cy_6_BITS (0x01)
  668. #define Cy_7_BITS (0x02)
  669. #define Cy_8_BITS (0x03)
  670. #define CyCOR2 (0x09*2)
  671. #define CyIXM (0x80)
  672. #define CyTxIBE (0x40)
  673. #define CyETC (0x20)
  674. #define CyAUTO_TXFL (0x60)
  675. #define CyLLM (0x10)
  676. #define CyRLM (0x08)
  677. #define CyRtsAO (0x04)
  678. #define CyCtsAE (0x02)
  679. #define CyDsrAE (0x01)
  680. #define CyCOR3 (0x0A*2)
  681. #define CySPL_CH_DRANGE (0x80) /* special character detect range */
  682. #define CySPL_CH_DET1 (0x40) /* enable special character detection
  683. on SCHR4-SCHR3 */
  684. #define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */
  685. #define CySPL_CH_DET2 (0x10) /* Enable special character detection
  686. on SCHR2-SCHR1 */
  687. #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
  688. #define CyCOR4 (0x1E*2)
  689. #define CyCOR5 (0x1F*2)
  690. #define CyCCSR (0x0B*2)
  691. #define CyRxEN (0x80)
  692. #define CyRxFloff (0x40)
  693. #define CyRxFlon (0x20)
  694. #define CyTxEN (0x08)
  695. #define CyTxFloff (0x04)
  696. #define CyTxFlon (0x02)
  697. #define CyRDCR (0x0E*2)
  698. #define CySCHR1 (0x1A*2)
  699. #define CySCHR2 (0x1B*2)
  700. #define CySCHR3 (0x1C*2)
  701. #define CySCHR4 (0x1D*2)
  702. #define CySCRL (0x22*2)
  703. #define CySCRH (0x23*2)
  704. #define CyLNC (0x24*2)
  705. #define CyMCOR1 (0x15*2)
  706. #define CyMCOR2 (0x16*2)
  707. #define CyRTPR (0x21*2)
  708. #define CyMSVR1 (0x6C*2)
  709. #define CyMSVR2 (0x6D*2)
  710. #define CyANY_DELTA (0xF0)
  711. #define CyDSR (0x80)
  712. #define CyCTS (0x40)
  713. #define CyRI (0x20)
  714. #define CyDCD (0x10)
  715. #define CyDTR (0x02)
  716. #define CyRTS (0x01)
  717. #define CyPVSR (0x6F*2)
  718. #define CyRBPR (0x78*2)
  719. #define CyRCOR (0x7C*2)
  720. #define CyTBPR (0x72*2)
  721. #define CyTCOR (0x76*2)
  722. /* Custom Registers */
  723. #define CyPLX_VER (0x3400)
  724. #define PLX_9050 0x0b
  725. #define PLX_9060 0x0c
  726. #define PLX_9080 0x0d
  727. /***************************************************************************/
  728. #endif /* __KERNEL__ */
  729. #endif /* _LINUX_CYCLADES_H */