cd1400.h 6.9 KB

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  1. /*****************************************************************************/
  2. /*
  3. * cd1400.h -- cd1400 UART hardware info.
  4. *
  5. * Copyright (C) 1996-1998 Stallion Technologies
  6. * Copyright (C) 1994-1996 Greg Ungerer.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21. */
  22. /*****************************************************************************/
  23. #ifndef _CD1400_H
  24. #define _CD1400_H
  25. /*****************************************************************************/
  26. /*
  27. * Define the number of async ports per cd1400 uart chip.
  28. */
  29. #define CD1400_PORTS 4
  30. /*
  31. * Define the cd1400 uarts internal FIFO sizes.
  32. */
  33. #define CD1400_TXFIFOSIZE 12
  34. #define CD1400_RXFIFOSIZE 12
  35. /*
  36. * Local RX FIFO thresh hold level. Also define the RTS thresh hold
  37. * based on the RX thresh hold.
  38. */
  39. #define FIFO_RXTHRESHOLD 6
  40. #define FIFO_RTSTHRESHOLD 7
  41. /*****************************************************************************/
  42. /*
  43. * Define the cd1400 register addresses. These are all the valid
  44. * registers with the cd1400. Some are global, some virtual, some
  45. * per port.
  46. */
  47. #define GFRCR 0x40
  48. #define CAR 0x68
  49. #define GCR 0x4b
  50. #define SVRR 0x67
  51. #define RICR 0x44
  52. #define TICR 0x45
  53. #define MICR 0x46
  54. #define RIR 0x6b
  55. #define TIR 0x6a
  56. #define MIR 0x69
  57. #define PPR 0x7e
  58. #define RIVR 0x43
  59. #define TIVR 0x42
  60. #define MIVR 0x41
  61. #define TDR 0x63
  62. #define RDSR 0x62
  63. #define MISR 0x4c
  64. #define EOSRR 0x60
  65. #define LIVR 0x18
  66. #define CCR 0x05
  67. #define SRER 0x06
  68. #define COR1 0x08
  69. #define COR2 0x09
  70. #define COR3 0x0a
  71. #define COR4 0x1e
  72. #define COR5 0x1f
  73. #define CCSR 0x0b
  74. #define RDCR 0x0e
  75. #define SCHR1 0x1a
  76. #define SCHR2 0x1b
  77. #define SCHR3 0x1c
  78. #define SCHR4 0x1d
  79. #define SCRL 0x22
  80. #define SCRH 0x23
  81. #define LNC 0x24
  82. #define MCOR1 0x15
  83. #define MCOR2 0x16
  84. #define RTPR 0x21
  85. #define MSVR1 0x6c
  86. #define MSVR2 0x6d
  87. #define PSVR 0x6f
  88. #define RBPR 0x78
  89. #define RCOR 0x7c
  90. #define TBPR 0x72
  91. #define TCOR 0x76
  92. /*****************************************************************************/
  93. /*
  94. * Define the set of baud rate clock divisors.
  95. */
  96. #define CD1400_CLK0 8
  97. #define CD1400_CLK1 32
  98. #define CD1400_CLK2 128
  99. #define CD1400_CLK3 512
  100. #define CD1400_CLK4 2048
  101. #define CD1400_NUMCLKS 5
  102. /*****************************************************************************/
  103. /*
  104. * Define the clock pre-scalar value to be a 5 ms clock. This should be
  105. * OK for now. It would probably be better to make it 10 ms, but we
  106. * can't fit that divisor into 8 bits!
  107. */
  108. #define PPR_SCALAR 244
  109. /*****************************************************************************/
  110. /*
  111. * Define values used to set character size options.
  112. */
  113. #define COR1_CHL5 0x00
  114. #define COR1_CHL6 0x01
  115. #define COR1_CHL7 0x02
  116. #define COR1_CHL8 0x03
  117. /*
  118. * Define values used to set the number of stop bits.
  119. */
  120. #define COR1_STOP1 0x00
  121. #define COR1_STOP15 0x04
  122. #define COR1_STOP2 0x08
  123. /*
  124. * Define values used to set the parity scheme in use.
  125. */
  126. #define COR1_PARNONE 0x00
  127. #define COR1_PARFORCE 0x20
  128. #define COR1_PARENB 0x40
  129. #define COR1_PARIGNORE 0x10
  130. #define COR1_PARODD 0x80
  131. #define COR1_PAREVEN 0x00
  132. #define COR2_IXM 0x80
  133. #define COR2_TXIBE 0x40
  134. #define COR2_ETC 0x20
  135. #define COR2_LLM 0x10
  136. #define COR2_RLM 0x08
  137. #define COR2_RTSAO 0x04
  138. #define COR2_CTSAE 0x02
  139. #define COR3_SCDRNG 0x80
  140. #define COR3_SCD34 0x40
  141. #define COR3_FCT 0x20
  142. #define COR3_SCD12 0x10
  143. /*
  144. * Define values used by COR4.
  145. */
  146. #define COR4_BRKINT 0x08
  147. #define COR4_IGNBRK 0x18
  148. /*****************************************************************************/
  149. /*
  150. * Define the modem control register values.
  151. * Note that the actual hardware is a little different to the conventional
  152. * pin names on the cd1400.
  153. */
  154. #define MSVR1_DTR 0x01
  155. #define MSVR1_DSR 0x10
  156. #define MSVR1_RI 0x20
  157. #define MSVR1_CTS 0x40
  158. #define MSVR1_DCD 0x80
  159. #define MSVR2_RTS 0x02
  160. #define MSVR2_DSR 0x10
  161. #define MSVR2_RI 0x20
  162. #define MSVR2_CTS 0x40
  163. #define MSVR2_DCD 0x80
  164. #define MCOR1_DCD 0x80
  165. #define MCOR1_CTS 0x40
  166. #define MCOR1_RI 0x20
  167. #define MCOR1_DSR 0x10
  168. #define MCOR2_DCD 0x80
  169. #define MCOR2_CTS 0x40
  170. #define MCOR2_RI 0x20
  171. #define MCOR2_DSR 0x10
  172. /*****************************************************************************/
  173. /*
  174. * Define the bits used with the service (interrupt) enable register.
  175. */
  176. #define SRER_NNDT 0x01
  177. #define SRER_TXEMPTY 0x02
  178. #define SRER_TXDATA 0x04
  179. #define SRER_RXDATA 0x10
  180. #define SRER_MODEM 0x80
  181. /*****************************************************************************/
  182. /*
  183. * Define operational commands for the command register.
  184. */
  185. #define CCR_RESET 0x80
  186. #define CCR_CORCHANGE 0x4e
  187. #define CCR_SENDCH 0x20
  188. #define CCR_CHANCTRL 0x10
  189. #define CCR_TXENABLE (CCR_CHANCTRL | 0x08)
  190. #define CCR_TXDISABLE (CCR_CHANCTRL | 0x04)
  191. #define CCR_RXENABLE (CCR_CHANCTRL | 0x02)
  192. #define CCR_RXDISABLE (CCR_CHANCTRL | 0x01)
  193. #define CCR_SENDSCHR1 (CCR_SENDCH | 0x01)
  194. #define CCR_SENDSCHR2 (CCR_SENDCH | 0x02)
  195. #define CCR_SENDSCHR3 (CCR_SENDCH | 0x03)
  196. #define CCR_SENDSCHR4 (CCR_SENDCH | 0x04)
  197. #define CCR_RESETCHAN (CCR_RESET | 0x00)
  198. #define CCR_RESETFULL (CCR_RESET | 0x01)
  199. #define CCR_TXFLUSHFIFO (CCR_RESET | 0x02)
  200. #define CCR_MAXWAIT 10000
  201. /*****************************************************************************/
  202. /*
  203. * Define the valid acknowledgement types (for hw ack cycle).
  204. */
  205. #define ACK_TYPMASK 0x07
  206. #define ACK_TYPTX 0x02
  207. #define ACK_TYPMDM 0x01
  208. #define ACK_TYPRXGOOD 0x03
  209. #define ACK_TYPRXBAD 0x07
  210. #define SVRR_RX 0x01
  211. #define SVRR_TX 0x02
  212. #define SVRR_MDM 0x04
  213. #define ST_OVERRUN 0x01
  214. #define ST_FRAMING 0x02
  215. #define ST_PARITY 0x04
  216. #define ST_BREAK 0x08
  217. #define ST_SCHAR1 0x10
  218. #define ST_SCHAR2 0x20
  219. #define ST_SCHAR3 0x30
  220. #define ST_SCHAR4 0x40
  221. #define ST_RANGE 0x70
  222. #define ST_SCHARMASK 0x70
  223. #define ST_TIMEOUT 0x80
  224. #define MISR_DCD 0x80
  225. #define MISR_CTS 0x40
  226. #define MISR_RI 0x20
  227. #define MISR_DSR 0x10
  228. /*****************************************************************************/
  229. /*
  230. * Defines for the CCSR status register.
  231. */
  232. #define CCSR_RXENABLED 0x80
  233. #define CCSR_RXFLOWON 0x40
  234. #define CCSR_RXFLOWOFF 0x20
  235. #define CCSR_TXENABLED 0x08
  236. #define CCSR_TXFLOWON 0x04
  237. #define CCSR_TXFLOWOFF 0x02
  238. /*****************************************************************************/
  239. /*
  240. * Define the embedded commands.
  241. */
  242. #define ETC_CMD 0x00
  243. #define ETC_STARTBREAK 0x81
  244. #define ETC_DELAY 0x82
  245. #define ETC_STOPBREAK 0x83
  246. /*****************************************************************************/
  247. #endif