tlbflush.h 13 KB

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  1. /*
  2. * linux/include/asm-arm/tlbflush.h
  3. *
  4. * Copyright (C) 1999-2003 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef _ASMARM_TLBFLUSH_H
  11. #define _ASMARM_TLBFLUSH_H
  12. #ifndef CONFIG_MMU
  13. #define tlb_flush(tlb) ((void) tlb)
  14. #else /* CONFIG_MMU */
  15. #include <asm/glue.h>
  16. #define TLB_V3_PAGE (1 << 0)
  17. #define TLB_V4_U_PAGE (1 << 1)
  18. #define TLB_V4_D_PAGE (1 << 2)
  19. #define TLB_V4_I_PAGE (1 << 3)
  20. #define TLB_V6_U_PAGE (1 << 4)
  21. #define TLB_V6_D_PAGE (1 << 5)
  22. #define TLB_V6_I_PAGE (1 << 6)
  23. #define TLB_V3_FULL (1 << 8)
  24. #define TLB_V4_U_FULL (1 << 9)
  25. #define TLB_V4_D_FULL (1 << 10)
  26. #define TLB_V4_I_FULL (1 << 11)
  27. #define TLB_V6_U_FULL (1 << 12)
  28. #define TLB_V6_D_FULL (1 << 13)
  29. #define TLB_V6_I_FULL (1 << 14)
  30. #define TLB_V6_U_ASID (1 << 16)
  31. #define TLB_V6_D_ASID (1 << 17)
  32. #define TLB_V6_I_ASID (1 << 18)
  33. #define TLB_DCLEAN (1 << 30)
  34. #define TLB_WB (1 << 31)
  35. /*
  36. * MMU TLB Model
  37. * =============
  38. *
  39. * We have the following to choose from:
  40. * v3 - ARMv3
  41. * v4 - ARMv4 without write buffer
  42. * v4wb - ARMv4 with write buffer without I TLB flush entry instruction
  43. * v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  44. * v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  45. */
  46. #undef _TLB
  47. #undef MULTI_TLB
  48. #define v3_tlb_flags (TLB_V3_FULL | TLB_V3_PAGE)
  49. #ifdef CONFIG_CPU_TLB_V3
  50. # define v3_possible_flags v3_tlb_flags
  51. # define v3_always_flags v3_tlb_flags
  52. # ifdef _TLB
  53. # define MULTI_TLB 1
  54. # else
  55. # define _TLB v3
  56. # endif
  57. #else
  58. # define v3_possible_flags 0
  59. # define v3_always_flags (-1UL)
  60. #endif
  61. #define v4_tlb_flags (TLB_V4_U_FULL | TLB_V4_U_PAGE)
  62. #ifdef CONFIG_CPU_TLB_V4WT
  63. # define v4_possible_flags v4_tlb_flags
  64. # define v4_always_flags v4_tlb_flags
  65. # ifdef _TLB
  66. # define MULTI_TLB 1
  67. # else
  68. # define _TLB v4
  69. # endif
  70. #else
  71. # define v4_possible_flags 0
  72. # define v4_always_flags (-1UL)
  73. #endif
  74. #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
  75. TLB_V4_I_FULL | TLB_V4_D_FULL | \
  76. TLB_V4_I_PAGE | TLB_V4_D_PAGE)
  77. #ifdef CONFIG_CPU_TLB_V4WBI
  78. # define v4wbi_possible_flags v4wbi_tlb_flags
  79. # define v4wbi_always_flags v4wbi_tlb_flags
  80. # ifdef _TLB
  81. # define MULTI_TLB 1
  82. # else
  83. # define _TLB v4wbi
  84. # endif
  85. #else
  86. # define v4wbi_possible_flags 0
  87. # define v4wbi_always_flags (-1UL)
  88. #endif
  89. #define v4wb_tlb_flags (TLB_WB | TLB_DCLEAN | \
  90. TLB_V4_I_FULL | TLB_V4_D_FULL | \
  91. TLB_V4_D_PAGE)
  92. #ifdef CONFIG_CPU_TLB_V4WB
  93. # define v4wb_possible_flags v4wb_tlb_flags
  94. # define v4wb_always_flags v4wb_tlb_flags
  95. # ifdef _TLB
  96. # define MULTI_TLB 1
  97. # else
  98. # define _TLB v4wb
  99. # endif
  100. #else
  101. # define v4wb_possible_flags 0
  102. # define v4wb_always_flags (-1UL)
  103. #endif
  104. #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
  105. TLB_V6_I_FULL | TLB_V6_D_FULL | \
  106. TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
  107. TLB_V6_I_ASID | TLB_V6_D_ASID)
  108. #ifdef CONFIG_CPU_TLB_V6
  109. # define v6wbi_possible_flags v6wbi_tlb_flags
  110. # define v6wbi_always_flags v6wbi_tlb_flags
  111. # ifdef _TLB
  112. # define MULTI_TLB 1
  113. # else
  114. # define _TLB v6wbi
  115. # endif
  116. #else
  117. # define v6wbi_possible_flags 0
  118. # define v6wbi_always_flags (-1UL)
  119. #endif
  120. #ifndef _TLB
  121. #error Unknown TLB model
  122. #endif
  123. #ifndef __ASSEMBLY__
  124. struct cpu_tlb_fns {
  125. void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
  126. void (*flush_kern_range)(unsigned long, unsigned long);
  127. unsigned long tlb_flags;
  128. };
  129. /*
  130. * Select the calling method
  131. */
  132. #ifdef MULTI_TLB
  133. #define __cpu_flush_user_tlb_range cpu_tlb.flush_user_range
  134. #define __cpu_flush_kern_tlb_range cpu_tlb.flush_kern_range
  135. #else
  136. #define __cpu_flush_user_tlb_range __glue(_TLB,_flush_user_tlb_range)
  137. #define __cpu_flush_kern_tlb_range __glue(_TLB,_flush_kern_tlb_range)
  138. extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
  139. extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
  140. #endif
  141. extern struct cpu_tlb_fns cpu_tlb;
  142. #define __cpu_tlb_flags cpu_tlb.tlb_flags
  143. /*
  144. * TLB Management
  145. * ==============
  146. *
  147. * The arch/arm/mm/tlb-*.S files implement these methods.
  148. *
  149. * The TLB specific code is expected to perform whatever tests it
  150. * needs to determine if it should invalidate the TLB for each
  151. * call. Start addresses are inclusive and end addresses are
  152. * exclusive; it is safe to round these addresses down.
  153. *
  154. * flush_tlb_all()
  155. *
  156. * Invalidate the entire TLB.
  157. *
  158. * flush_tlb_mm(mm)
  159. *
  160. * Invalidate all TLB entries in a particular address
  161. * space.
  162. * - mm - mm_struct describing address space
  163. *
  164. * flush_tlb_range(mm,start,end)
  165. *
  166. * Invalidate a range of TLB entries in the specified
  167. * address space.
  168. * - mm - mm_struct describing address space
  169. * - start - start address (may not be aligned)
  170. * - end - end address (exclusive, may not be aligned)
  171. *
  172. * flush_tlb_page(vaddr,vma)
  173. *
  174. * Invalidate the specified page in the specified address range.
  175. * - vaddr - virtual address (may not be aligned)
  176. * - vma - vma_struct describing address range
  177. *
  178. * flush_kern_tlb_page(kaddr)
  179. *
  180. * Invalidate the TLB entry for the specified page. The address
  181. * will be in the kernels virtual memory space. Current uses
  182. * only require the D-TLB to be invalidated.
  183. * - kaddr - Kernel virtual memory address
  184. */
  185. /*
  186. * We optimise the code below by:
  187. * - building a set of TLB flags that might be set in __cpu_tlb_flags
  188. * - building a set of TLB flags that will always be set in __cpu_tlb_flags
  189. * - if we're going to need __cpu_tlb_flags, access it once and only once
  190. *
  191. * This allows us to build optimal assembly for the single-CPU type case,
  192. * and as close to optimal given the compiler constrants for multi-CPU
  193. * case. We could do better for the multi-CPU case if the compiler
  194. * implemented the "%?" method, but this has been discontinued due to too
  195. * many people getting it wrong.
  196. */
  197. #define possible_tlb_flags (v3_possible_flags | \
  198. v4_possible_flags | \
  199. v4wbi_possible_flags | \
  200. v4wb_possible_flags | \
  201. v6wbi_possible_flags)
  202. #define always_tlb_flags (v3_always_flags & \
  203. v4_always_flags & \
  204. v4wbi_always_flags & \
  205. v4wb_always_flags & \
  206. v6wbi_always_flags)
  207. #define tlb_flag(f) ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
  208. static inline void local_flush_tlb_all(void)
  209. {
  210. const int zero = 0;
  211. const unsigned int __tlb_flag = __cpu_tlb_flags;
  212. if (tlb_flag(TLB_WB))
  213. dsb();
  214. if (tlb_flag(TLB_V3_FULL))
  215. asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
  216. if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
  217. asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
  218. if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
  219. asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
  220. if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
  221. asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
  222. if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
  223. TLB_V6_I_PAGE | TLB_V6_D_PAGE |
  224. TLB_V6_I_ASID | TLB_V6_D_ASID)) {
  225. /* flush the branch target cache */
  226. asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
  227. dsb();
  228. isb();
  229. }
  230. }
  231. static inline void local_flush_tlb_mm(struct mm_struct *mm)
  232. {
  233. const int zero = 0;
  234. const int asid = ASID(mm);
  235. const unsigned int __tlb_flag = __cpu_tlb_flags;
  236. if (tlb_flag(TLB_WB))
  237. dsb();
  238. if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
  239. if (tlb_flag(TLB_V3_FULL))
  240. asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
  241. if (tlb_flag(TLB_V4_U_FULL))
  242. asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
  243. if (tlb_flag(TLB_V4_D_FULL))
  244. asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
  245. if (tlb_flag(TLB_V4_I_FULL))
  246. asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
  247. }
  248. if (tlb_flag(TLB_V6_U_ASID))
  249. asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
  250. if (tlb_flag(TLB_V6_D_ASID))
  251. asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
  252. if (tlb_flag(TLB_V6_I_ASID))
  253. asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
  254. if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
  255. TLB_V6_I_PAGE | TLB_V6_D_PAGE |
  256. TLB_V6_I_ASID | TLB_V6_D_ASID)) {
  257. /* flush the branch target cache */
  258. asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
  259. dsb();
  260. }
  261. }
  262. static inline void
  263. local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
  264. {
  265. const int zero = 0;
  266. const unsigned int __tlb_flag = __cpu_tlb_flags;
  267. uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
  268. if (tlb_flag(TLB_WB))
  269. dsb();
  270. if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
  271. if (tlb_flag(TLB_V3_PAGE))
  272. asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
  273. if (tlb_flag(TLB_V4_U_PAGE))
  274. asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
  275. if (tlb_flag(TLB_V4_D_PAGE))
  276. asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
  277. if (tlb_flag(TLB_V4_I_PAGE))
  278. asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
  279. if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
  280. asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
  281. }
  282. if (tlb_flag(TLB_V6_U_PAGE))
  283. asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
  284. if (tlb_flag(TLB_V6_D_PAGE))
  285. asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
  286. if (tlb_flag(TLB_V6_I_PAGE))
  287. asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
  288. if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
  289. TLB_V6_I_PAGE | TLB_V6_D_PAGE |
  290. TLB_V6_I_ASID | TLB_V6_D_ASID)) {
  291. /* flush the branch target cache */
  292. asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
  293. dsb();
  294. }
  295. }
  296. static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
  297. {
  298. const int zero = 0;
  299. const unsigned int __tlb_flag = __cpu_tlb_flags;
  300. kaddr &= PAGE_MASK;
  301. if (tlb_flag(TLB_WB))
  302. dsb();
  303. if (tlb_flag(TLB_V3_PAGE))
  304. asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
  305. if (tlb_flag(TLB_V4_U_PAGE))
  306. asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
  307. if (tlb_flag(TLB_V4_D_PAGE))
  308. asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
  309. if (tlb_flag(TLB_V4_I_PAGE))
  310. asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
  311. if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
  312. asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
  313. if (tlb_flag(TLB_V6_U_PAGE))
  314. asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
  315. if (tlb_flag(TLB_V6_D_PAGE))
  316. asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
  317. if (tlb_flag(TLB_V6_I_PAGE))
  318. asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
  319. if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
  320. TLB_V6_I_PAGE | TLB_V6_D_PAGE |
  321. TLB_V6_I_ASID | TLB_V6_D_ASID)) {
  322. /* flush the branch target cache */
  323. asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
  324. dsb();
  325. isb();
  326. }
  327. }
  328. /*
  329. * flush_pmd_entry
  330. *
  331. * Flush a PMD entry (word aligned, or double-word aligned) to
  332. * RAM if the TLB for the CPU we are running on requires this.
  333. * This is typically used when we are creating PMD entries.
  334. *
  335. * clean_pmd_entry
  336. *
  337. * Clean (but don't drain the write buffer) if the CPU requires
  338. * these operations. This is typically used when we are removing
  339. * PMD entries.
  340. */
  341. static inline void flush_pmd_entry(pmd_t *pmd)
  342. {
  343. const unsigned int __tlb_flag = __cpu_tlb_flags;
  344. if (tlb_flag(TLB_DCLEAN))
  345. asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
  346. : : "r" (pmd) : "cc");
  347. if (tlb_flag(TLB_WB))
  348. dsb();
  349. }
  350. static inline void clean_pmd_entry(pmd_t *pmd)
  351. {
  352. const unsigned int __tlb_flag = __cpu_tlb_flags;
  353. if (tlb_flag(TLB_DCLEAN))
  354. asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
  355. : : "r" (pmd) : "cc");
  356. }
  357. #undef tlb_flag
  358. #undef always_tlb_flags
  359. #undef possible_tlb_flags
  360. /*
  361. * Convert calls to our calling convention.
  362. */
  363. #define local_flush_tlb_range(vma,start,end) __cpu_flush_user_tlb_range(start,end,vma)
  364. #define local_flush_tlb_kernel_range(s,e) __cpu_flush_kern_tlb_range(s,e)
  365. #ifndef CONFIG_SMP
  366. #define flush_tlb_all local_flush_tlb_all
  367. #define flush_tlb_mm local_flush_tlb_mm
  368. #define flush_tlb_page local_flush_tlb_page
  369. #define flush_tlb_kernel_page local_flush_tlb_kernel_page
  370. #define flush_tlb_range local_flush_tlb_range
  371. #define flush_tlb_kernel_range local_flush_tlb_kernel_range
  372. #else
  373. extern void flush_tlb_all(void);
  374. extern void flush_tlb_mm(struct mm_struct *mm);
  375. extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
  376. extern void flush_tlb_kernel_page(unsigned long kaddr);
  377. extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
  378. extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
  379. #endif
  380. /*
  381. * if PG_dcache_dirty is set for the page, we need to ensure that any
  382. * cache entries for the kernels virtual memory range are written
  383. * back to the page.
  384. */
  385. extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
  386. /*
  387. * ARM processors do not cache TLB tables in RAM.
  388. */
  389. #define flush_tlb_pgtables(mm,start,end) do { } while (0)
  390. #endif
  391. #endif /* CONFIG_MMU */
  392. #endif