system.h 9.6 KB

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  1. #ifndef __ASM_ARM_SYSTEM_H
  2. #define __ASM_ARM_SYSTEM_H
  3. #ifdef __KERNEL__
  4. #include <asm/memory.h>
  5. #define CPU_ARCH_UNKNOWN 0
  6. #define CPU_ARCH_ARMv3 1
  7. #define CPU_ARCH_ARMv4 2
  8. #define CPU_ARCH_ARMv4T 3
  9. #define CPU_ARCH_ARMv5 4
  10. #define CPU_ARCH_ARMv5T 5
  11. #define CPU_ARCH_ARMv5TE 6
  12. #define CPU_ARCH_ARMv5TEJ 7
  13. #define CPU_ARCH_ARMv6 8
  14. /*
  15. * CR1 bits (CP#15 CR1)
  16. */
  17. #define CR_M (1 << 0) /* MMU enable */
  18. #define CR_A (1 << 1) /* Alignment abort enable */
  19. #define CR_C (1 << 2) /* Dcache enable */
  20. #define CR_W (1 << 3) /* Write buffer enable */
  21. #define CR_P (1 << 4) /* 32-bit exception handler */
  22. #define CR_D (1 << 5) /* 32-bit data address range */
  23. #define CR_L (1 << 6) /* Implementation defined */
  24. #define CR_B (1 << 7) /* Big endian */
  25. #define CR_S (1 << 8) /* System MMU protection */
  26. #define CR_R (1 << 9) /* ROM MMU protection */
  27. #define CR_F (1 << 10) /* Implementation defined */
  28. #define CR_Z (1 << 11) /* Implementation defined */
  29. #define CR_I (1 << 12) /* Icache enable */
  30. #define CR_V (1 << 13) /* Vectors relocated to 0xffff0000 */
  31. #define CR_RR (1 << 14) /* Round Robin cache replacement */
  32. #define CR_L4 (1 << 15) /* LDR pc can set T bit */
  33. #define CR_DT (1 << 16)
  34. #define CR_IT (1 << 18)
  35. #define CR_ST (1 << 19)
  36. #define CR_FI (1 << 21) /* Fast interrupt (lower latency mode) */
  37. #define CR_U (1 << 22) /* Unaligned access operation */
  38. #define CR_XP (1 << 23) /* Extended page tables */
  39. #define CR_VE (1 << 24) /* Vectored interrupts */
  40. #define CPUID_ID 0
  41. #define CPUID_CACHETYPE 1
  42. #define CPUID_TCM 2
  43. #define CPUID_TLBTYPE 3
  44. #ifdef CONFIG_CPU_CP15
  45. #define read_cpuid(reg) \
  46. ({ \
  47. unsigned int __val; \
  48. asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
  49. : "=r" (__val) \
  50. : \
  51. : "cc"); \
  52. __val; \
  53. })
  54. #else
  55. #define read_cpuid(reg) (processor_id)
  56. #endif
  57. /*
  58. * This is used to ensure the compiler did actually allocate the register we
  59. * asked it for some inline assembly sequences. Apparently we can't trust
  60. * the compiler from one version to another so a bit of paranoia won't hurt.
  61. * This string is meant to be concatenated with the inline asm string and
  62. * will cause compilation to stop on mismatch.
  63. * (for details, see gcc PR 15089)
  64. */
  65. #define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
  66. #ifndef __ASSEMBLY__
  67. #include <linux/linkage.h>
  68. #include <linux/irqflags.h>
  69. struct thread_info;
  70. struct task_struct;
  71. /* information about the system we're running on */
  72. extern unsigned int system_rev;
  73. extern unsigned int system_serial_low;
  74. extern unsigned int system_serial_high;
  75. extern unsigned int mem_fclk_21285;
  76. struct pt_regs;
  77. void die(const char *msg, struct pt_regs *regs, int err)
  78. __attribute__((noreturn));
  79. struct siginfo;
  80. void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
  81. unsigned long err, unsigned long trap);
  82. void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
  83. struct pt_regs *),
  84. int sig, const char *name);
  85. #define xchg(ptr,x) \
  86. ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
  87. #define tas(ptr) (xchg((ptr),1))
  88. extern asmlinkage void __backtrace(void);
  89. extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
  90. struct mm_struct;
  91. extern void show_pte(struct mm_struct *mm, unsigned long addr);
  92. extern void __show_regs(struct pt_regs *);
  93. extern int cpu_architecture(void);
  94. extern void cpu_init(void);
  95. void arm_machine_restart(char mode);
  96. extern void (*arm_pm_restart)(char str);
  97. /*
  98. * Intel's XScale3 core supports some v6 features (supersections, L2)
  99. * but advertises itself as v5 as it does not support the v6 ISA. For
  100. * this reason, we need a way to explicitly test for this type of CPU.
  101. */
  102. #ifndef CONFIG_CPU_XSC3
  103. #define cpu_is_xsc3() 0
  104. #else
  105. static inline int cpu_is_xsc3(void)
  106. {
  107. extern unsigned int processor_id;
  108. if ((processor_id & 0xffffe000) == 0x69056000)
  109. return 1;
  110. return 0;
  111. }
  112. #endif
  113. #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
  114. #define cpu_is_xscale() 0
  115. #else
  116. #define cpu_is_xscale() 1
  117. #endif
  118. #define UDBG_UNDEFINED (1 << 0)
  119. #define UDBG_SYSCALL (1 << 1)
  120. #define UDBG_BADABORT (1 << 2)
  121. #define UDBG_SEGV (1 << 3)
  122. #define UDBG_BUS (1 << 4)
  123. extern unsigned int user_debug;
  124. #if __LINUX_ARM_ARCH__ >= 4
  125. #define vectors_high() (cr_alignment & CR_V)
  126. #else
  127. #define vectors_high() (0)
  128. #endif
  129. #if defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ >= 6
  130. #define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
  131. : : "r" (0) : "memory")
  132. #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  133. : : "r" (0) : "memory")
  134. #define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
  135. : : "r" (0) : "memory")
  136. #else
  137. #define isb() __asm__ __volatile__ ("" : : : "memory")
  138. #define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
  139. : : "r" (0) : "memory")
  140. #define dmb() __asm__ __volatile__ ("" : : : "memory")
  141. #endif
  142. #ifndef CONFIG_SMP
  143. #define mb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  144. #define rmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  145. #define wmb() do { if (arch_is_coherent()) dmb(); else barrier(); } while (0)
  146. #define smp_mb() barrier()
  147. #define smp_rmb() barrier()
  148. #define smp_wmb() barrier()
  149. #else
  150. #define mb() dmb()
  151. #define rmb() dmb()
  152. #define wmb() dmb()
  153. #define smp_mb() dmb()
  154. #define smp_rmb() dmb()
  155. #define smp_wmb() dmb()
  156. #endif
  157. #define read_barrier_depends() do { } while(0)
  158. #define smp_read_barrier_depends() do { } while(0)
  159. #define set_mb(var, value) do { var = value; smp_mb(); } while (0)
  160. #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
  161. extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
  162. extern unsigned long cr_alignment; /* defined in entry-armv.S */
  163. static inline unsigned int get_cr(void)
  164. {
  165. unsigned int val;
  166. asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc");
  167. return val;
  168. }
  169. static inline void set_cr(unsigned int val)
  170. {
  171. asm volatile("mcr p15, 0, %0, c1, c0, 0 @ set CR"
  172. : : "r" (val) : "cc");
  173. isb();
  174. }
  175. #ifndef CONFIG_SMP
  176. extern void adjust_cr(unsigned long mask, unsigned long set);
  177. #endif
  178. #define CPACC_FULL(n) (3 << (n * 2))
  179. #define CPACC_SVC(n) (1 << (n * 2))
  180. #define CPACC_DISABLE(n) (0 << (n * 2))
  181. static inline unsigned int get_copro_access(void)
  182. {
  183. unsigned int val;
  184. asm("mrc p15, 0, %0, c1, c0, 2 @ get copro access"
  185. : "=r" (val) : : "cc");
  186. return val;
  187. }
  188. static inline void set_copro_access(unsigned int val)
  189. {
  190. asm volatile("mcr p15, 0, %0, c1, c0, 2 @ set copro access"
  191. : : "r" (val) : "cc");
  192. isb();
  193. }
  194. /*
  195. * switch_mm() may do a full cache flush over the context switch,
  196. * so enable interrupts over the context switch to avoid high
  197. * latency.
  198. */
  199. #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
  200. /*
  201. * switch_to(prev, next) should switch from task `prev' to `next'
  202. * `prev' will never be the same as `next'. schedule() itself
  203. * contains the memory barrier to tell GCC not to cache `current'.
  204. */
  205. extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
  206. #define switch_to(prev,next,last) \
  207. do { \
  208. last = __switch_to(prev,task_thread_info(prev), task_thread_info(next)); \
  209. } while (0)
  210. /*
  211. * On SMP systems, when the scheduler does migration-cost autodetection,
  212. * it needs a way to flush as much of the CPU's caches as possible.
  213. *
  214. * TODO: fill this in!
  215. */
  216. static inline void sched_cacheflush(void)
  217. {
  218. }
  219. #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
  220. /*
  221. * On the StrongARM, "swp" is terminally broken since it bypasses the
  222. * cache totally. This means that the cache becomes inconsistent, and,
  223. * since we use normal loads/stores as well, this is really bad.
  224. * Typically, this causes oopsen in filp_close, but could have other,
  225. * more disasterous effects. There are two work-arounds:
  226. * 1. Disable interrupts and emulate the atomic swap
  227. * 2. Clean the cache, perform atomic swap, flush the cache
  228. *
  229. * We choose (1) since its the "easiest" to achieve here and is not
  230. * dependent on the processor type.
  231. *
  232. * NOTE that this solution won't work on an SMP system, so explcitly
  233. * forbid it here.
  234. */
  235. #define swp_is_buggy
  236. #endif
  237. static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
  238. {
  239. extern void __bad_xchg(volatile void *, int);
  240. unsigned long ret;
  241. #ifdef swp_is_buggy
  242. unsigned long flags;
  243. #endif
  244. #if __LINUX_ARM_ARCH__ >= 6
  245. unsigned int tmp;
  246. #endif
  247. switch (size) {
  248. #if __LINUX_ARM_ARCH__ >= 6
  249. case 1:
  250. asm volatile("@ __xchg1\n"
  251. "1: ldrexb %0, [%3]\n"
  252. " strexb %1, %2, [%3]\n"
  253. " teq %1, #0\n"
  254. " bne 1b"
  255. : "=&r" (ret), "=&r" (tmp)
  256. : "r" (x), "r" (ptr)
  257. : "memory", "cc");
  258. break;
  259. case 4:
  260. asm volatile("@ __xchg4\n"
  261. "1: ldrex %0, [%3]\n"
  262. " strex %1, %2, [%3]\n"
  263. " teq %1, #0\n"
  264. " bne 1b"
  265. : "=&r" (ret), "=&r" (tmp)
  266. : "r" (x), "r" (ptr)
  267. : "memory", "cc");
  268. break;
  269. #elif defined(swp_is_buggy)
  270. #ifdef CONFIG_SMP
  271. #error SMP is not supported on this platform
  272. #endif
  273. case 1:
  274. raw_local_irq_save(flags);
  275. ret = *(volatile unsigned char *)ptr;
  276. *(volatile unsigned char *)ptr = x;
  277. raw_local_irq_restore(flags);
  278. break;
  279. case 4:
  280. raw_local_irq_save(flags);
  281. ret = *(volatile unsigned long *)ptr;
  282. *(volatile unsigned long *)ptr = x;
  283. raw_local_irq_restore(flags);
  284. break;
  285. #else
  286. case 1:
  287. asm volatile("@ __xchg1\n"
  288. " swpb %0, %1, [%2]"
  289. : "=&r" (ret)
  290. : "r" (x), "r" (ptr)
  291. : "memory", "cc");
  292. break;
  293. case 4:
  294. asm volatile("@ __xchg4\n"
  295. " swp %0, %1, [%2]"
  296. : "=&r" (ret)
  297. : "r" (x), "r" (ptr)
  298. : "memory", "cc");
  299. break;
  300. #endif
  301. default:
  302. __bad_xchg(ptr, size), ret = 0;
  303. break;
  304. }
  305. return ret;
  306. }
  307. extern void disable_hlt(void);
  308. extern void enable_hlt(void);
  309. #endif /* __ASSEMBLY__ */
  310. #define arch_align_stack(x) (x)
  311. #endif /* __KERNEL__ */
  312. #endif