spinlock.h 4.2 KB

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  1. #ifndef __ASM_SPINLOCK_H
  2. #define __ASM_SPINLOCK_H
  3. #if __LINUX_ARM_ARCH__ < 6
  4. #error SMP not supported on pre-ARMv6 CPUs
  5. #endif
  6. /*
  7. * ARMv6 Spin-locking.
  8. *
  9. * We exclusively read the old value. If it is zero, we may have
  10. * won the lock, so we try exclusively storing it. A memory barrier
  11. * is required after we get a lock, and before we release it, because
  12. * V6 CPUs are assumed to have weakly ordered memory.
  13. *
  14. * Unlocked value: 0
  15. * Locked value: 1
  16. */
  17. #define __raw_spin_is_locked(x) ((x)->lock != 0)
  18. #define __raw_spin_unlock_wait(lock) \
  19. do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
  20. #define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
  21. static inline void __raw_spin_lock(raw_spinlock_t *lock)
  22. {
  23. unsigned long tmp;
  24. __asm__ __volatile__(
  25. "1: ldrex %0, [%1]\n"
  26. " teq %0, #0\n"
  27. #ifdef CONFIG_CPU_32v6K
  28. " wfene\n"
  29. #endif
  30. " strexeq %0, %2, [%1]\n"
  31. " teqeq %0, #0\n"
  32. " bne 1b"
  33. : "=&r" (tmp)
  34. : "r" (&lock->lock), "r" (1)
  35. : "cc");
  36. smp_mb();
  37. }
  38. static inline int __raw_spin_trylock(raw_spinlock_t *lock)
  39. {
  40. unsigned long tmp;
  41. __asm__ __volatile__(
  42. " ldrex %0, [%1]\n"
  43. " teq %0, #0\n"
  44. " strexeq %0, %2, [%1]"
  45. : "=&r" (tmp)
  46. : "r" (&lock->lock), "r" (1)
  47. : "cc");
  48. if (tmp == 0) {
  49. smp_mb();
  50. return 1;
  51. } else {
  52. return 0;
  53. }
  54. }
  55. static inline void __raw_spin_unlock(raw_spinlock_t *lock)
  56. {
  57. smp_mb();
  58. __asm__ __volatile__(
  59. " str %1, [%0]\n"
  60. #ifdef CONFIG_CPU_32v6K
  61. " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
  62. " sev"
  63. #endif
  64. :
  65. : "r" (&lock->lock), "r" (0)
  66. : "cc");
  67. }
  68. /*
  69. * RWLOCKS
  70. *
  71. *
  72. * Write locks are easy - we just set bit 31. When unlocking, we can
  73. * just write zero since the lock is exclusively held.
  74. */
  75. static inline void __raw_write_lock(raw_rwlock_t *rw)
  76. {
  77. unsigned long tmp;
  78. __asm__ __volatile__(
  79. "1: ldrex %0, [%1]\n"
  80. " teq %0, #0\n"
  81. #ifdef CONFIG_CPU_32v6K
  82. " wfene\n"
  83. #endif
  84. " strexeq %0, %2, [%1]\n"
  85. " teq %0, #0\n"
  86. " bne 1b"
  87. : "=&r" (tmp)
  88. : "r" (&rw->lock), "r" (0x80000000)
  89. : "cc");
  90. smp_mb();
  91. }
  92. static inline int __raw_write_trylock(raw_rwlock_t *rw)
  93. {
  94. unsigned long tmp;
  95. __asm__ __volatile__(
  96. "1: ldrex %0, [%1]\n"
  97. " teq %0, #0\n"
  98. " strexeq %0, %2, [%1]"
  99. : "=&r" (tmp)
  100. : "r" (&rw->lock), "r" (0x80000000)
  101. : "cc");
  102. if (tmp == 0) {
  103. smp_mb();
  104. return 1;
  105. } else {
  106. return 0;
  107. }
  108. }
  109. static inline void __raw_write_unlock(raw_rwlock_t *rw)
  110. {
  111. smp_mb();
  112. __asm__ __volatile__(
  113. "str %1, [%0]\n"
  114. #ifdef CONFIG_CPU_32v6K
  115. " mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
  116. " sev\n"
  117. #endif
  118. :
  119. : "r" (&rw->lock), "r" (0)
  120. : "cc");
  121. }
  122. /* write_can_lock - would write_trylock() succeed? */
  123. #define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
  124. /*
  125. * Read locks are a bit more hairy:
  126. * - Exclusively load the lock value.
  127. * - Increment it.
  128. * - Store new lock value if positive, and we still own this location.
  129. * If the value is negative, we've already failed.
  130. * - If we failed to store the value, we want a negative result.
  131. * - If we failed, try again.
  132. * Unlocking is similarly hairy. We may have multiple read locks
  133. * currently active. However, we know we won't have any write
  134. * locks.
  135. */
  136. static inline void __raw_read_lock(raw_rwlock_t *rw)
  137. {
  138. unsigned long tmp, tmp2;
  139. __asm__ __volatile__(
  140. "1: ldrex %0, [%2]\n"
  141. " adds %0, %0, #1\n"
  142. " strexpl %1, %0, [%2]\n"
  143. #ifdef CONFIG_CPU_32v6K
  144. " wfemi\n"
  145. #endif
  146. " rsbpls %0, %1, #0\n"
  147. " bmi 1b"
  148. : "=&r" (tmp), "=&r" (tmp2)
  149. : "r" (&rw->lock)
  150. : "cc");
  151. smp_mb();
  152. }
  153. static inline void __raw_read_unlock(raw_rwlock_t *rw)
  154. {
  155. unsigned long tmp, tmp2;
  156. smp_mb();
  157. __asm__ __volatile__(
  158. "1: ldrex %0, [%2]\n"
  159. " sub %0, %0, #1\n"
  160. " strex %1, %0, [%2]\n"
  161. " teq %1, #0\n"
  162. " bne 1b"
  163. #ifdef CONFIG_CPU_32v6K
  164. "\n cmp %0, #0\n"
  165. " mcreq p15, 0, %0, c7, c10, 4\n"
  166. " seveq"
  167. #endif
  168. : "=&r" (tmp), "=&r" (tmp2)
  169. : "r" (&rw->lock)
  170. : "cc");
  171. }
  172. static inline int __raw_read_trylock(raw_rwlock_t *rw)
  173. {
  174. unsigned long tmp, tmp2 = 1;
  175. __asm__ __volatile__(
  176. "1: ldrex %0, [%2]\n"
  177. " adds %0, %0, #1\n"
  178. " strexpl %1, %0, [%2]\n"
  179. : "=&r" (tmp), "+r" (tmp2)
  180. : "r" (&rw->lock)
  181. : "cc");
  182. smp_mb();
  183. return tmp2 == 0;
  184. }
  185. /* read_can_lock - would read_trylock() succeed? */
  186. #define __raw_read_can_lock(x) ((x)->lock < 0x80000000)
  187. #define _raw_spin_relax(lock) cpu_relax()
  188. #define _raw_read_relax(lock) cpu_relax()
  189. #define _raw_write_relax(lock) cpu_relax()
  190. #endif /* __ASM_SPINLOCK_H */