pgtable.h 14 KB

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  1. /*
  2. * linux/include/asm-arm/pgtable.h
  3. *
  4. * Copyright (C) 1995-2002 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #ifndef _ASMARM_PGTABLE_H
  11. #define _ASMARM_PGTABLE_H
  12. #include <asm-generic/4level-fixup.h>
  13. #include <asm/proc-fns.h>
  14. #ifndef CONFIG_MMU
  15. #include "pgtable-nommu.h"
  16. #else
  17. #include <asm/memory.h>
  18. #include <asm/arch/vmalloc.h>
  19. #include <asm/pgtable-hwdef.h>
  20. /*
  21. * Just any arbitrary offset to the start of the vmalloc VM area: the
  22. * current 8MB value just means that there will be a 8MB "hole" after the
  23. * physical memory until the kernel virtual memory starts. That means that
  24. * any out-of-bounds memory accesses will hopefully be caught.
  25. * The vmalloc() routines leaves a hole of 4kB between each vmalloced
  26. * area for the same reason. ;)
  27. *
  28. * Note that platforms may override VMALLOC_START, but they must provide
  29. * VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
  30. * which may not overlap IO space.
  31. */
  32. #ifndef VMALLOC_START
  33. #define VMALLOC_OFFSET (8*1024*1024)
  34. #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
  35. #endif
  36. /*
  37. * Hardware-wise, we have a two level page table structure, where the first
  38. * level has 4096 entries, and the second level has 256 entries. Each entry
  39. * is one 32-bit word. Most of the bits in the second level entry are used
  40. * by hardware, and there aren't any "accessed" and "dirty" bits.
  41. *
  42. * Linux on the other hand has a three level page table structure, which can
  43. * be wrapped to fit a two level page table structure easily - using the PGD
  44. * and PTE only. However, Linux also expects one "PTE" table per page, and
  45. * at least a "dirty" bit.
  46. *
  47. * Therefore, we tweak the implementation slightly - we tell Linux that we
  48. * have 2048 entries in the first level, each of which is 8 bytes (iow, two
  49. * hardware pointers to the second level.) The second level contains two
  50. * hardware PTE tables arranged contiguously, followed by Linux versions
  51. * which contain the state information Linux needs. We, therefore, end up
  52. * with 512 entries in the "PTE" level.
  53. *
  54. * This leads to the page tables having the following layout:
  55. *
  56. * pgd pte
  57. * | |
  58. * +--------+ +0
  59. * | |-----> +------------+ +0
  60. * +- - - - + +4 | h/w pt 0 |
  61. * | |-----> +------------+ +1024
  62. * +--------+ +8 | h/w pt 1 |
  63. * | | +------------+ +2048
  64. * +- - - - + | Linux pt 0 |
  65. * | | +------------+ +3072
  66. * +--------+ | Linux pt 1 |
  67. * | | +------------+ +4096
  68. *
  69. * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
  70. * PTE_xxx for definitions of bits appearing in the "h/w pt".
  71. *
  72. * PMD_xxx definitions refer to bits in the first level page table.
  73. *
  74. * The "dirty" bit is emulated by only granting hardware write permission
  75. * iff the page is marked "writable" and "dirty" in the Linux PTE. This
  76. * means that a write to a clean page will cause a permission fault, and
  77. * the Linux MM layer will mark the page dirty via handle_pte_fault().
  78. * For the hardware to notice the permission change, the TLB entry must
  79. * be flushed, and ptep_establish() does that for us.
  80. *
  81. * The "accessed" or "young" bit is emulated by a similar method; we only
  82. * allow accesses to the page if the "young" bit is set. Accesses to the
  83. * page will cause a fault, and handle_pte_fault() will set the young bit
  84. * for us as long as the page is marked present in the corresponding Linux
  85. * PTE entry. Again, ptep_establish() will ensure that the TLB is up to
  86. * date.
  87. *
  88. * However, when the "young" bit is cleared, we deny access to the page
  89. * by clearing the hardware PTE. Currently Linux does not flush the TLB
  90. * for us in this case, which means the TLB will retain the transation
  91. * until either the TLB entry is evicted under pressure, or a context
  92. * switch which changes the user space mapping occurs.
  93. */
  94. #define PTRS_PER_PTE 512
  95. #define PTRS_PER_PMD 1
  96. #define PTRS_PER_PGD 2048
  97. /*
  98. * PMD_SHIFT determines the size of the area a second-level page table can map
  99. * PGDIR_SHIFT determines what a third-level page table entry can map
  100. */
  101. #define PMD_SHIFT 21
  102. #define PGDIR_SHIFT 21
  103. #define LIBRARY_TEXT_START 0x0c000000
  104. #ifndef __ASSEMBLY__
  105. extern void __pte_error(const char *file, int line, unsigned long val);
  106. extern void __pmd_error(const char *file, int line, unsigned long val);
  107. extern void __pgd_error(const char *file, int line, unsigned long val);
  108. #define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte_val(pte))
  109. #define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
  110. #define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd_val(pgd))
  111. #endif /* !__ASSEMBLY__ */
  112. #define PMD_SIZE (1UL << PMD_SHIFT)
  113. #define PMD_MASK (~(PMD_SIZE-1))
  114. #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
  115. #define PGDIR_MASK (~(PGDIR_SIZE-1))
  116. /*
  117. * This is the lowest virtual address we can permit any user space
  118. * mapping to be mapped at. This is particularly important for
  119. * non-high vector CPUs.
  120. */
  121. #define FIRST_USER_ADDRESS PAGE_SIZE
  122. #define FIRST_USER_PGD_NR 1
  123. #define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
  124. /*
  125. * section address mask and size definitions.
  126. */
  127. #define SECTION_SHIFT 20
  128. #define SECTION_SIZE (1UL << SECTION_SHIFT)
  129. #define SECTION_MASK (~(SECTION_SIZE-1))
  130. /*
  131. * ARMv6 supersection address mask and size definitions.
  132. */
  133. #define SUPERSECTION_SHIFT 24
  134. #define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
  135. #define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
  136. /*
  137. * "Linux" PTE definitions.
  138. *
  139. * We keep two sets of PTEs - the hardware and the linux version.
  140. * This allows greater flexibility in the way we map the Linux bits
  141. * onto the hardware tables, and allows us to have YOUNG and DIRTY
  142. * bits.
  143. *
  144. * The PTE table pointer refers to the hardware entries; the "Linux"
  145. * entries are stored 1024 bytes below.
  146. */
  147. #define L_PTE_PRESENT (1 << 0)
  148. #define L_PTE_FILE (1 << 1) /* only when !PRESENT */
  149. #define L_PTE_YOUNG (1 << 1)
  150. #define L_PTE_BUFFERABLE (1 << 2) /* matches PTE */
  151. #define L_PTE_CACHEABLE (1 << 3) /* matches PTE */
  152. #define L_PTE_USER (1 << 4)
  153. #define L_PTE_WRITE (1 << 5)
  154. #define L_PTE_EXEC (1 << 6)
  155. #define L_PTE_DIRTY (1 << 7)
  156. #define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
  157. #ifndef __ASSEMBLY__
  158. /*
  159. * The pgprot_* and protection_map entries will be fixed up in runtime
  160. * to include the cachable and bufferable bits based on memory policy,
  161. * as well as any architecture dependent bits like global/ASID and SMP
  162. * shared mapping bits.
  163. */
  164. #define _L_PTE_DEFAULT L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_CACHEABLE | L_PTE_BUFFERABLE
  165. #define _L_PTE_READ L_PTE_USER | L_PTE_EXEC
  166. extern pgprot_t pgprot_user;
  167. extern pgprot_t pgprot_kernel;
  168. #define PAGE_NONE pgprot_user
  169. #define PAGE_COPY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
  170. #define PAGE_SHARED __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ | \
  171. L_PTE_WRITE)
  172. #define PAGE_READONLY __pgprot(pgprot_val(pgprot_user) | _L_PTE_READ)
  173. #define PAGE_KERNEL pgprot_kernel
  174. #define __PAGE_NONE __pgprot(_L_PTE_DEFAULT)
  175. #define __PAGE_COPY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
  176. #define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT | _L_PTE_READ | L_PTE_WRITE)
  177. #define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT | _L_PTE_READ)
  178. #endif /* __ASSEMBLY__ */
  179. /*
  180. * The table below defines the page protection levels that we insert into our
  181. * Linux page table version. These get translated into the best that the
  182. * architecture can perform. Note that on most ARM hardware:
  183. * 1) We cannot do execute protection
  184. * 2) If we could do execute protection, then read is implied
  185. * 3) write implies read permissions
  186. */
  187. #define __P000 __PAGE_NONE
  188. #define __P001 __PAGE_READONLY
  189. #define __P010 __PAGE_COPY
  190. #define __P011 __PAGE_COPY
  191. #define __P100 __PAGE_READONLY
  192. #define __P101 __PAGE_READONLY
  193. #define __P110 __PAGE_COPY
  194. #define __P111 __PAGE_COPY
  195. #define __S000 __PAGE_NONE
  196. #define __S001 __PAGE_READONLY
  197. #define __S010 __PAGE_SHARED
  198. #define __S011 __PAGE_SHARED
  199. #define __S100 __PAGE_READONLY
  200. #define __S101 __PAGE_READONLY
  201. #define __S110 __PAGE_SHARED
  202. #define __S111 __PAGE_SHARED
  203. #ifndef __ASSEMBLY__
  204. /*
  205. * ZERO_PAGE is a global shared page that is always zero: used
  206. * for zero-mapped memory areas etc..
  207. */
  208. extern struct page *empty_zero_page;
  209. #define ZERO_PAGE(vaddr) (empty_zero_page)
  210. #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
  211. #define pfn_pte(pfn,prot) (__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)))
  212. #define pte_none(pte) (!pte_val(pte))
  213. #define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
  214. #define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
  215. #define pte_offset_kernel(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
  216. #define pte_offset_map(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
  217. #define pte_offset_map_nested(dir,addr) (pmd_page_vaddr(*(dir)) + __pte_index(addr))
  218. #define pte_unmap(pte) do { } while (0)
  219. #define pte_unmap_nested(pte) do { } while (0)
  220. #define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
  221. #define set_pte_at(mm,addr,ptep,pteval) do { \
  222. set_pte_ext(ptep, pteval, (addr) >= PAGE_OFFSET ? 0 : PTE_EXT_NG); \
  223. } while (0)
  224. /*
  225. * The following only work if pte_present() is true.
  226. * Undefined behaviour if not..
  227. */
  228. #define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT)
  229. #define pte_read(pte) (pte_val(pte) & L_PTE_USER)
  230. #define pte_write(pte) (pte_val(pte) & L_PTE_WRITE)
  231. #define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC)
  232. #define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
  233. #define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
  234. /*
  235. * The following only works if pte_present() is not true.
  236. */
  237. #define pte_file(pte) (pte_val(pte) & L_PTE_FILE)
  238. #define pte_to_pgoff(x) (pte_val(x) >> 2)
  239. #define pgoff_to_pte(x) __pte(((x) << 2) | L_PTE_FILE)
  240. #define PTE_FILE_MAX_BITS 30
  241. #define PTE_BIT_FUNC(fn,op) \
  242. static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
  243. /*PTE_BIT_FUNC(rdprotect, &= ~L_PTE_USER);*/
  244. /*PTE_BIT_FUNC(mkread, |= L_PTE_USER);*/
  245. PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
  246. PTE_BIT_FUNC(mkwrite, |= L_PTE_WRITE);
  247. PTE_BIT_FUNC(exprotect, &= ~L_PTE_EXEC);
  248. PTE_BIT_FUNC(mkexec, |= L_PTE_EXEC);
  249. PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY);
  250. PTE_BIT_FUNC(mkdirty, |= L_PTE_DIRTY);
  251. PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG);
  252. PTE_BIT_FUNC(mkyoung, |= L_PTE_YOUNG);
  253. /*
  254. * Mark the prot value as uncacheable and unbufferable.
  255. */
  256. #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) & ~(L_PTE_CACHEABLE | L_PTE_BUFFERABLE))
  257. #define pgprot_writecombine(prot) __pgprot(pgprot_val(prot) & ~L_PTE_CACHEABLE)
  258. #define pmd_none(pmd) (!pmd_val(pmd))
  259. #define pmd_present(pmd) (pmd_val(pmd))
  260. #define pmd_bad(pmd) (pmd_val(pmd) & 2)
  261. #define copy_pmd(pmdpd,pmdps) \
  262. do { \
  263. pmdpd[0] = pmdps[0]; \
  264. pmdpd[1] = pmdps[1]; \
  265. flush_pmd_entry(pmdpd); \
  266. } while (0)
  267. #define pmd_clear(pmdp) \
  268. do { \
  269. pmdp[0] = __pmd(0); \
  270. pmdp[1] = __pmd(0); \
  271. clean_pmd_entry(pmdp); \
  272. } while (0)
  273. static inline pte_t *pmd_page_vaddr(pmd_t pmd)
  274. {
  275. unsigned long ptr;
  276. ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
  277. ptr += PTRS_PER_PTE * sizeof(void *);
  278. return __va(ptr);
  279. }
  280. #define pmd_page(pmd) virt_to_page(__va(pmd_val(pmd)))
  281. /*
  282. * Permanent address of a page. We never have highmem, so this is trivial.
  283. */
  284. #define pages_to_mb(x) ((x) >> (20 - PAGE_SHIFT))
  285. /*
  286. * Conversion functions: convert a page and protection to a page entry,
  287. * and a page entry and page directory to the page they refer to.
  288. */
  289. #define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
  290. /*
  291. * The "pgd_xxx()" functions here are trivial for a folded two-level
  292. * setup: the pgd is never bad, and a pmd always exists (as it's folded
  293. * into the pgd entry)
  294. */
  295. #define pgd_none(pgd) (0)
  296. #define pgd_bad(pgd) (0)
  297. #define pgd_present(pgd) (1)
  298. #define pgd_clear(pgdp) do { } while (0)
  299. #define set_pgd(pgd,pgdp) do { } while (0)
  300. /* to find an entry in a page-table-directory */
  301. #define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
  302. #define pgd_offset(mm, addr) ((mm)->pgd+pgd_index(addr))
  303. /* to find an entry in a kernel page-table-directory */
  304. #define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
  305. /* Find an entry in the second-level page table.. */
  306. #define pmd_offset(dir, addr) ((pmd_t *)(dir))
  307. /* Find an entry in the third-level page table.. */
  308. #define __pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
  309. static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
  310. {
  311. const unsigned long mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
  312. pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
  313. return pte;
  314. }
  315. extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
  316. /* Encode and decode a swap entry.
  317. *
  318. * We support up to 32GB of swap on 4k machines
  319. */
  320. #define __swp_type(x) (((x).val >> 2) & 0x7f)
  321. #define __swp_offset(x) ((x).val >> 9)
  322. #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 9) })
  323. #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
  324. #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
  325. /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
  326. /* FIXME: this is not correct */
  327. #define kern_addr_valid(addr) (1)
  328. #include <asm-generic/pgtable.h>
  329. /*
  330. * We provide our own arch_get_unmapped_area to cope with VIPT caches.
  331. */
  332. #define HAVE_ARCH_UNMAPPED_AREA
  333. /*
  334. * remap a physical page `pfn' of size `size' with page protection `prot'
  335. * into virtual address `from'
  336. */
  337. #define io_remap_pfn_range(vma,from,pfn,size,prot) \
  338. remap_pfn_range(vma, from, pfn, size, prot)
  339. #define MK_IOSPACE_PFN(space, pfn) (pfn)
  340. #define GET_IOSPACE(pfn) 0
  341. #define GET_PFN(pfn) (pfn)
  342. #define pgtable_cache_init() do { } while (0)
  343. #endif /* !__ASSEMBLY__ */
  344. #endif /* CONFIG_MMU */
  345. #endif /* _ASMARM_PGTABLE_H */