h3600_gpio.h 34 KB

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  1. /*
  2. *
  3. * Definitions for H3600 Handheld Computer
  4. *
  5. * Copyright 2000 Compaq Computer Corporation.
  6. *
  7. * Use consistent with the GNU GPL is permitted,
  8. * provided that this copyright notice is
  9. * preserved in its entirety in all copies and derived works.
  10. *
  11. * COMPAQ COMPUTER CORPORATION MAKES NO WARRANTIES, EXPRESSED OR IMPLIED,
  12. * AS TO THE USEFULNESS OR CORRECTNESS OF THIS CODE OR ITS
  13. * FITNESS FOR ANY PARTICULAR PURPOSE.
  14. *
  15. * Author: Jamey Hicks.
  16. *
  17. * History:
  18. *
  19. * 2001-10-?? Andrew Christian Added support for iPAQ H3800
  20. *
  21. */
  22. #ifndef _INCLUDE_H3600_GPIO_H_
  23. #define _INCLUDE_H3600_GPIO_H_
  24. /*
  25. * GPIO lines that are common across ALL iPAQ models are in "h3600.h"
  26. * This file contains machine-specific definitions
  27. */
  28. #define GPIO_H3600_SUSPEND GPIO_GPIO (0)
  29. /* GPIO[2:9] used by LCD on H3600/3800, used as GPIO on H3100 */
  30. #define GPIO_H3100_BT_ON GPIO_GPIO (2)
  31. #define GPIO_H3100_GPIO3 GPIO_GPIO (3)
  32. #define GPIO_H3100_QMUTE GPIO_GPIO (4)
  33. #define GPIO_H3100_LCD_3V_ON GPIO_GPIO (5)
  34. #define GPIO_H3100_AUD_ON GPIO_GPIO (6)
  35. #define GPIO_H3100_AUD_PWR_ON GPIO_GPIO (7)
  36. #define GPIO_H3100_IR_ON GPIO_GPIO (8)
  37. #define GPIO_H3100_IR_FSEL GPIO_GPIO (9)
  38. /* for H3600, audio sample rate clock generator */
  39. #define GPIO_H3600_CLK_SET0 GPIO_GPIO (12)
  40. #define GPIO_H3600_CLK_SET1 GPIO_GPIO (13)
  41. #define GPIO_H3600_ACTION_BUTTON GPIO_GPIO (18)
  42. #define GPIO_H3600_SOFT_RESET GPIO_GPIO (20) /* Also known as BATT_FAULT */
  43. #define GPIO_H3600_OPT_LOCK GPIO_GPIO (22)
  44. #define GPIO_H3600_OPT_DET GPIO_GPIO (27)
  45. /* H3800 specific pins */
  46. #define GPIO_H3800_AC_IN GPIO_GPIO (12)
  47. #define GPIO_H3800_COM_DSR GPIO_GPIO (13)
  48. #define GPIO_H3800_MMC_INT GPIO_GPIO (18)
  49. #define GPIO_H3800_NOPT_IND GPIO_GPIO (20) /* Almost exactly the same as GPIO_H3600_OPT_DET */
  50. #define GPIO_H3800_OPT_BAT_FAULT GPIO_GPIO (22)
  51. #define GPIO_H3800_CLK_OUT GPIO_GPIO (27)
  52. /****************************************************/
  53. #define IRQ_GPIO_H3600_ACTION_BUTTON IRQ_GPIO18
  54. #define IRQ_GPIO_H3600_OPT_DET IRQ_GPIO27
  55. #define IRQ_GPIO_H3800_MMC_INT IRQ_GPIO18
  56. #define IRQ_GPIO_H3800_NOPT_IND IRQ_GPIO20 /* almost same as OPT_DET */
  57. /* H3100 / 3600 EGPIO pins */
  58. #define EGPIO_H3600_VPP_ON (1 << 0)
  59. #define EGPIO_H3600_CARD_RESET (1 << 1) /* reset the attached pcmcia/compactflash card. active high. */
  60. #define EGPIO_H3600_OPT_RESET (1 << 2) /* reset the attached option pack. active high. */
  61. #define EGPIO_H3600_CODEC_NRESET (1 << 3) /* reset the onboard UDA1341. active low. */
  62. #define EGPIO_H3600_OPT_NVRAM_ON (1 << 4) /* apply power to optionpack nvram, active high. */
  63. #define EGPIO_H3600_OPT_ON (1 << 5) /* full power to option pack. active high. */
  64. #define EGPIO_H3600_LCD_ON (1 << 6) /* enable 3.3V to LCD. active high. */
  65. #define EGPIO_H3600_RS232_ON (1 << 7) /* UART3 transceiver force on. Active high. */
  66. /* H3600 only EGPIO pins */
  67. #define EGPIO_H3600_LCD_PCI (1 << 8) /* LCD control IC enable. active high. */
  68. #define EGPIO_H3600_IR_ON (1 << 9) /* apply power to IR module. active high. */
  69. #define EGPIO_H3600_AUD_AMP_ON (1 << 10) /* apply power to audio power amp. active high. */
  70. #define EGPIO_H3600_AUD_PWR_ON (1 << 11) /* apply power to reset of audio circuit. active high. */
  71. #define EGPIO_H3600_QMUTE (1 << 12) /* mute control for onboard UDA1341. active high. */
  72. #define EGPIO_H3600_IR_FSEL (1 << 13) /* IR speed select: 1->fast, 0->slow */
  73. #define EGPIO_H3600_LCD_5V_ON (1 << 14) /* enable 5V to LCD. active high. */
  74. #define EGPIO_H3600_LVDD_ON (1 << 15) /* enable 9V and -6.5V to LCD. */
  75. /********************* H3800, ASIC #2 ********************/
  76. #define _H3800_ASIC2_Base (H3600_EGPIO_VIRT)
  77. #define H3800_ASIC2_OFFSET(s,x,y) \
  78. (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
  79. #define H3800_ASIC2_NOFFSET(s,x,n,y) \
  80. (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC2_ ## x ## _ ## n ## _Base + _H3800_ASIC2_ ## x ## _ ## y)))
  81. #define _H3800_ASIC2_GPIO_Base 0x0000
  82. #define _H3800_ASIC2_GPIO_Direction 0x0000 /* R/W, 16 bits 1:input, 0:output */
  83. #define _H3800_ASIC2_GPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */
  84. #define _H3800_ASIC2_GPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */
  85. #define _H3800_ASIC2_GPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */
  86. #define _H3800_ASIC2_GPIO_InterruptClear 0x0010 /* W, 12 bits */
  87. #define _H3800_ASIC2_GPIO_InterruptFlag 0x0010 /* R, 12 bits - reads int status */
  88. #define _H3800_ASIC2_GPIO_Data 0x0014 /* R/W, 16 bits */
  89. #define _H3800_ASIC2_GPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */
  90. #define _H3800_ASIC2_GPIO_InterruptEnable 0x001c /* R/W, 12 bits 1:enable interrupt */
  91. #define _H3800_ASIC2_GPIO_Alternate 0x003c /* R/W, 12+1 bits - set alternate functions */
  92. #define H3800_ASIC2_GPIO_Direction H3800_ASIC2_OFFSET( u16, GPIO, Direction )
  93. #define H3800_ASIC2_GPIO_InterruptType H3800_ASIC2_OFFSET( u16, GPIO, InterruptType )
  94. #define H3800_ASIC2_GPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, GPIO, InterruptEdgeType )
  95. #define H3800_ASIC2_GPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, GPIO, InterruptLevelType )
  96. #define H3800_ASIC2_GPIO_InterruptClear H3800_ASIC2_OFFSET( u16, GPIO, InterruptClear )
  97. #define H3800_ASIC2_GPIO_InterruptFlag H3800_ASIC2_OFFSET( u16, GPIO, InterruptFlag )
  98. #define H3800_ASIC2_GPIO_Data H3800_ASIC2_OFFSET( u16, GPIO, Data )
  99. #define H3800_ASIC2_GPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, GPIO, BattFaultOut )
  100. #define H3800_ASIC2_GPIO_InterruptEnable H3800_ASIC2_OFFSET( u16, GPIO, InterruptEnable )
  101. #define H3800_ASIC2_GPIO_Alternate H3800_ASIC2_OFFSET( u16, GPIO, Alternate )
  102. #define GPIO_H3800_ASIC2_IN_Y1_N (1 << 0) /* Output: Touchscreen Y1 */
  103. #define GPIO_H3800_ASIC2_IN_X0 (1 << 1) /* Output: Touchscreen X0 */
  104. #define GPIO_H3800_ASIC2_IN_Y0 (1 << 2) /* Output: Touchscreen Y0 */
  105. #define GPIO_H3800_ASIC2_IN_X1_N (1 << 3) /* Output: Touchscreen X1 */
  106. #define GPIO_H3800_ASIC2_BT_RST (1 << 4) /* Output: Bluetooth reset */
  107. #define GPIO_H3800_ASIC2_PEN_IRQ (1 << 5) /* Input : Pen down */
  108. #define GPIO_H3800_ASIC2_SD_DETECT (1 << 6) /* Input : SD detect */
  109. #define GPIO_H3800_ASIC2_EAR_IN_N (1 << 7) /* Input : Audio jack plug inserted */
  110. #define GPIO_H3800_ASIC2_OPT_PCM_RESET (1 << 8) /* Output: */
  111. #define GPIO_H3800_ASIC2_OPT_RESET (1 << 9) /* Output: */
  112. #define GPIO_H3800_ASIC2_USB_DETECT_N (1 << 10) /* Input : */
  113. #define GPIO_H3800_ASIC2_SD_CON_SLT (1 << 11) /* Input : */
  114. #define _H3800_ASIC2_KPIO_Base 0x0200
  115. #define _H3800_ASIC2_KPIO_Direction 0x0000 /* R/W, 12 bits 1:input, 0:output */
  116. #define _H3800_ASIC2_KPIO_InterruptType 0x0004 /* R/W, 12 bits 1:edge, 0:level */
  117. #define _H3800_ASIC2_KPIO_InterruptEdgeType 0x0008 /* R/W, 12 bits 1:rising, 0:falling */
  118. #define _H3800_ASIC2_KPIO_InterruptLevelType 0x000C /* R/W, 12 bits 1:high, 0:low */
  119. #define _H3800_ASIC2_KPIO_InterruptClear 0x0010 /* W, 20 bits - 8 special */
  120. #define _H3800_ASIC2_KPIO_InterruptFlag 0x0010 /* R, 20 bits - 8 special - reads int status */
  121. #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */
  122. #define _H3800_ASIC2_KPIO_BattFaultOut 0x0018 /* R/W, 16 bit - sets level on batt fault */
  123. #define _H3800_ASIC2_KPIO_InterruptEnable 0x001c /* R/W, 20 bits - 8 special */
  124. #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */
  125. #define H3800_ASIC2_KPIO_Direction H3800_ASIC2_OFFSET( u16, KPIO, Direction )
  126. #define H3800_ASIC2_KPIO_InterruptType H3800_ASIC2_OFFSET( u16, KPIO, InterruptType )
  127. #define H3800_ASIC2_KPIO_InterruptEdgeType H3800_ASIC2_OFFSET( u16, KPIO, InterruptEdgeType )
  128. #define H3800_ASIC2_KPIO_InterruptLevelType H3800_ASIC2_OFFSET( u16, KPIO, InterruptLevelType )
  129. #define H3800_ASIC2_KPIO_InterruptClear H3800_ASIC2_OFFSET( u32, KPIO, InterruptClear )
  130. #define H3800_ASIC2_KPIO_InterruptFlag H3800_ASIC2_OFFSET( u32, KPIO, InterruptFlag )
  131. #define H3800_ASIC2_KPIO_Data H3800_ASIC2_OFFSET( u16, KPIO, Data )
  132. #define H3800_ASIC2_KPIO_BattFaultOut H3800_ASIC2_OFFSET( u16, KPIO, BattFaultOut )
  133. #define H3800_ASIC2_KPIO_InterruptEnable H3800_ASIC2_OFFSET( u32, KPIO, InterruptEnable )
  134. #define H3800_ASIC2_KPIO_Alternate H3800_ASIC2_OFFSET( u16, KPIO, Alternate )
  135. #define H3800_ASIC2_KPIO_SPI_INT ( 1 << 16 )
  136. #define H3800_ASIC2_KPIO_OWM_INT ( 1 << 17 )
  137. #define H3800_ASIC2_KPIO_ADC_INT ( 1 << 18 )
  138. #define H3800_ASIC2_KPIO_UART_0_INT ( 1 << 19 )
  139. #define H3800_ASIC2_KPIO_UART_1_INT ( 1 << 20 )
  140. #define H3800_ASIC2_KPIO_TIMER_0_INT ( 1 << 21 )
  141. #define H3800_ASIC2_KPIO_TIMER_1_INT ( 1 << 22 )
  142. #define H3800_ASIC2_KPIO_TIMER_2_INT ( 1 << 23 )
  143. #define KPIO_H3800_ASIC2_RECORD_BTN_N (1 << 0) /* Record button */
  144. #define KPIO_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Keypad */
  145. #define KPIO_H3800_ASIC2_KEY_5W2_N (1 << 2) /* */
  146. #define KPIO_H3800_ASIC2_KEY_5W3_N (1 << 3) /* */
  147. #define KPIO_H3800_ASIC2_KEY_5W4_N (1 << 4) /* */
  148. #define KPIO_H3800_ASIC2_KEY_5W5_N (1 << 5) /* */
  149. #define KPIO_H3800_ASIC2_KEY_LEFT_N (1 << 6) /* */
  150. #define KPIO_H3800_ASIC2_KEY_RIGHT_N (1 << 7) /* */
  151. #define KPIO_H3800_ASIC2_KEY_AP1_N (1 << 8) /* Old "Calendar" */
  152. #define KPIO_H3800_ASIC2_KEY_AP2_N (1 << 9) /* Old "Schedule" */
  153. #define KPIO_H3800_ASIC2_KEY_AP3_N (1 << 10) /* Old "Q" */
  154. #define KPIO_H3800_ASIC2_KEY_AP4_N (1 << 11) /* Old "Undo" */
  155. /* Alternate KPIO functions (set by default) */
  156. #define KPIO_ALT_H3800_ASIC2_KEY_5W1_N (1 << 1) /* Action key */
  157. #define KPIO_ALT_H3800_ASIC2_KEY_5W2_N (1 << 2) /* J1 of keypad input */
  158. #define KPIO_ALT_H3800_ASIC2_KEY_5W3_N (1 << 3) /* J2 of keypad input */
  159. #define KPIO_ALT_H3800_ASIC2_KEY_5W4_N (1 << 4) /* J3 of keypad input */
  160. #define KPIO_ALT_H3800_ASIC2_KEY_5W5_N (1 << 5) /* J4 of keypad input */
  161. #define _H3800_ASIC2_SPI_Base 0x0400
  162. #define _H3800_ASIC2_SPI_Control 0x0000 /* R/W 8 bits */
  163. #define _H3800_ASIC2_SPI_Data 0x0004 /* R/W 8 bits */
  164. #define _H3800_ASIC2_SPI_ChipSelectDisabled 0x0008 /* W 8 bits */
  165. #define H3800_ASIC2_SPI_Control H3800_ASIC2_OFFSET( u8, SPI, Control )
  166. #define H3800_ASIC2_SPI_Data H3800_ASIC2_OFFSET( u8, SPI, Data )
  167. #define H3800_ASIC2_SPI_ChipSelectDisabled H3800_ASIC2_OFFSET( u8, SPI, ChipSelectDisabled )
  168. #define _H3800_ASIC2_PWM_0_Base 0x0600
  169. #define _H3800_ASIC2_PWM_1_Base 0x0700
  170. #define _H3800_ASIC2_PWM_TimeBase 0x0000 /* R/W 6 bits */
  171. #define _H3800_ASIC2_PWM_PeriodTime 0x0004 /* R/W 12 bits */
  172. #define _H3800_ASIC2_PWM_DutyTime 0x0008 /* R/W 12 bits */
  173. #define H3800_ASIC2_PWM_0_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 0, TimeBase )
  174. #define H3800_ASIC2_PWM_0_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 0, PeriodTime )
  175. #define H3800_ASIC2_PWM_0_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 0, DutyTime )
  176. #define H3800_ASIC2_PWM_1_TimeBase H3800_ASIC2_NOFFSET( u8, PWM, 1, TimeBase )
  177. #define H3800_ASIC2_PWM_1_PeriodTime H3800_ASIC2_NOFFSET( u16, PWM, 1, PeriodTime )
  178. #define H3800_ASIC2_PWM_1_DutyTime H3800_ASIC2_NOFFSET( u16, PWM, 1, DutyTime )
  179. #define H3800_ASIC2_PWM_TIMEBASE_MASK 0xf /* Low 4 bits sets time base, max = 8 */
  180. #define H3800_ASIC2_PWM_TIMEBASE_ENABLE ( 1 << 4 ) /* Enable clock */
  181. #define H3800_ASIC2_PWM_TIMEBASE_CLEAR ( 1 << 5 ) /* Clear the PWM */
  182. #define _H3800_ASIC2_LED_0_Base 0x0800
  183. #define _H3800_ASIC2_LED_1_Base 0x0880
  184. #define _H3800_ASIC2_LED_2_Base 0x0900
  185. #define _H3800_ASIC2_LED_TimeBase 0x0000 /* R/W 7 bits */
  186. #define _H3800_ASIC2_LED_PeriodTime 0x0004 /* R/W 12 bits */
  187. #define _H3800_ASIC2_LED_DutyTime 0x0008 /* R/W 12 bits */
  188. #define _H3800_ASIC2_LED_AutoStopCount 0x000c /* R/W 16 bits */
  189. #define H3800_ASIC2_LED_0_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 0, TimeBase )
  190. #define H3800_ASIC2_LED_0_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 0, PeriodTime )
  191. #define H3800_ASIC2_LED_0_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 0, DutyTime )
  192. #define H3800_ASIC2_LED_0_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 0, AutoStopClock )
  193. #define H3800_ASIC2_LED_1_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 1, TimeBase )
  194. #define H3800_ASIC2_LED_1_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 1, PeriodTime )
  195. #define H3800_ASIC2_LED_1_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 1, DutyTime )
  196. #define H3800_ASIC2_LED_1_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 1, AutoStopClock )
  197. #define H3800_ASIC2_LED_2_TimeBase H3800_ASIC2_NOFFSET( u8, LED, 2, TimeBase )
  198. #define H3800_ASIC2_LED_2_PeriodTime H3800_ASIC2_NOFFSET( u16, LED, 2, PeriodTime )
  199. #define H3800_ASIC2_LED_2_DutyTime H3800_ASIC2_NOFFSET( u16, LED, 2, DutyTime )
  200. #define H3800_ASIC2_LED_2_AutoStopClock H3800_ASIC2_NOFFSET( u16, LED, 2, AutoStopClock )
  201. #define H3800_ASIC2_LED_TIMEBASE_MASK 0x0f /* Low 4 bits sets time base, max = 13 */
  202. #define H3800_ASIC2_LED_TIMEBASE_BLINK ( 1 << 4 ) /* Enable blinking */
  203. #define H3800_ASIC2_LED_TIMEBASE_AUTOSTOP ( 1 << 5 )
  204. #define H3800_ASIC2_LED_TIMEBASE_ALWAYS ( 1 << 6 ) /* Enable blink always */
  205. #define _H3800_ASIC2_UART_0_Base 0x0A00
  206. #define _H3800_ASIC2_UART_1_Base 0x0C00
  207. #define _H3800_ASIC2_UART_Receive 0x0000 /* R 8 bits */
  208. #define _H3800_ASIC2_UART_Transmit 0x0000 /* W 8 bits */
  209. #define _H3800_ASIC2_UART_IntEnable 0x0004 /* R/W 8 bits */
  210. #define _H3800_ASIC2_UART_IntVerify 0x0008 /* R/W 8 bits */
  211. #define _H3800_ASIC2_UART_FIFOControl 0x000c /* R/W 8 bits */
  212. #define _H3800_ASIC2_UART_LineControl 0x0010 /* R/W 8 bits */
  213. #define _H3800_ASIC2_UART_ModemStatus 0x0014 /* R/W 8 bits */
  214. #define _H3800_ASIC2_UART_LineStatus 0x0018 /* R/W 8 bits */
  215. #define _H3800_ASIC2_UART_ScratchPad 0x001c /* R/W 8 bits */
  216. #define _H3800_ASIC2_UART_DivisorLatchL 0x0020 /* R/W 8 bits */
  217. #define _H3800_ASIC2_UART_DivisorLatchH 0x0024 /* R/W 8 bits */
  218. #define H3800_ASIC2_UART_0_Receive H3800_ASIC2_NOFFSET( u8, UART, 0, Receive )
  219. #define H3800_ASIC2_UART_0_Transmit H3800_ASIC2_NOFFSET( u8, UART, 0, Transmit )
  220. #define H3800_ASIC2_UART_0_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 0, IntEnable )
  221. #define H3800_ASIC2_UART_0_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 0, IntVerify )
  222. #define H3800_ASIC2_UART_0_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 0, FIFOControl )
  223. #define H3800_ASIC2_UART_0_LineControl H3800_ASIC2_NOFFSET( u8, UART, 0, LineControl )
  224. #define H3800_ASIC2_UART_0_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 0, ModemStatus )
  225. #define H3800_ASIC2_UART_0_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 0, LineStatus )
  226. #define H3800_ASIC2_UART_0_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 0, ScratchPad )
  227. #define H3800_ASIC2_UART_0_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchL )
  228. #define H3800_ASIC2_UART_0_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 0, DivisorLatchH )
  229. #define H3800_ASIC2_UART_1_Receive H3800_ASIC2_NOFFSET( u8, UART, 1, Receive )
  230. #define H3800_ASIC2_UART_1_Transmit H3800_ASIC2_NOFFSET( u8, UART, 1, Transmit )
  231. #define H3800_ASIC2_UART_1_IntEnable H3800_ASIC2_NOFFSET( u8, UART, 1, IntEnable )
  232. #define H3800_ASIC2_UART_1_IntVerify H3800_ASIC2_NOFFSET( u8, UART, 1, IntVerify )
  233. #define H3800_ASIC2_UART_1_FIFOControl H3800_ASIC2_NOFFSET( u8, UART, 1, FIFOControl )
  234. #define H3800_ASIC2_UART_1_LineControl H3800_ASIC2_NOFFSET( u8, UART, 1, LineControl )
  235. #define H3800_ASIC2_UART_1_ModemStatus H3800_ASIC2_NOFFSET( u8, UART, 1, ModemStatus )
  236. #define H3800_ASIC2_UART_1_LineStatus H3800_ASIC2_NOFFSET( u8, UART, 1, LineStatus )
  237. #define H3800_ASIC2_UART_1_ScratchPad H3800_ASIC2_NOFFSET( u8, UART, 1, ScratchPad )
  238. #define H3800_ASIC2_UART_1_DivisorLatchL H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchL )
  239. #define H3800_ASIC2_UART_1_DivisorLatchH H3800_ASIC2_NOFFSET( u8, UART, 1, DivisorLatchH )
  240. #define _H3800_ASIC2_TIMER_Base 0x0E00
  241. #define _H3800_ASIC2_TIMER_Command 0x0000 /* R/W 8 bits */
  242. #define H3800_ASIC2_TIMER_Command H3800_ASIC2_OFFSET( u8, Timer, Command )
  243. #define H3800_ASIC2_TIMER_GAT_0 ( 1 << 0 ) /* Gate enable, counter 0 */
  244. #define H3800_ASIC2_TIMER_GAT_1 ( 1 << 1 ) /* Gate enable, counter 1 */
  245. #define H3800_ASIC2_TIMER_GAT_2 ( 1 << 2 ) /* Gate enable, counter 2 */
  246. #define H3800_ASIC2_TIMER_CLK_0 ( 1 << 3 ) /* Clock enable, counter 0 */
  247. #define H3800_ASIC2_TIMER_CLK_1 ( 1 << 4 ) /* Clock enable, counter 1 */
  248. #define H3800_ASIC2_TIMER_CLK_2 ( 1 << 5 ) /* Clock enable, counter 2 */
  249. #define H3800_ASIC2_TIMER_MODE_0 ( 1 << 6 ) /* Mode 0 enable, counter 0 */
  250. #define H3800_ASIC2_TIMER_MODE_1 ( 1 << 7 ) /* Mode 0 enable, counter 1 */
  251. #define _H3800_ASIC2_CLOCK_Base 0x1000
  252. #define _H3800_ASIC2_CLOCK_Enable 0x0000 /* R/W 18 bits */
  253. #define H3800_ASIC2_CLOCK_Enable H3800_ASIC2_OFFSET( u32, CLOCK, Enable )
  254. #define H3800_ASIC2_CLOCK_AUDIO_1 0x0001 /* Enable 4.1 MHz clock for 8Khz and 4khz sample rate */
  255. #define H3800_ASIC2_CLOCK_AUDIO_2 0x0002 /* Enable 12.3 MHz clock for 48Khz and 32khz sample rate */
  256. #define H3800_ASIC2_CLOCK_AUDIO_3 0x0004 /* Enable 5.6 MHz clock for 11 kHZ sample rate */
  257. #define H3800_ASIC2_CLOCK_AUDIO_4 0x0008 /* Enable 11.289 MHz clock for 44 and 22 kHz sample rate */
  258. #define H3800_ASIC2_CLOCK_ADC ( 1 << 4 ) /* 1.024 MHz clock to ADC */
  259. #define H3800_ASIC2_CLOCK_SPI ( 1 << 5 ) /* 4.096 MHz clock to SPI */
  260. #define H3800_ASIC2_CLOCK_OWM ( 1 << 6 ) /* 4.096 MHz clock to OWM */
  261. #define H3800_ASIC2_CLOCK_PWM ( 1 << 7 ) /* 2.048 MHz clock to PWM */
  262. #define H3800_ASIC2_CLOCK_UART_1 ( 1 << 8 ) /* 24.576 MHz clock to UART1 (turn off bit 16) */
  263. #define H3800_ASIC2_CLOCK_UART_0 ( 1 << 9 ) /* 24.576 MHz clock to UART0 (turn off bit 17) */
  264. #define H3800_ASIC2_CLOCK_SD_1 ( 1 << 10 ) /* 16.934 MHz to SD */
  265. #define H3800_ASIC2_CLOCK_SD_2 ( 2 << 10 ) /* 24.576 MHz to SD */
  266. #define H3800_ASIC2_CLOCK_SD_3 ( 3 << 10 ) /* 33.869 MHz to SD */
  267. #define H3800_ASIC2_CLOCK_SD_4 ( 4 << 10 ) /* 49.152 MHz to SD */
  268. #define H3800_ASIC2_CLOCK_EX0 ( 1 << 13 ) /* Enable 32.768 kHz crystal */
  269. #define H3800_ASIC2_CLOCK_EX1 ( 1 << 14 ) /* Enable 24.576 MHz crystal */
  270. #define H3800_ASIC2_CLOCK_EX2 ( 1 << 15 ) /* Enable 33.869 MHz crystal */
  271. #define H3800_ASIC2_CLOCK_SLOW_UART_1 ( 1 << 16 ) /* Enable 3.686 MHz to UART1 (turn off bit 8) */
  272. #define H3800_ASIC2_CLOCK_SLOW_UART_0 ( 1 << 17 ) /* Enable 3.686 MHz to UART0 (turn off bit 9) */
  273. #define _H3800_ASIC2_ADC_Base 0x1200
  274. #define _H3800_ASIC2_ADC_Multiplexer 0x0000 /* R/W 4 bits - low 3 bits set channel */
  275. #define _H3800_ASIC2_ADC_ControlStatus 0x0004 /* R/W 8 bits */
  276. #define _H3800_ASIC2_ADC_Data 0x0008 /* R 10 bits */
  277. #define H3800_ASIC2_ADC_Multiplexer H3800_ASIC2_OFFSET( u8, ADC, Multiplexer )
  278. #define H3800_ASIC2_ADC_ControlStatus H3800_ASIC2_OFFSET( u8, ADC, ControlStatus )
  279. #define H3800_ASIC2_ADC_Data H3800_ASIC2_OFFSET( u16, ADC, Data )
  280. #define H3600_ASIC2_ADC_MUX_CHANNEL_MASK 0x07 /* Low 3 bits sets channel. max = 4 */
  281. #define H3600_ASIC2_ADC_MUX_CLKEN ( 1 << 3 ) /* Enable clock */
  282. #define H3600_ASIC2_ADC_CSR_ADPS_MASK 0x0f /* Low 4 bits sets prescale, max = 8 */
  283. #define H3600_ASIC2_ADC_CSR_FREE_RUN ( 1 << 4 )
  284. #define H3600_ASIC2_ADC_CSR_INT_ENABLE ( 1 << 5 )
  285. #define H3600_ASIC2_ADC_CSR_START ( 1 << 6 ) /* Set to start conversion. Goes to 0 when done */
  286. #define H3600_ASIC2_ADC_CSR_ENABLE ( 1 << 7 ) /* 1:power up ADC, 0:power down */
  287. #define _H3800_ASIC2_INTR_Base 0x1600
  288. #define _H3800_ASIC2_INTR_MaskAndFlag 0x0000 /* R/(W) 8bits */
  289. #define _H3800_ASIC2_INTR_ClockPrescale 0x0004 /* R/(W) 5bits */
  290. #define _H3800_ASIC2_INTR_TimerSet 0x0008 /* R/(W) 8bits */
  291. #define H3800_ASIC2_INTR_MaskAndFlag H3800_ASIC2_OFFSET( u8, INTR, MaskAndFlag )
  292. #define H3800_ASIC2_INTR_ClockPrescale H3800_ASIC2_OFFSET( u8, INTR, ClockPrescale )
  293. #define H3800_ASIC2_INTR_TimerSet H3800_ASIC2_OFFSET( u8, INTR, TimerSet )
  294. #define H3800_ASIC2_INTR_GLOBAL_MASK ( 1 << 0 ) /* Global interrupt mask */
  295. #define H3800_ASIC2_INTR_POWER_ON_RESET ( 1 << 1 ) /* 01: Power on reset (bits 1 & 2 ) */
  296. #define H3800_ASIC2_INTR_EXTERNAL_RESET ( 2 << 1 ) /* 10: External reset (bits 1 & 2 ) */
  297. #define H3800_ASIC2_INTR_MASK_UART_0 ( 1 << 4 )
  298. #define H3800_ASIC2_INTR_MASK_UART_1 ( 1 << 5 )
  299. #define H3800_ASIC2_INTR_MASK_TIMER ( 1 << 6 )
  300. #define H3800_ASIC2_INTR_MASK_OWM ( 1 << 7 )
  301. #define H3800_ASIC2_INTR_CLOCK_PRESCALE 0x0f /* 4 bits, max 14 */
  302. #define H3800_ASIC2_INTR_SET ( 1 << 4 ) /* Time base enable */
  303. #define _H3800_ASIC2_OWM_Base 0x1800
  304. #define _H3800_ASIC2_OWM_Command 0x0000 /* R/W 4 bits command register */
  305. #define _H3800_ASIC2_OWM_Data 0x0004 /* R/W 8 bits, transmit / receive buffer */
  306. #define _H3800_ASIC2_OWM_Interrupt 0x0008 /* R/W Command register */
  307. #define _H3800_ASIC2_OWM_InterruptEnable 0x000c /* R/W Command register */
  308. #define _H3800_ASIC2_OWM_ClockDivisor 0x0010 /* R/W 5 bits of divisor and pre-scale */
  309. #define H3800_ASIC2_OWM_Command H3800_ASIC2_OFFSET( u8, OWM, Command )
  310. #define H3800_ASIC2_OWM_Data H3800_ASIC2_OFFSET( u8, OWM, Data )
  311. #define H3800_ASIC2_OWM_Interrupt H3800_ASIC2_OFFSET( u8, OWM, Interrupt )
  312. #define H3800_ASIC2_OWM_InterruptEnable H3800_ASIC2_OFFSET( u8, OWM, InterruptEnable )
  313. #define H3800_ASIC2_OWM_ClockDivisor H3800_ASIC2_OFFSET( u8, OWM, ClockDivisor )
  314. #define H3800_ASIC2_OWM_CMD_ONE_WIRE_RESET ( 1 << 0 ) /* Set to force reset on 1-wire bus */
  315. #define H3800_ASIC2_OWM_CMD_SRA ( 1 << 1 ) /* Set to switch to Search ROM accelerator mode */
  316. #define H3800_ASIC2_OWM_CMD_DQ_OUTPUT ( 1 << 2 ) /* Write only - forces bus low */
  317. #define H3800_ASIC2_OWM_CMD_DQ_INPUT ( 1 << 3 ) /* Read only - reflects state of bus */
  318. #define H3800_ASIC2_OWM_INT_PD ( 1 << 0 ) /* Presence detect */
  319. #define H3800_ASIC2_OWM_INT_PDR ( 1 << 1 ) /* Presence detect result */
  320. #define H3800_ASIC2_OWM_INT_TBE ( 1 << 2 ) /* Transmit buffer empty */
  321. #define H3800_ASIC2_OWM_INT_TEMT ( 1 << 3 ) /* Transmit shift register empty */
  322. #define H3800_ASIC2_OWM_INT_RBF ( 1 << 4 ) /* Receive buffer full */
  323. #define H3800_ASIC2_OWM_INTEN_EPD ( 1 << 0 ) /* Enable receive buffer full interrupt */
  324. #define H3800_ASIC2_OWM_INTEN_IAS ( 1 << 1 ) /* Enable transmit shift register empty interrupt */
  325. #define H3800_ASIC2_OWM_INTEN_ETBE ( 1 << 2 ) /* Enable transmit buffer empty interrupt */
  326. #define H3800_ASIC2_OWM_INTEN_ETMT ( 1 << 3 ) /* INTR active state */
  327. #define H3800_ASIC2_OWM_INTEN_ERBF ( 1 << 4 ) /* Enable presence detect interrupt */
  328. #define _H3800_ASIC2_FlashCtl_Base 0x1A00
  329. /****************************************************/
  330. /* H3800, ASIC #1
  331. * This ASIC is accesed through ASIC #2, and
  332. * mapped into the 1c00 - 1f00 region
  333. */
  334. #define H3800_ASIC1_OFFSET(s,x,y) \
  335. (*((volatile s *) (_H3800_ASIC2_Base + _H3800_ASIC1_ ## x ## _Base + (_H3800_ASIC1_ ## x ## _ ## y << 1))))
  336. #define _H3800_ASIC1_MMC_Base 0x1c00
  337. #define _H3800_ASIC1_MMC_StartStopClock 0x00 /* R/W 8bit */
  338. #define _H3800_ASIC1_MMC_Status 0x02 /* R See below, default 0x0040 */
  339. #define _H3800_ASIC1_MMC_ClockRate 0x04 /* R/W 8bit, low 3 bits are clock divisor */
  340. #define _H3800_ASIC1_MMC_SPIRegister 0x08 /* R/W 8bit, see below */
  341. #define _H3800_ASIC1_MMC_CmdDataCont 0x0a /* R/W 8bit, write to start MMC adapter */
  342. #define _H3800_ASIC1_MMC_ResponseTimeout 0x0c /* R/W 8bit, clocks before response timeout */
  343. #define _H3800_ASIC1_MMC_ReadTimeout 0x0e /* R/W 16bit, clocks before received data timeout */
  344. #define _H3800_ASIC1_MMC_BlockLength 0x10 /* R/W 10bit */
  345. #define _H3800_ASIC1_MMC_NumOfBlocks 0x12 /* R/W 16bit, in block mode, number of blocks */
  346. #define _H3800_ASIC1_MMC_InterruptMask 0x1a /* R/W 8bit */
  347. #define _H3800_ASIC1_MMC_CommandNumber 0x1c /* R/W 6 bits */
  348. #define _H3800_ASIC1_MMC_ArgumentH 0x1e /* R/W 16 bits */
  349. #define _H3800_ASIC1_MMC_ArgumentL 0x20 /* R/W 16 bits */
  350. #define _H3800_ASIC1_MMC_ResFifo 0x22 /* R 8 x 16 bits - contains response FIFO */
  351. #define _H3800_ASIC1_MMC_BufferPartFull 0x28 /* R/W 8 bits */
  352. #define H3800_ASIC1_MMC_StartStopClock H3800_ASIC1_OFFSET( u8, MMC, StartStopClock )
  353. #define H3800_ASIC1_MMC_Status H3800_ASIC1_OFFSET( u16, MMC, Status )
  354. #define H3800_ASIC1_MMC_ClockRate H3800_ASIC1_OFFSET( u8, MMC, ClockRate )
  355. #define H3800_ASIC1_MMC_SPIRegister H3800_ASIC1_OFFSET( u8, MMC, SPIRegister )
  356. #define H3800_ASIC1_MMC_CmdDataCont H3800_ASIC1_OFFSET( u8, MMC, CmdDataCont )
  357. #define H3800_ASIC1_MMC_ResponseTimeout H3800_ASIC1_OFFSET( u8, MMC, ResponseTimeout )
  358. #define H3800_ASIC1_MMC_ReadTimeout H3800_ASIC1_OFFSET( u16, MMC, ReadTimeout )
  359. #define H3800_ASIC1_MMC_BlockLength H3800_ASIC1_OFFSET( u16, MMC, BlockLength )
  360. #define H3800_ASIC1_MMC_NumOfBlocks H3800_ASIC1_OFFSET( u16, MMC, NumOfBlocks )
  361. #define H3800_ASIC1_MMC_InterruptMask H3800_ASIC1_OFFSET( u8, MMC, InterruptMask )
  362. #define H3800_ASIC1_MMC_CommandNumber H3800_ASIC1_OFFSET( u8, MMC, CommandNumber )
  363. #define H3800_ASIC1_MMC_ArgumentH H3800_ASIC1_OFFSET( u16, MMC, ArgumentH )
  364. #define H3800_ASIC1_MMC_ArgumentL H3800_ASIC1_OFFSET( u16, MMC, ArgumentL )
  365. #define H3800_ASIC1_MMC_ResFifo H3800_ASIC1_OFFSET( u16, MMC, ResFifo )
  366. #define H3800_ASIC1_MMC_BufferPartFull H3800_ASIC1_OFFSET( u8, MMC, BufferPartFull )
  367. #define H3800_ASIC1_MMC_STOP_CLOCK (1 << 0) /* Write to "StartStopClock" register */
  368. #define H3800_ASIC1_MMC_START_CLOCK (1 << 1)
  369. #define H3800_ASIC1_MMC_STATUS_READ_TIMEOUT (1 << 0)
  370. #define H3800_ASIC1_MMC_STATUS_RESPONSE_TIMEOUT (1 << 1)
  371. #define H3800_ASIC1_MMC_STATUS_CRC_WRITE_ERROR (1 << 2)
  372. #define H3800_ASIC1_MMC_STATUS_CRC_READ_ERROR (1 << 3)
  373. #define H3800_ASIC1_MMC_STATUS_SPI_READ_ERROR (1 << 4) /* SPI data token error received */
  374. #define H3800_ASIC1_MMC_STATUS_CRC_RESPONSE_ERROR (1 << 5)
  375. #define H3800_ASIC1_MMC_STATUS_FIFO_EMPTY (1 << 6)
  376. #define H3800_ASIC1_MMC_STATUS_FIFO_FULL (1 << 7)
  377. #define H3800_ASIC1_MMC_STATUS_CLOCK_ENABLE (1 << 8) /* MultiMediaCard clock stopped */
  378. #define H3800_ASIC1_MMC_STATUS_DATA_TRANSFER_DONE (1 << 11) /* Write operation, indicates transfer finished */
  379. #define H3800_ASIC1_MMC_STATUS_END_PROGRAM (1 << 12) /* End write and read operations */
  380. #define H3800_ASIC1_MMC_STATUS_END_COMMAND_RESPONSE (1 << 13) /* End command response */
  381. #define H3800_ASIC1_MMC_SPI_REG_SPI_ENABLE (1 << 0) /* Enables SPI mode */
  382. #define H3800_ASIC1_MMC_SPI_REG_CRC_ON (1 << 1) /* 1:turn on CRC */
  383. #define H3800_ASIC1_MMC_SPI_REG_SPI_CS_ENABLE (1 << 2) /* 1:turn on SPI CS */
  384. #define H3800_ASIC1_MMC_SPI_REG_CS_ADDRESS_MASK 0x38 /* Bits 3,4,5 are the SPI CS relative address */
  385. #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_NO_RESPONSE 0x00
  386. #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R1 0x01
  387. #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R2 0x02
  388. #define H3800_ASIC1_MMC_CMD_DATA_CONT_FORMAT_R3 0x03
  389. #define H3800_ASIC1_MMC_CMD_DATA_CONT_DATA_ENABLE (1 << 2) /* This command contains a data transfer */
  390. #define H3800_ASIC1_MMC_CMD_DATA_CONT_WRITE (1 << 3) /* This data transfer is a write */
  391. #define H3800_ASIC1_MMC_CMD_DATA_CONT_STREAM_MODE (1 << 4) /* This data transfer is in stream mode */
  392. #define H3800_ASIC1_MMC_CMD_DATA_CONT_BUSY_BIT (1 << 5) /* Busy signal expected after current cmd */
  393. #define H3800_ASIC1_MMC_CMD_DATA_CONT_INITIALIZE (1 << 6) /* Enables the 80 bits for initializing card */
  394. #define H3800_ASIC1_MMC_INT_MASK_DATA_TRANSFER_DONE (1 << 0)
  395. #define H3800_ASIC1_MMC_INT_MASK_PROGRAM_DONE (1 << 1)
  396. #define H3800_ASIC1_MMC_INT_MASK_END_COMMAND_RESPONSE (1 << 2)
  397. #define H3800_ASIC1_MMC_INT_MASK_BUFFER_READY (1 << 3)
  398. #define H3800_ASIC1_MMC_BUFFER_PART_FULL (1 << 0)
  399. /********* GPIO **********/
  400. #define _H3800_ASIC1_GPIO_Base 0x1e00
  401. #define _H3800_ASIC1_GPIO_Mask 0x30 /* R/W 0:don't mask, 1:mask interrupt */
  402. #define _H3800_ASIC1_GPIO_Direction 0x32 /* R/W 0:input, 1:output */
  403. #define _H3800_ASIC1_GPIO_Out 0x34 /* R/W 0:output low, 1:output high */
  404. #define _H3800_ASIC1_GPIO_TriggerType 0x36 /* R/W 0:level, 1:edge */
  405. #define _H3800_ASIC1_GPIO_EdgeTrigger 0x38 /* R/W 0:falling, 1:rising */
  406. #define _H3800_ASIC1_GPIO_LevelTrigger 0x3A /* R/W 0:low, 1:high level detect */
  407. #define _H3800_ASIC1_GPIO_LevelStatus 0x3C /* R/W 0:none, 1:detect */
  408. #define _H3800_ASIC1_GPIO_EdgeStatus 0x3E /* R/W 0:none, 1:detect */
  409. #define _H3800_ASIC1_GPIO_State 0x40 /* R See masks below (default 0) */
  410. #define _H3800_ASIC1_GPIO_Reset 0x42 /* R/W See masks below (default 0x04) */
  411. #define _H3800_ASIC1_GPIO_SleepMask 0x44 /* R/W 0:don't mask, 1:mask trigger in sleep mode */
  412. #define _H3800_ASIC1_GPIO_SleepDir 0x46 /* R/W direction 0:input, 1:output in sleep mode */
  413. #define _H3800_ASIC1_GPIO_SleepOut 0x48 /* R/W level 0:low, 1:high in sleep mode */
  414. #define _H3800_ASIC1_GPIO_Status 0x4A /* R Pin status */
  415. #define _H3800_ASIC1_GPIO_BattFaultDir 0x4C /* R/W direction 0:input, 1:output in batt_fault */
  416. #define _H3800_ASIC1_GPIO_BattFaultOut 0x4E /* R/W level 0:low, 1:high in batt_fault */
  417. #define H3800_ASIC1_GPIO_Mask H3800_ASIC1_OFFSET( u16, GPIO, Mask )
  418. #define H3800_ASIC1_GPIO_Direction H3800_ASIC1_OFFSET( u16, GPIO, Direction )
  419. #define H3800_ASIC1_GPIO_Out H3800_ASIC1_OFFSET( u16, GPIO, Out )
  420. #define H3800_ASIC1_GPIO_TriggerType H3800_ASIC1_OFFSET( u16, GPIO, TriggerType )
  421. #define H3800_ASIC1_GPIO_EdgeTrigger H3800_ASIC1_OFFSET( u16, GPIO, EdgeTrigger )
  422. #define H3800_ASIC1_GPIO_LevelTrigger H3800_ASIC1_OFFSET( u16, GPIO, LevelTrigger )
  423. #define H3800_ASIC1_GPIO_LevelStatus H3800_ASIC1_OFFSET( u16, GPIO, LevelStatus )
  424. #define H3800_ASIC1_GPIO_EdgeStatus H3800_ASIC1_OFFSET( u16, GPIO, EdgeStatus )
  425. #define H3800_ASIC1_GPIO_State H3800_ASIC1_OFFSET( u8, GPIO, State )
  426. #define H3800_ASIC1_GPIO_Reset H3800_ASIC1_OFFSET( u8, GPIO, Reset )
  427. #define H3800_ASIC1_GPIO_SleepMask H3800_ASIC1_OFFSET( u16, GPIO, SleepMask )
  428. #define H3800_ASIC1_GPIO_SleepDir H3800_ASIC1_OFFSET( u16, GPIO, SleepDir )
  429. #define H3800_ASIC1_GPIO_SleepOut H3800_ASIC1_OFFSET( u16, GPIO, SleepOut )
  430. #define H3800_ASIC1_GPIO_Status H3800_ASIC1_OFFSET( u16, GPIO, Status )
  431. #define H3800_ASIC1_GPIO_BattFaultDir H3800_ASIC1_OFFSET( u16, GPIO, BattFaultDir )
  432. #define H3800_ASIC1_GPIO_BattFaultOut H3800_ASIC1_OFFSET( u16, GPIO, BattFaultOut )
  433. #define H3800_ASIC1_GPIO_STATE_MASK (1 << 0)
  434. #define H3800_ASIC1_GPIO_STATE_DIRECTION (1 << 1)
  435. #define H3800_ASIC1_GPIO_STATE_OUT (1 << 2)
  436. #define H3800_ASIC1_GPIO_STATE_TRIGGER_TYPE (1 << 3)
  437. #define H3800_ASIC1_GPIO_STATE_EDGE_TRIGGER (1 << 4)
  438. #define H3800_ASIC1_GPIO_STATE_LEVEL_TRIGGER (1 << 5)
  439. #define H3800_ASIC1_GPIO_RESET_SOFTWARE (1 << 0)
  440. #define H3800_ASIC1_GPIO_RESET_AUTO_SLEEP (1 << 1)
  441. #define H3800_ASIC1_GPIO_RESET_FIRST_PWR_ON (1 << 2)
  442. /* These are all outputs */
  443. #define GPIO_H3800_ASIC1_IR_ON_N (1 << 0) /* Apply power to the IR Module */
  444. #define GPIO_H3800_ASIC1_SD_PWR_ON (1 << 1) /* Secure Digital power on */
  445. #define GPIO_H3800_ASIC1_RS232_ON (1 << 2) /* Turn on power to the RS232 chip ? */
  446. #define GPIO_H3800_ASIC1_PULSE_GEN (1 << 3) /* Goes to speaker / earphone */
  447. #define GPIO_H3800_ASIC1_CH_TIMER (1 << 4) /* */
  448. #define GPIO_H3800_ASIC1_LCD_5V_ON (1 << 5) /* Enables LCD_5V */
  449. #define GPIO_H3800_ASIC1_LCD_ON (1 << 6) /* Enables LCD_3V */
  450. #define GPIO_H3800_ASIC1_LCD_PCI (1 << 7) /* Connects to PDWN on LCD controller */
  451. #define GPIO_H3800_ASIC1_VGH_ON (1 << 8) /* Drives VGH on the LCD (+9??) */
  452. #define GPIO_H3800_ASIC1_VGL_ON (1 << 9) /* Drivers VGL on the LCD (-6??) */
  453. #define GPIO_H3800_ASIC1_FL_PWR_ON (1 << 10) /* Frontlight power on */
  454. #define GPIO_H3800_ASIC1_BT_PWR_ON (1 << 11) /* Bluetooth power on */
  455. #define GPIO_H3800_ASIC1_SPK_ON (1 << 12) /* */
  456. #define GPIO_H3800_ASIC1_EAR_ON_N (1 << 13) /* */
  457. #define GPIO_H3800_ASIC1_AUD_PWR_ON (1 << 14) /* */
  458. /* Write enable for the flash */
  459. #define _H3800_ASIC1_FlashWP_Base 0x1F00
  460. #define _H3800_ASIC1_FlashWP_VPP_ON 0x00 /* R 1: write, 0: protect */
  461. #define H3800_ASIC1_FlashWP_VPP_ON H3800_ASIC1_OFFSET( u8, FlashWP, VPP_ON )
  462. #endif /* _INCLUDE_H3600_GPIO_H_ */