SA-1101.h 30 KB

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  1. /*
  2. * SA-1101.h
  3. *
  4. * Copyright (c) Peter Danielsson 1999
  5. *
  6. * Definition of constants related to the sa1101
  7. * support chip for the sa1100
  8. *
  9. */
  10. /* Be sure that virtual mapping is defined right */
  11. #ifndef __ASM_ARCH_HARDWARE_H
  12. #error You must include hardware.h not SA-1101.h
  13. #endif
  14. #ifndef SA1101_BASE
  15. #error You must define SA-1101 physical base address
  16. #endif
  17. #ifndef LANGUAGE
  18. # ifdef __ASSEMBLY__
  19. # define LANGUAGE Assembly
  20. # else
  21. # define LANGUAGE C
  22. # endif
  23. #endif
  24. /*
  25. * We have mapped the sa1101 depending on the value of SA1101_BASE.
  26. * It then appears from 0xf4000000.
  27. */
  28. #define SA1101_p2v( x ) ((x) - SA1101_BASE + 0xf4000000)
  29. #define SA1101_v2p( x ) ((x) - 0xf4000000 + SA1101_BASE)
  30. #ifndef SA1101_p2v
  31. #define SA1101_p2v(PhAdd) (PhAdd)
  32. #endif
  33. #include <asm/arch/bitfield.h>
  34. #define C 0
  35. #define Assembly 1
  36. /*
  37. * Memory map
  38. */
  39. #define __SHMEM_CONTROL0 0x00000000
  40. #define __SYSTEM_CONTROL1 0x00000400
  41. #define __ARBITER 0x00020000
  42. #define __SYSTEM_CONTROL2 0x00040000
  43. #define __SYSTEM_CONTROL3 0x00060000
  44. #define __PARALLEL_PORT 0x00080000
  45. #define __VIDMEM_CONTROL 0x00100000
  46. #define __UPDATE_FIFO 0x00120000
  47. #define __SHMEM_CONTROL1 0x00140000
  48. #define __INTERRUPT_CONTROL 0x00160000
  49. #define __USB_CONTROL 0x00180000
  50. #define __TRACK_INTERFACE 0x001a0000
  51. #define __MOUSE_INTERFACE 0x001b0000
  52. #define __KEYPAD_INTERFACE 0x001c0000
  53. #define __PCMCIA_INTERFACE 0x001e0000
  54. #define __VGA_CONTROL 0x00200000
  55. #define __GPIO_INTERFACE 0x00300000
  56. /*
  57. * Macro that calculates real address for registers in the SA-1101
  58. */
  59. #define _SA1101( x ) ((x) + SA1101_BASE)
  60. /*
  61. * Interface and shared memory controller registers
  62. *
  63. * Registers
  64. * SKCR SA-1101 control register (read/write)
  65. * SMCR Shared Memory Controller Register
  66. * SNPR Snoop Register
  67. */
  68. #define _SKCR _SA1101( 0x00000000 ) /* SA-1101 Control Reg. */
  69. #define _SMCR _SA1101( 0x00140000 ) /* Shared Mem. Control Reg. */
  70. #define _SNPR _SA1101( 0x00140400 ) /* Snoop Reg. */
  71. #if LANGUAGE == C
  72. #define SKCR (*((volatile Word *) SA1101_p2v (_SKCR)))
  73. #define SMCR (*((volatile Word *) SA1101_p2v (_SMCR)))
  74. #define SNPR (*((volatile Word *) SA1101_p2v (_SNPR)))
  75. #define SKCR_PLLEn 0x0001 /* Enable On-Chip PLL */
  76. #define SKCR_BCLKEn 0x0002 /* Enables BCLK */
  77. #define SKCR_Sleep 0x0004 /* Sleep Mode */
  78. #define SKCR_IRefEn 0x0008 /* DAC Iref input enable */
  79. #define SKCR_VCOON 0x0010 /* VCO bias */
  80. #define SKCR_ScanTestEn 0x0020 /* Enables scan test */
  81. #define SKCR_ClockTestEn 0x0040 /* Enables clock test */
  82. #define SMCR_DCAC Fld(2,0) /* Number of column address bits */
  83. #define SMCR_DRAC Fld(2,2) /* Number of row address bits */
  84. #define SMCR_ArbiterBias 0x0008 /* favor video or USB */
  85. #define SMCR_TopVidMem Fld(4,5) /* Top 4 bits of vidmem addr. */
  86. #define SMCR_ColAdrBits( x ) /* col. addr bits 8..11 */ \
  87. (( (x) - 8 ) << FShft (SMCR_DCAC))
  88. #define SMCR_RowAdrBits( x ) /* row addr bits 9..12 */\
  89. (( (x) - 9 ) << FShft (SMCR_DRAC)
  90. #define SNPR_VFBstart Fld(12,0) /* Video frame buffer addr */
  91. #define SNPR_VFBsize Fld(11,12) /* Video frame buffer size */
  92. #define SNPR_WholeBank (1 << 23) /* Whole bank bit */
  93. #define SNPR_BankSelect Fld(2,27) /* Bank select */
  94. #define SNPR_SnoopEn (1 << 31) /* Enable snoop operation */
  95. #define SNPR_Set_VFBsize( x ) /* set frame buffer size (in kb) */ \
  96. ( (x) << FShft (SNPR_VFBsize))
  97. #define SNPR_Select_Bank(x) /* select bank 0 or 1 */ \
  98. (( (x) + 1 ) << FShft (SNPR_BankSelect ))
  99. #endif /* LANGUAGE == C */
  100. /*
  101. * Video Memory Controller
  102. *
  103. * Registers
  104. * VMCCR Configuration register
  105. * VMCAR VMC address register
  106. * VMCDR VMC data register
  107. *
  108. */
  109. #define _VMCCR _SA1101( 0x00100000 ) /* Configuration register */
  110. #define _VMCAR _SA1101( 0x00101000 ) /* VMC address register */
  111. #define _VMCDR _SA1101( 0x00101400 ) /* VMC data register */
  112. #if LANGUAGE == C
  113. #define VMCCR (*((volatile Word *) SA1101_p2v (_VMCCR)))
  114. #define VMCAR (*((volatile Word *) SA1101_p2v (_VMCAR)))
  115. #define VMCDR (*((volatile Word *) SA1101_p2v (_VMCDR)))
  116. #define VMCCR_RefreshEn 0x0000 /* Enable memory refresh */
  117. #define VMCCR_Config 0x0001 /* DRAM size */
  118. #define VMCCR_RefPeriod Fld(2,3) /* Refresh period */
  119. #define VMCCR_StaleDataWait Fld(4,5) /* Stale FIFO data timeout counter */
  120. #define VMCCR_SleepState (1<<9) /* State of interface pins in sleep*/
  121. #define VMCCR_RefTest (1<<10) /* refresh test */
  122. #define VMCCR_RefLow Fld(6,11) /* refresh low counter */
  123. #define VMCCR_RefHigh Fld(7,17) /* refresh high counter */
  124. #define VMCCR_SDTCTest Fld(7,24) /* stale data timeout counter */
  125. #define VMCCR_ForceSelfRef (1<<31) /* Force self refresh */
  126. #endif LANGUAGE == C
  127. /* Update FIFO
  128. *
  129. * Registers
  130. * UFCR Update FIFO Control Register
  131. * UFSR Update FIFO Status Register
  132. * UFLVLR update FIFO level register
  133. * UFDR update FIFO data register
  134. */
  135. #define _UFCR _SA1101(0x00120000) /* Update FIFO Control Reg. */
  136. #define _UFSR _SA1101(0x00120400) /* Update FIFO Status Reg. */
  137. #define _UFLVLR _SA1101(0x00120800) /* Update FIFO level reg. */
  138. #define _UFDR _SA1101(0x00120c00) /* Update FIFO data reg. */
  139. #if LANGUAGE == C
  140. #define UFCR (*((volatile Word *) SA1101_p2v (_UFCR)))
  141. #define UFSR (*((volatile Word *) SA1101_p2v (_UFSR)))
  142. #define UFLVLR (*((volatile Word *) SA1101_p2v (_UFLVLR)))
  143. #define UFDR (*((volatile Word *) SA1101_p2v (_UFDR)))
  144. #define UFCR_FifoThreshhold Fld(7,0) /* Level for FifoGTn flag */
  145. #define UFSR_FifoGTnFlag 0x01 /* FifoGTn flag */#define UFSR_FifoEmpty 0x80 /* FIFO is empty */
  146. #endif /* LANGUAGE == C */
  147. /* System Controller
  148. *
  149. * Registers
  150. * SKPCR Power Control Register
  151. * SKCDR Clock Divider Register
  152. * DACDR1 DAC1 Data register
  153. * DACDR2 DAC2 Data register
  154. */
  155. #define _SKPCR _SA1101(0x00000400)
  156. #define _SKCDR _SA1101(0x00040000)
  157. #define _DACDR1 _SA1101(0x00060000)
  158. #define _DACDR2 _SA1101(0x00060400)
  159. #if LANGUAGE == C
  160. #define SKPCR (*((volatile Word *) SA1101_p2v (_SKPCR)))
  161. #define SKCDR (*((volatile Word *) SA1101_p2v (_SKCDR)))
  162. #define DACDR1 (*((volatile Word *) SA1101_p2v (_DACDR1)))
  163. #define DACDR2 (*((volatile Word *) SA1101_p2v (_DACDR2)))
  164. #define SKPCR_UCLKEn 0x01 /* USB Enable */
  165. #define SKPCR_PCLKEn 0x02 /* PS/2 Enable */
  166. #define SKPCR_ICLKEn 0x04 /* Interrupt Controller Enable */
  167. #define SKPCR_VCLKEn 0x08 /* Video Controller Enable */
  168. #define SKPCR_PICLKEn 0x10 /* parallel port Enable */
  169. #define SKPCR_DCLKEn 0x20 /* DACs Enable */
  170. #define SKPCR_nKPADEn 0x40 /* Multiplexer */
  171. #define SKCDR_PLLMul Fld(7,0) /* PLL Multiplier */
  172. #define SKCDR_VCLKEn Fld(2,7) /* Video controller clock divider */
  173. #define SKDCR_BCLKEn (1<<9) /* BCLK Divider */
  174. #define SKDCR_UTESTCLKEn (1<<10) /* Route USB clock during test mode */
  175. #define SKDCR_DivRValue Fld(6,11) /* Input clock divider for PLL */
  176. #define SKDCR_DivNValue Fld(5,17) /* Output clock divider for PLL */
  177. #define SKDCR_PLLRSH Fld(3,22) /* PLL bandwidth control */
  178. #define SKDCR_ChargePump (1<<25) /* Charge pump control */
  179. #define SKDCR_ClkTestMode (1<<26) /* Clock output test mode */
  180. #define SKDCR_ClkTestEn (1<<27) /* Test clock generator */
  181. #define SKDCR_ClkJitterCntl Fld(3,28) /* video clock jitter compensation */
  182. #define DACDR_DACCount Fld(8,0) /* Count value */
  183. #define DACDR1_DACCount DACDR_DACCount
  184. #define DACDR2_DACCount DACDR_DACCount
  185. #endif /* LANGUAGE == C */
  186. /*
  187. * Parallel Port Interface
  188. *
  189. * Registers
  190. * IEEE_Config IEEE mode selection and programmable attributes
  191. * IEEE_Control Controls the states of IEEE port control outputs
  192. * IEEE_Data Forward transfer data register
  193. * IEEE_Addr Forward transfer address register
  194. * IEEE_Status Port IO signal status register
  195. * IEEE_IntStatus Port interrupts status register
  196. * IEEE_FifoLevels Rx and Tx FIFO interrupt generation levels
  197. * IEEE_InitTime Forward timeout counter initial value
  198. * IEEE_TimerStatus Forward timeout counter current value
  199. * IEEE_FifoReset Reset forward transfer FIFO
  200. * IEEE_ReloadValue Counter reload value
  201. * IEEE_TestControl Control testmode
  202. * IEEE_TestDataIn Test data register
  203. * IEEE_TestDataInEn Enable test data
  204. * IEEE_TestCtrlIn Test control signals
  205. * IEEE_TestCtrlInEn Enable test control signals
  206. * IEEE_TestDataStat Current data bus value
  207. *
  208. */
  209. /*
  210. * The control registers are defined as offsets from a base address
  211. */
  212. #define _IEEE( x ) _SA1101( (x) + __PARALLEL_PORT )
  213. #define _IEEE_Config _IEEE( 0x0000 )
  214. #define _IEEE_Control _IEEE( 0x0400 )
  215. #define _IEEE_Data _IEEE( 0x4000 )
  216. #define _IEEE_Addr _IEEE( 0x0800 )
  217. #define _IEEE_Status _IEEE( 0x0c00 )
  218. #define _IEEE_IntStatus _IEEE( 0x1000 )
  219. #define _IEEE_FifoLevels _IEEE( 0x1400 )
  220. #define _IEEE_InitTime _IEEE( 0x1800 )
  221. #define _IEEE_TimerStatus _IEEE( 0x1c00 )
  222. #define _IEEE_FifoReset _IEEE( 0x2000 )
  223. #define _IEEE_ReloadValue _IEEE( 0x3c00 )
  224. #define _IEEE_TestControl _IEEE( 0x2400 )
  225. #define _IEEE_TestDataIn _IEEE( 0x2800 )
  226. #define _IEEE_TestDataInEn _IEEE( 0x2c00 )
  227. #define _IEEE_TestCtrlIn _IEEE( 0x3000 )
  228. #define _IEEE_TestCtrlInEn _IEEE( 0x3400 )
  229. #define _IEEE_TestDataStat _IEEE( 0x3800 )
  230. #if LANGUAGE == C
  231. #define IEEE_Config (*((volatile Word *) SA1101_p2v (_IEEE_Config)))
  232. #define IEEE_Control (*((volatile Word *) SA1101_p2v (_IEEE_Control)))
  233. #define IEEE_Data (*((volatile Word *) SA1101_p2v (_IEEE_Data)))
  234. #define IEEE_Addr (*((volatile Word *) SA1101_p2v (_IEEE_Addr)))
  235. #define IEEE_Status (*((volatile Word *) SA1101_p2v (_IEEE_Status)))
  236. #define IEEE_IntStatus (*((volatile Word *) SA1101_p2v (_IEEE_IntStatus)))
  237. #define IEEE_FifoLevels (*((volatile Word *) SA1101_p2v (_IEEE_FifoLevels)))
  238. #define IEEE_InitTime (*((volatile Word *) SA1101_p2v (_IEEE_InitTime)))
  239. #define IEEE_TimerStatus (*((volatile Word *) SA1101_p2v (_IEEE_TimerStatus)))
  240. #define IEEE_FifoReset (*((volatile Word *) SA1101_p2v (_IEEE_FifoReset)))
  241. #define IEEE_ReloadValue (*((volatile Word *) SA1101_p2v (_IEEE_ReloadValue)))
  242. #define IEEE_TestControl (*((volatile Word *) SA1101_p2v (_IEEE_TestControl)))
  243. #define IEEE_TestDataIn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataIn)))
  244. #define IEEE_TestDataInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestDataInEn)))
  245. #define IEEE_TestCtrlIn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlIn)))
  246. #define IEEE_TestCtrlInEn (*((volatile Word *) SA1101_p2v (_IEEE_TestCtrlInEn)))
  247. #define IEEE_TestDataStat (*((volatile Word *) SA1101_p2v (_IEEE_TestDataStat)))
  248. #define IEEE_Config_M Fld(3,0) /* Mode select */
  249. #define IEEE_Config_D 0x04 /* FIFO access enable */
  250. #define IEEE_Config_B 0x08 /* 9-bit word enable */
  251. #define IEEE_Config_T 0x10 /* Data transfer enable */
  252. #define IEEE_Config_A 0x20 /* Data transfer direction */
  253. #define IEEE_Config_E 0x40 /* Timer enable */
  254. #define IEEE_Control_A 0x08 /* AutoFd output */
  255. #define IEEE_Control_E 0x04 /* Selectin output */
  256. #define IEEE_Control_T 0x02 /* Strobe output */
  257. #define IEEE_Control_I 0x01 /* Port init output */
  258. #define IEEE_Data_C (1<<31) /* Byte count */
  259. #define IEEE_Data_Db Fld(9,16) /* Data byte 2 */
  260. #define IEEE_Data_Da Fld(9,0) /* Data byte 1 */
  261. #define IEEE_Addr_A Fld(8,0) /* forward address transfer byte */
  262. #define IEEE_Status_A 0x0100 /* nAutoFd port output status */
  263. #define IEEE_Status_E 0x0080 /* nSelectIn port output status */
  264. #define IEEE_Status_T 0x0040 /* nStrobe port output status */
  265. #define IEEE_Status_I 0x0020 /* nInit port output status */
  266. #define IEEE_Status_B 0x0010 /* Busy port inout status */
  267. #define IEEE_Status_S 0x0008 /* Select port input status */
  268. #define IEEE_Status_K 0x0004 /* nAck port input status */
  269. #define IEEE_Status_F 0x0002 /* nFault port input status */
  270. #define IEEE_Status_R 0x0001 /* pError port input status */
  271. #define IEEE_IntStatus_IntReqDat 0x0100
  272. #define IEEE_IntStatus_IntReqEmp 0x0080
  273. #define IEEE_IntStatus_IntReqInt 0x0040
  274. #define IEEE_IntStatus_IntReqRav 0x0020
  275. #define IEEE_IntStatus_IntReqTim 0x0010
  276. #define IEEE_IntStatus_RevAddrComp 0x0008
  277. #define IEEE_IntStatus_RevDataComp 0x0004
  278. #define IEEE_IntStatus_FwdAddrComp 0x0002
  279. #define IEEE_IntStatus_FwdDataComp 0x0001
  280. #define IEEE_FifoLevels_RevFifoLevel 2
  281. #define IEEE_FifoLevels_FwdFifoLevel 1
  282. #define IEEE_InitTime_TimValInit Fld(22,0)
  283. #define IEEE_TimerStatus_TimValStat Fld(22,0)
  284. #define IEEE_ReloadValue_Reload Fld(4,0)
  285. #define IEEE_TestControl_RegClk 0x04
  286. #define IEEE_TestControl_ClockSelect Fld(2,1)
  287. #define IEEE_TestControl_TimerTestModeEn 0x01
  288. #define IEEE_TestCtrlIn_PError 0x10
  289. #define IEEE_TestCtrlIn_nFault 0x08
  290. #define IEEE_TestCtrlIn_nAck 0x04
  291. #define IEEE_TestCtrlIn_PSel 0x02
  292. #define IEEE_TestCtrlIn_Busy 0x01
  293. #endif /* LANGUAGE == C */
  294. /*
  295. * VGA Controller
  296. *
  297. * Registers
  298. * VideoControl Video Control Register
  299. * VgaTiming0 VGA Timing Register 0
  300. * VgaTiming1 VGA Timing Register 1
  301. * VgaTiming2 VGA Timing Register 2
  302. * VgaTiming3 VGA Timing Register 3
  303. * VgaBorder VGA Border Color Register
  304. * VgaDBAR VGADMA Base Address Register
  305. * VgaDCAR VGADMA Channel Current Address Register
  306. * VgaStatus VGA Status Register
  307. * VgaInterruptMask VGA Interrupt Mask Register
  308. * VgaPalette VGA Palette Registers
  309. * DacControl DAC Control Register
  310. * VgaTest VGA Controller Test Register
  311. */
  312. #define _VGA( x ) _SA1101( ( x ) + __VGA_CONTROL )
  313. #define _VideoControl _VGA( 0x0000 )
  314. #define _VgaTiming0 _VGA( 0x0400 )
  315. #define _VgaTiming1 _VGA( 0x0800 )
  316. #define _VgaTiming2 _VGA( 0x0c00 )
  317. #define _VgaTiming3 _VGA( 0x1000 )
  318. #define _VgaBorder _VGA( 0x1400 )
  319. #define _VgaDBAR _VGA( 0x1800 )
  320. #define _VgaDCAR _VGA( 0x1c00 )
  321. #define _VgaStatus _VGA( 0x2000 )
  322. #define _VgaInterruptMask _VGA( 0x2400 )
  323. #define _VgaPalette _VGA( 0x40000 )
  324. #define _DacControl _VGA( 0x3000 )
  325. #define _VgaTest _VGA( 0x2c00 )
  326. #if (LANGUAGE == C)
  327. #define VideoControl (*((volatile Word *) SA1101_p2v (_VideoControl)))
  328. #define VgaTiming0 (*((volatile Word *) SA1101_p2v (_VgaTiming0)))
  329. #define VgaTiming1 (*((volatile Word *) SA1101_p2v (_VgaTiming1)))
  330. #define VgaTiming2 (*((volatile Word *) SA1101_p2v (_VgaTiming2)))
  331. #define VgaTiming3 (*((volatile Word *) SA1101_p2v (_VgaTiming3)))
  332. #define VgaBorder (*((volatile Word *) SA1101_p2v (_VgaBorder)))
  333. #define VgaDBAR (*((volatile Word *) SA1101_p2v (_VgaDBAR)))
  334. #define VgaDCAR (*((volatile Word *) SA1101_p2v (_VgaDCAR)))
  335. #define VgaStatus (*((volatile Word *) SA1101_p2v (_VgaStatus)))
  336. #define VgaInterruptMask (*((volatile Word *) SA1101_p2v (_VgaInterruptMask)))
  337. #define VgaPalette (*((volatile Word *) SA1101_p2v (_VgaPalette)))
  338. #define DacControl (*((volatile Word *) SA1101_p2v (_DacControl))
  339. #define VgaTest (*((volatile Word *) SA1101_p2v (_VgaTest)))
  340. #define VideoControl_VgaEn 0x00000000
  341. #define VideoControl_BGR 0x00000001
  342. #define VideoControl_VCompVal Fld(2,2)
  343. #define VideoControl_VgaReq Fld(4,4)
  344. #define VideoControl_VBurstL Fld(4,8)
  345. #define VideoControl_VMode (1<<12)
  346. #define VideoControl_PalRead (1<<13)
  347. #define VgaTiming0_PPL Fld(6,2)
  348. #define VgaTiming0_HSW Fld(8,8)
  349. #define VgaTiming0_HFP Fld(8,16)
  350. #define VgaTiming0_HBP Fld(8,24)
  351. #define VgaTiming1_LPS Fld(10,0)
  352. #define VgaTiming1_VSW Fld(6,10)
  353. #define VgaTiming1_VFP Fld(8,16)
  354. #define VgaTiming1_VBP Fld(8,24)
  355. #define VgaTiming2_IVS 0x01
  356. #define VgaTiming2_IHS 0x02
  357. #define VgaTiming2_CVS 0x04
  358. #define VgaTiming2_CHS 0x08
  359. #define VgaTiming3_HBS Fld(8,0)
  360. #define VgaTiming3_HBE Fld(8,8)
  361. #define VgaTiming3_VBS Fld(8,16)
  362. #define VgaTiming3_VBE Fld(8,24)
  363. #define VgaBorder_BCOL Fld(24,0)
  364. #define VgaStatus_VFUF 0x01
  365. #define VgaStatus_VNext 0x02
  366. #define VgaStatus_VComp 0x04
  367. #define VgaInterruptMask_VFUFMask 0x00
  368. #define VgaInterruptMask_VNextMask 0x01
  369. #define VgaInterruptMask_VCompMask 0x02
  370. #define VgaPalette_R Fld(8,0)
  371. #define VgaPalette_G Fld(8,8)
  372. #define VgaPalette_B Fld(8,16)
  373. #define DacControl_DACON 0x0001
  374. #define DacControl_COMPON 0x0002
  375. #define DacControl_PEDON 0x0004
  376. #define DacControl_RTrim Fld(5,4)
  377. #define DacControl_GTrim Fld(5,9)
  378. #define DacControl_BTrim Fld(5,14)
  379. #define VgaTest_TDAC 0x00
  380. #define VgaTest_Datatest Fld(4,1)
  381. #define VgaTest_DACTESTDAC 0x10
  382. #define VgaTest_DACTESTOUT Fld(3,5)
  383. #endif /* LANGUAGE == C */
  384. /*
  385. * USB Host Interface Controller
  386. *
  387. * Registers
  388. * Revision
  389. * Control
  390. * CommandStatus
  391. * InterruptStatus
  392. * InterruptEnable
  393. * HCCA
  394. * PeriodCurrentED
  395. * ControlHeadED
  396. * BulkHeadED
  397. * BulkCurrentED
  398. * DoneHead
  399. * FmInterval
  400. * FmRemaining
  401. * FmNumber
  402. * PeriodicStart
  403. * LSThreshold
  404. * RhDescriptorA
  405. * RhDescriptorB
  406. * RhStatus
  407. * RhPortStatus
  408. * USBStatus
  409. * USBReset
  410. * USTAR
  411. * USWER
  412. * USRFR
  413. * USNFR
  414. * USTCSR
  415. * USSR
  416. *
  417. */
  418. #define _USB( x ) _SA1101( ( x ) + __USB_CONTROL )
  419. #define _Revision _USB( 0x0000 )
  420. #define _Control _USB( 0x0888 )
  421. #define _CommandStatus _USB( 0x0c00 )
  422. #define _InterruptStatus _USB( 0x1000 )
  423. #define _InterruptEnable _USB( 0x1400 )
  424. #define _HCCA _USB( 0x1800 )
  425. #define _PeriodCurrentED _USB( 0x1c00 )
  426. #define _ControlHeadED _USB( 0x2000 )
  427. #define _BulkHeadED _USB( 0x2800 )
  428. #define _BulkCurrentED _USB( 0x2c00 )
  429. #define _DoneHead _USB( 0x3000 )
  430. #define _FmInterval _USB( 0x3400 )
  431. #define _FmRemaining _USB( 0x3800 )
  432. #define _FmNumber _USB( 0x3c00 )
  433. #define _PeriodicStart _USB( 0x4000 )
  434. #define _LSThreshold _USB( 0x4400 )
  435. #define _RhDescriptorA _USB( 0x4800 )
  436. #define _RhDescriptorB _USB( 0x4c00 )
  437. #define _RhStatus _USB( 0x5000 )
  438. #define _RhPortStatus _USB( 0x5400 )
  439. #define _USBStatus _USB( 0x11800 )
  440. #define _USBReset _USB( 0x11c00 )
  441. #define _USTAR _USB( 0x10400 )
  442. #define _USWER _USB( 0x10800 )
  443. #define _USRFR _USB( 0x10c00 )
  444. #define _USNFR _USB( 0x11000 )
  445. #define _USTCSR _USB( 0x11400 )
  446. #define _USSR _USB( 0x11800 )
  447. #if (LANGUAGE == C)
  448. #define Revision (*((volatile Word *) SA1101_p2v (_Revision)))
  449. #define Control (*((volatile Word *) SA1101_p2v (_Control)))
  450. #define CommandStatus (*((volatile Word *) SA1101_p2v (_CommandStatus)))
  451. #define InterruptStatus (*((volatile Word *) SA1101_p2v (_InterruptStatus)))
  452. #define InterruptEnable (*((volatile Word *) SA1101_p2v (_InterruptEnable)))
  453. #define HCCA (*((volatile Word *) SA1101_p2v (_HCCA)))
  454. #define PeriodCurrentED (*((volatile Word *) SA1101_p2v (_PeriodCurrentED)))
  455. #define ControlHeadED (*((volatile Word *) SA1101_p2v (_ControlHeadED)))
  456. #define BulkHeadED (*((volatile Word *) SA1101_p2v (_BulkHeadED)))
  457. #define BulkCurrentED (*((volatile Word *) SA1101_p2v (_BulkCurrentED)))
  458. #define DoneHead (*((volatile Word *) SA1101_p2v (_DoneHead)))
  459. #define FmInterval (*((volatile Word *) SA1101_p2v (_FmInterval)))
  460. #define FmRemaining (*((volatile Word *) SA1101_p2v (_FmRemaining)))
  461. #define FmNumber (*((volatile Word *) SA1101_p2v (_FmNumber)))
  462. #define PeriodicStart (*((volatile Word *) SA1101_p2v (_PeriodicStart)))
  463. #define LSThreshold (*((volatile Word *) SA1101_p2v (_LSThreshold)))
  464. #define RhDescriptorA (*((volatile Word *) SA1101_p2v (_RhDescriptorA)))
  465. #define RhDescriptorB (*((volatile Word *) SA1101_p2v (_RhDescriptorB)))
  466. #define RhStatus (*((volatile Word *) SA1101_p2v (_RhStatus)))
  467. #define RhPortStatus (*((volatile Word *) SA1101_p2v (_RhPortStatus)))
  468. #define USBStatus (*((volatile Word *) SA1101_p2v (_USBStatus)))
  469. #define USBReset (*((volatile Word *) SA1101_p2v (_USBReset)))
  470. #define USTAR (*((volatile Word *) SA1101_p2v (_USTAR)))
  471. #define USWER (*((volatile Word *) SA1101_p2v (_USWER)))
  472. #define USRFR (*((volatile Word *) SA1101_p2v (_USRFR)))
  473. #define USNFR (*((volatile Word *) SA1101_p2v (_USNFR)))
  474. #define USTCSR (*((volatile Word *) SA1101_p2v (_USTCSR)))
  475. #define USSR (*((volatile Word *) SA1101_p2v (_USSR)))
  476. #define USBStatus_IrqHciRmtWkp (1<<7)
  477. #define USBStatus_IrqHciBuffAcc (1<<8)
  478. #define USBStatus_nIrqHciM (1<<9)
  479. #define USBStatus_nHciMFClr (1<<10)
  480. #define USBReset_ForceIfReset 0x01
  481. #define USBReset_ForceHcReset 0x02
  482. #define USBReset_ClkGenReset 0x04
  483. #define USTCR_RdBstCntrl Fld(3,0)
  484. #define USTCR_ByteEnable Fld(4,3)
  485. #define USTCR_WriteEn (1<<7)
  486. #define USTCR_FifoCir (1<<8)
  487. #define USTCR_TestXferSel (1<<9)
  488. #define USTCR_FifoCirAtEnd (1<<10)
  489. #define USTCR_nSimScaleDownClk (1<<11)
  490. #define USSR_nAppMDEmpty 0x01
  491. #define USSR_nAppMDFirst 0x02
  492. #define USSR_nAppMDLast 0x04
  493. #define USSR_nAppMDFull 0x08
  494. #define USSR_nAppMAFull 0x10
  495. #define USSR_XferReq 0x20
  496. #define USSR_XferEnd 0x40
  497. #endif /* LANGUAGE == C */
  498. /*
  499. * Interrupt Controller
  500. *
  501. * Registers
  502. * INTTEST0 Test register 0
  503. * INTTEST1 Test register 1
  504. * INTENABLE0 Interrupt Enable register 0
  505. * INTENABLE1 Interrupt Enable register 1
  506. * INTPOL0 Interrupt Polarity selection 0
  507. * INTPOL1 Interrupt Polarity selection 1
  508. * INTTSTSEL Interrupt source selection
  509. * INTSTATCLR0 Interrupt Status 0
  510. * INTSTATCLR1 Interrupt Status 1
  511. * INTSET0 Interrupt Set 0
  512. * INTSET1 Interrupt Set 1
  513. */
  514. #define _INT( x ) _SA1101( ( x ) + __INTERRUPT_CONTROL)
  515. #define _INTTEST0 _INT( 0x1000 )
  516. #define _INTTEST1 _INT( 0x1400 )
  517. #define _INTENABLE0 _INT( 0x2000 )
  518. #define _INTENABLE1 _INT( 0x2400 )
  519. #define _INTPOL0 _INT( 0x3000 )
  520. #define _INTPOL1 _INT( 0x3400 )
  521. #define _INTTSTSEL _INT( 0x5000 )
  522. #define _INTSTATCLR0 _INT( 0x6000 )
  523. #define _INTSTATCLR1 _INT( 0x6400 )
  524. #define _INTSET0 _INT( 0x7000 )
  525. #define _INTSET1 _INT( 0x7400 )
  526. #if ( LANGUAGE == C )
  527. #define INTTEST0 (*((volatile Word *) SA1101_p2v (_INTTEST0)))
  528. #define INTTEST1 (*((volatile Word *) SA1101_p2v (_INTTEST1)))
  529. #define INTENABLE0 (*((volatile Word *) SA1101_p2v (_INTENABLE0)))
  530. #define INTENABLE1 (*((volatile Word *) SA1101_p2v (_INTENABLE1)))
  531. #define INTPOL0 (*((volatile Word *) SA1101_p2v (_INTPOL0)))
  532. #define INTPOL1 (*((volatile Word *) SA1101_p2v (_INTPOL1)))
  533. #define INTTSTSEL (*((volatile Word *) SA1101_p2v (_INTTSTSEL)))
  534. #define INTSTATCLR0 (*((volatile Word *) SA1101_p2v (_INTSTATCLR0)))
  535. #define INTSTATCLR1 (*((volatile Word *) SA1101_p2v (_INTSTATCLR1)))
  536. #define INTSET0 (*((volatile Word *) SA1101_p2v (_INTSET0)))
  537. #define INTSET1 (*((volatile Word *) SA1101_p2v (_INTSET1)))
  538. #endif /* LANGUAGE == C */
  539. /*
  540. * PS/2 Trackpad and Mouse Interfaces
  541. *
  542. * Registers (prefix kbd applies to trackpad interface, mse to mouse)
  543. * KBDCR Control Register
  544. * KBDSTAT Status Register
  545. * KBDDATA Transmit/Receive Data register
  546. * KBDCLKDIV Clock Division Register
  547. * KBDPRECNT Clock Precount Register
  548. * KBDTEST1 Test register 1
  549. * KBDTEST2 Test register 2
  550. * KBDTEST3 Test register 3
  551. * KBDTEST4 Test register 4
  552. * MSECR
  553. * MSESTAT
  554. * MSEDATA
  555. * MSECLKDIV
  556. * MSEPRECNT
  557. * MSETEST1
  558. * MSETEST2
  559. * MSETEST3
  560. * MSETEST4
  561. *
  562. */
  563. #define _KBD( x ) _SA1101( ( x ) + __TRACK_INTERFACE )
  564. #define _MSE( x ) _SA1101( ( x ) + __MOUSE_INTERFACE )
  565. #define _KBDCR _KBD( 0x0000 )
  566. #define _KBDSTAT _KBD( 0x0400 )
  567. #define _KBDDATA _KBD( 0x0800 )
  568. #define _KBDCLKDIV _KBD( 0x0c00 )
  569. #define _KBDPRECNT _KBD( 0x1000 )
  570. #define _KBDTEST1 _KBD( 0x2000 )
  571. #define _KBDTEST2 _KBD( 0x2400 )
  572. #define _KBDTEST3 _KBD( 0x2800 )
  573. #define _KBDTEST4 _KBD( 0x2c00 )
  574. #define _MSECR _MSE( 0x0000 )
  575. #define _MSESTAT _MSE( 0x0400 )
  576. #define _MSEDATA _MSE( 0x0800 )
  577. #define _MSECLKDIV _MSE( 0x0c00 )
  578. #define _MSEPRECNT _MSE( 0x1000 )
  579. #define _MSETEST1 _MSE( 0x2000 )
  580. #define _MSETEST2 _MSE( 0x2400 )
  581. #define _MSETEST3 _MSE( 0x2800 )
  582. #define _MSETEST4 _MSE( 0x2c00 )
  583. #if ( LANGUAGE == C )
  584. #define KBDCR (*((volatile Word *) SA1101_p2v (_KBDCR)))
  585. #define KBDSTAT (*((volatile Word *) SA1101_p2v (_KBDSTAT)))
  586. #define KBDDATA (*((volatile Word *) SA1101_p2v (_KBDDATA)))
  587. #define KBDCLKDIV (*((volatile Word *) SA1101_p2v (_KBDCLKDIV)))
  588. #define KBDPRECNT (*((volatile Word *) SA1101_p2v (_KBDPRECNT)))
  589. #define KBDTEST1 (*((volatile Word *) SA1101_p2v (_KBDTEST1)))
  590. #define KBDTEST2 (*((volatile Word *) SA1101_p2v (_KBDTEST2)))
  591. #define KBDTEST3 (*((volatile Word *) SA1101_p2v (_KBDTEST3)))
  592. #define KBDTEST4 (*((volatile Word *) SA1101_p2v (_KBDTEST4)))
  593. #define MSECR (*((volatile Word *) SA1101_p2v (_MSECR)))
  594. #define MSESTAT (*((volatile Word *) SA1101_p2v (_MSESTAT)))
  595. #define MSEDATA (*((volatile Word *) SA1101_p2v (_MSEDATA)))
  596. #define MSECLKDIV (*((volatile Word *) SA1101_p2v (_MSECLKDIV)))
  597. #define MSEPRECNT (*((volatile Word *) SA1101_p2v (_MSEPRECNT)))
  598. #define MSETEST1 (*((volatile Word *) SA1101_p2v (_MSETEST1)))
  599. #define MSETEST2 (*((volatile Word *) SA1101_p2v (_MSETEST2)))
  600. #define MSETEST3 (*((volatile Word *) SA1101_p2v (_MSETEST3)))
  601. #define MSETEST4 (*((volatile Word *) SA1101_p2v (_MSETEST4)))
  602. #define KBDCR_ENA 0x08
  603. #define KBDCR_FKD 0x02
  604. #define KBDCR_FKC 0x01
  605. #define KBDSTAT_TXE 0x80
  606. #define KBDSTAT_TXB 0x40
  607. #define KBDSTAT_RXF 0x20
  608. #define KBDSTAT_RXB 0x10
  609. #define KBDSTAT_ENA 0x08
  610. #define KBDSTAT_RXP 0x04
  611. #define KBDSTAT_KBD 0x02
  612. #define KBDSTAT_KBC 0x01
  613. #define KBDCLKDIV_DivVal Fld(4,0)
  614. #define MSECR_ENA 0x08
  615. #define MSECR_FKD 0x02
  616. #define MSECR_FKC 0x01
  617. #define MSESTAT_TXE 0x80
  618. #define MSESTAT_TXB 0x40
  619. #define MSESTAT_RXF 0x20
  620. #define MSESTAT_RXB 0x10
  621. #define MSESTAT_ENA 0x08
  622. #define MSESTAT_RXP 0x04
  623. #define MSESTAT_MSD 0x02
  624. #define MSESTAT_MSC 0x01
  625. #define MSECLKDIV_DivVal Fld(4,0)
  626. #define KBDTEST1_CD 0x80
  627. #define KBDTEST1_RC1 0x40
  628. #define KBDTEST1_MC 0x20
  629. #define KBDTEST1_C Fld(2,3)
  630. #define KBDTEST1_T2 0x40
  631. #define KBDTEST1_T1 0x20
  632. #define KBDTEST1_T0 0x10
  633. #define KBDTEST2_TICBnRES 0x08
  634. #define KBDTEST2_RKC 0x04
  635. #define KBDTEST2_RKD 0x02
  636. #define KBDTEST2_SEL 0x01
  637. #define KBDTEST3_ms_16 0x80
  638. #define KBDTEST3_us_64 0x40
  639. #define KBDTEST3_us_16 0x20
  640. #define KBDTEST3_DIV8 0x10
  641. #define KBDTEST3_DIn 0x08
  642. #define KBDTEST3_CIn 0x04
  643. #define KBDTEST3_KD 0x02
  644. #define KBDTEST3_KC 0x01
  645. #define KBDTEST4_BC12 0x80
  646. #define KBDTEST4_BC11 0x40
  647. #define KBDTEST4_TRES 0x20
  648. #define KBDTEST4_CLKOE 0x10
  649. #define KBDTEST4_CRES 0x08
  650. #define KBDTEST4_RXB 0x04
  651. #define KBDTEST4_TXB 0x02
  652. #define KBDTEST4_SRX 0x01
  653. #define MSETEST1_CD 0x80
  654. #define MSETEST1_RC1 0x40
  655. #define MSETEST1_MC 0x20
  656. #define MSETEST1_C Fld(2,3)
  657. #define MSETEST1_T2 0x40
  658. #define MSETEST1_T1 0x20
  659. #define MSETEST1_T0 0x10
  660. #define MSETEST2_TICBnRES 0x08
  661. #define MSETEST2_RKC 0x04
  662. #define MSETEST2_RKD 0x02
  663. #define MSETEST2_SEL 0x01
  664. #define MSETEST3_ms_16 0x80
  665. #define MSETEST3_us_64 0x40
  666. #define MSETEST3_us_16 0x20
  667. #define MSETEST3_DIV8 0x10
  668. #define MSETEST3_DIn 0x08
  669. #define MSETEST3_CIn 0x04
  670. #define MSETEST3_KD 0x02
  671. #define MSETEST3_KC 0x01
  672. #define MSETEST4_BC12 0x80
  673. #define MSETEST4_BC11 0x40
  674. #define MSETEST4_TRES 0x20
  675. #define MSETEST4_CLKOE 0x10
  676. #define MSETEST4_CRES 0x08
  677. #define MSETEST4_RXB 0x04
  678. #define MSETEST4_TXB 0x02
  679. #define MSETEST4_SRX 0x01
  680. #endif /* LANGUAGE == C */
  681. /*
  682. * General-Purpose I/O Interface
  683. *
  684. * Registers
  685. * PADWR Port A Data Write Register
  686. * PBDWR Port B Data Write Register
  687. * PADRR Port A Data Read Register
  688. * PBDRR Port B Data Read Register
  689. * PADDR Port A Data Direction Register
  690. * PBDDR Port B Data Direction Register
  691. * PASSR Port A Sleep State Register
  692. * PBSSR Port B Sleep State Register
  693. *
  694. */
  695. #define _PIO( x ) _SA1101( ( x ) + __GPIO_INTERFACE )
  696. #define _PADWR _PIO( 0x0000 )
  697. #define _PBDWR _PIO( 0x0400 )
  698. #define _PADRR _PIO( 0x0000 )
  699. #define _PBDRR _PIO( 0x0400 )
  700. #define _PADDR _PIO( 0x0800 )
  701. #define _PBDDR _PIO( 0x0c00 )
  702. #define _PASSR _PIO( 0x1000 )
  703. #define _PBSSR _PIO( 0x1400 )
  704. #if ( LANGUAGE == C )
  705. #define PADWR (*((volatile Word *) SA1101_p2v (_PADWR)))
  706. #define PBDWR (*((volatile Word *) SA1101_p2v (_PBDWR)))
  707. #define PADRR (*((volatile Word *) SA1101_p2v (_PADRR)))
  708. #define PBDRR (*((volatile Word *) SA1101_p2v (_PBDRR)))
  709. #define PADDR (*((volatile Word *) SA1101_p2v (_PADDR)))
  710. #define PBDDR (*((volatile Word *) SA1101_p2v (_PBDDR)))
  711. #define PASSR (*((volatile Word *) SA1101_p2v (_PASSR)))
  712. #define PBSSR (*((volatile Word *) SA1101_p2v (_PBSSR)))
  713. #endif
  714. /*
  715. * Keypad Interface
  716. *
  717. * Registers
  718. * PXDWR
  719. * PXDRR
  720. * PYDWR
  721. * PYDRR
  722. *
  723. */
  724. #define _KEYPAD( x ) _SA1101( ( x ) + __KEYPAD_INTERFACE )
  725. #define _PXDWR _KEYPAD( 0x0000 )
  726. #define _PXDRR _KEYPAD( 0x0000 )
  727. #define _PYDWR _KEYPAD( 0x0400 )
  728. #define _PYDRR _KEYPAD( 0x0400 )
  729. #if ( LANGUAGE == C )
  730. #define PXDWR (*((volatile Word *) SA1101_p2v (_PXDWR)))
  731. #define PXDRR (*((volatile Word *) SA1101_p2v (_PXDRR)))
  732. #define PYDWR (*((volatile Word *) SA1101_p2v (_PYDWR)))
  733. #define PYDRR (*((volatile Word *) SA1101_p2v (_PYDRR)))
  734. #endif
  735. /*
  736. * PCMCIA Interface
  737. *
  738. * Registers
  739. * PCSR Status Register
  740. * PCCR Control Register
  741. * PCSSR Sleep State Register
  742. *
  743. */
  744. #define _CARD( x ) _SA1101( ( x ) + __PCMCIA_INTERFACE )
  745. #define _PCSR _CARD( 0x0000 )
  746. #define _PCCR _CARD( 0x0400 )
  747. #define _PCSSR _CARD( 0x0800 )
  748. #if ( LANGUAGE == C )
  749. #define PCSR (*((volatile Word *) SA1101_p2v (_PCSR)))
  750. #define PCCR (*((volatile Word *) SA1101_p2v (_PCCR)))
  751. #define PCSSR (*((volatile Word *) SA1101_p2v (_PCSSR)))
  752. #define PCSR_S0_ready 0x0001
  753. #define PCSR_S1_ready 0x0002
  754. #define PCSR_S0_detected 0x0004
  755. #define PCSR_S1_detected 0x0008
  756. #define PCSR_S0_VS1 0x0010
  757. #define PCSR_S0_VS2 0x0020
  758. #define PCSR_S1_VS1 0x0040
  759. #define PCSR_S1_VS2 0x0080
  760. #define PCSR_S0_WP 0x0100
  761. #define PCSR_S1_WP 0x0200
  762. #define PCSR_S0_BVD1_nSTSCHG 0x0400
  763. #define PCSR_S0_BVD2_nSPKR 0x0800
  764. #define PCSR_S1_BVD1_nSTSCHG 0x1000
  765. #define PCSR_S1_BVD2_nSPKR 0x2000
  766. #define PCCR_S0_VPP0 0x0001
  767. #define PCCR_S0_VPP1 0x0002
  768. #define PCCR_S0_VCC0 0x0004
  769. #define PCCR_S0_VCC1 0x0008
  770. #define PCCR_S1_VPP0 0x0010
  771. #define PCCR_S1_VPP1 0x0020
  772. #define PCCR_S1_VCC0 0x0040
  773. #define PCCR_S1_VCC1 0x0080
  774. #define PCCR_S0_reset 0x0100
  775. #define PCCR_S1_reset 0x0200
  776. #define PCCR_S0_float 0x0400
  777. #define PCCR_S1_float 0x0800
  778. #define PCSSR_S0_VCC0 0x0001
  779. #define PCSSR_S0_VCC1 0x0002
  780. #define PCSSR_S0_VPP0 0x0004
  781. #define PCSSR_S0_VPP1 0x0008
  782. #define PCSSR_S0_control 0x0010
  783. #define PCSSR_S1_VCC0 0x0020
  784. #define PCSSR_S1_VCC1 0x0040
  785. #define PCSSR_S1_VPP0 0x0080
  786. #define PCSSR_S1_VPP1 0x0100
  787. #define PCSSR_S1_control 0x0200
  788. #endif
  789. #undef C
  790. #undef Assembly