SA-1100.h 111 KB

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  1. /*
  2. * FILE SA-1100.h
  3. *
  4. * Version 1.2
  5. * Author Copyright (c) Marc A. Viredaz, 1998
  6. * DEC Western Research Laboratory, Palo Alto, CA
  7. * Date January 1998 (April 1997)
  8. * System StrongARM SA-1100
  9. * Language C or ARM Assembly
  10. * Purpose Definition of constants related to the StrongARM
  11. * SA-1100 microprocessor (Advanced RISC Machine (ARM)
  12. * architecture version 4). This file is based on the
  13. * StrongARM SA-1100 data sheet version 2.2.
  14. *
  15. */
  16. /* Be sure that virtual mapping is defined right */
  17. #ifndef __ASM_ARCH_HARDWARE_H
  18. #error You must include hardware.h not SA-1100.h
  19. #endif
  20. #include "bitfield.h"
  21. /*
  22. * SA1100 CS line to physical address
  23. */
  24. #define SA1100_CS0_PHYS 0x00000000
  25. #define SA1100_CS1_PHYS 0x08000000
  26. #define SA1100_CS2_PHYS 0x10000000
  27. #define SA1100_CS3_PHYS 0x18000000
  28. #define SA1100_CS4_PHYS 0x40000000
  29. #define SA1100_CS5_PHYS 0x48000000
  30. /*
  31. * Personal Computer Memory Card International Association (PCMCIA) sockets
  32. */
  33. #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
  34. #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
  35. #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
  36. #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
  37. #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
  38. #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
  39. #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
  40. #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
  41. #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
  42. #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
  43. #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
  44. #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
  45. #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
  46. #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
  47. (0x20000000 + (Nb)*PCMCIASp)
  48. #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
  49. #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
  50. (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
  51. #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
  52. (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
  53. #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
  54. #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
  55. #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
  56. #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
  57. #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
  58. #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
  59. #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
  60. #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
  61. /*
  62. * Universal Serial Bus (USB) Device Controller (UDC) control registers
  63. *
  64. * Registers
  65. * Ser0UDCCR Serial port 0 Universal Serial Bus (USB) Device
  66. * Controller (UDC) Control Register (read/write).
  67. * Ser0UDCAR Serial port 0 Universal Serial Bus (USB) Device
  68. * Controller (UDC) Address Register (read/write).
  69. * Ser0UDCOMP Serial port 0 Universal Serial Bus (USB) Device
  70. * Controller (UDC) Output Maximum Packet size register
  71. * (read/write).
  72. * Ser0UDCIMP Serial port 0 Universal Serial Bus (USB) Device
  73. * Controller (UDC) Input Maximum Packet size register
  74. * (read/write).
  75. * Ser0UDCCS0 Serial port 0 Universal Serial Bus (USB) Device
  76. * Controller (UDC) Control/Status register end-point 0
  77. * (read/write).
  78. * Ser0UDCCS1 Serial port 0 Universal Serial Bus (USB) Device
  79. * Controller (UDC) Control/Status register end-point 1
  80. * (output, read/write).
  81. * Ser0UDCCS2 Serial port 0 Universal Serial Bus (USB) Device
  82. * Controller (UDC) Control/Status register end-point 2
  83. * (input, read/write).
  84. * Ser0UDCD0 Serial port 0 Universal Serial Bus (USB) Device
  85. * Controller (UDC) Data register end-point 0
  86. * (read/write).
  87. * Ser0UDCWC Serial port 0 Universal Serial Bus (USB) Device
  88. * Controller (UDC) Write Count register end-point 0
  89. * (read).
  90. * Ser0UDCDR Serial port 0 Universal Serial Bus (USB) Device
  91. * Controller (UDC) Data Register (read/write).
  92. * Ser0UDCSR Serial port 0 Universal Serial Bus (USB) Device
  93. * Controller (UDC) Status Register (read/write).
  94. */
  95. #define Ser0UDCCR __REG(0x80000000) /* Ser. port 0 UDC Control Reg. */
  96. #define Ser0UDCAR __REG(0x80000004) /* Ser. port 0 UDC Address Reg. */
  97. #define Ser0UDCOMP __REG(0x80000008) /* Ser. port 0 UDC Output Maximum Packet size reg. */
  98. #define Ser0UDCIMP __REG(0x8000000C) /* Ser. port 0 UDC Input Maximum Packet size reg. */
  99. #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
  100. #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
  101. #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
  102. #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
  103. #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
  104. #define Ser0UDCDR __REG(0x80000028) /* Ser. port 0 UDC Data Reg. */
  105. #define Ser0UDCSR __REG(0x80000030) /* Ser. port 0 UDC Status Reg. */
  106. #define UDCCR_UDD 0x00000001 /* UDC Disable */
  107. #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
  108. #define UDCCR_RESIM 0x00000004 /* Resume Interrupt Mask, per errata */
  109. #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
  110. /* (disable) */
  111. #define UDCCR_RIM 0x00000010 /* Receive Interrupt Mask */
  112. /* (disable) */
  113. #define UDCCR_TIM 0x00000020 /* Transmit Interrupt Mask */
  114. /* (disable) */
  115. #define UDCCR_SRM 0x00000040 /* Suspend/Resume interrupt Mask */
  116. /* (disable) */
  117. #define UDCCR_SUSIM UDCCR_SRM /* Per errata, SRM just masks suspend */
  118. #define UDCCR_REM 0x00000080 /* REset interrupt Mask (disable) */
  119. #define UDCAR_ADD Fld (7, 0) /* function ADDress */
  120. #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
  121. /* [byte] */
  122. #define UDCOMP_OutMaxPkt(Size) /* Output Maximum Packet size */ \
  123. /* [1..256 byte] */ \
  124. (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
  125. #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
  126. /* [byte] */
  127. #define UDCIMP_InMaxPkt(Size) /* Input Maximum Packet size */ \
  128. /* [1..256 byte] */ \
  129. (((Size) - 1) << FShft (UDCIMP_INMAXP))
  130. #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
  131. #define UDCCS0_IPR 0x00000002 /* Input Packet Ready */
  132. #define UDCCS0_SST 0x00000004 /* Sent STall */
  133. #define UDCCS0_FST 0x00000008 /* Force STall */
  134. #define UDCCS0_DE 0x00000010 /* Data End */
  135. #define UDCCS0_SE 0x00000020 /* Setup End (read) */
  136. #define UDCCS0_SO 0x00000040 /* Serviced Output packet ready */
  137. /* (write) */
  138. #define UDCCS0_SSE 0x00000080 /* Serviced Setup End (write) */
  139. #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
  140. /* Service request (read) */
  141. #define UDCCS1_RPC 0x00000002 /* Receive Packet Complete */
  142. #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
  143. #define UDCCS1_SST 0x00000008 /* Sent STall */
  144. #define UDCCS1_FST 0x00000010 /* Force STall */
  145. #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
  146. #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
  147. /* Service request (read) */
  148. #define UDCCS2_TPC 0x00000002 /* Transmit Packet Complete */
  149. #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
  150. #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
  151. #define UDCCS2_SST 0x00000010 /* Sent STall */
  152. #define UDCCS2_FST 0x00000020 /* Force STall */
  153. #define UDCD0_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  154. #define UDCWC_WC Fld (4, 0) /* Write Count */
  155. #define UDCDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  156. #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
  157. #define UDCSR_RIR 0x00000002 /* Receive Interrupt Request */
  158. #define UDCSR_TIR 0x00000004 /* Transmit Interrupt Request */
  159. #define UDCSR_SUSIR 0x00000008 /* SUSpend Interrupt Request */
  160. #define UDCSR_RESIR 0x00000010 /* RESume Interrupt Request */
  161. #define UDCSR_RSTIR 0x00000020 /* ReSeT Interrupt Request */
  162. /*
  163. * Universal Asynchronous Receiver/Transmitter (UART) control registers
  164. *
  165. * Registers
  166. * Ser1UTCR0 Serial port 1 Universal Asynchronous
  167. * Receiver/Transmitter (UART) Control Register 0
  168. * (read/write).
  169. * Ser1UTCR1 Serial port 1 Universal Asynchronous
  170. * Receiver/Transmitter (UART) Control Register 1
  171. * (read/write).
  172. * Ser1UTCR2 Serial port 1 Universal Asynchronous
  173. * Receiver/Transmitter (UART) Control Register 2
  174. * (read/write).
  175. * Ser1UTCR3 Serial port 1 Universal Asynchronous
  176. * Receiver/Transmitter (UART) Control Register 3
  177. * (read/write).
  178. * Ser1UTDR Serial port 1 Universal Asynchronous
  179. * Receiver/Transmitter (UART) Data Register
  180. * (read/write).
  181. * Ser1UTSR0 Serial port 1 Universal Asynchronous
  182. * Receiver/Transmitter (UART) Status Register 0
  183. * (read/write).
  184. * Ser1UTSR1 Serial port 1 Universal Asynchronous
  185. * Receiver/Transmitter (UART) Status Register 1 (read).
  186. *
  187. * Ser2UTCR0 Serial port 2 Universal Asynchronous
  188. * Receiver/Transmitter (UART) Control Register 0
  189. * (read/write).
  190. * Ser2UTCR1 Serial port 2 Universal Asynchronous
  191. * Receiver/Transmitter (UART) Control Register 1
  192. * (read/write).
  193. * Ser2UTCR2 Serial port 2 Universal Asynchronous
  194. * Receiver/Transmitter (UART) Control Register 2
  195. * (read/write).
  196. * Ser2UTCR3 Serial port 2 Universal Asynchronous
  197. * Receiver/Transmitter (UART) Control Register 3
  198. * (read/write).
  199. * Ser2UTCR4 Serial port 2 Universal Asynchronous
  200. * Receiver/Transmitter (UART) Control Register 4
  201. * (read/write).
  202. * Ser2UTDR Serial port 2 Universal Asynchronous
  203. * Receiver/Transmitter (UART) Data Register
  204. * (read/write).
  205. * Ser2UTSR0 Serial port 2 Universal Asynchronous
  206. * Receiver/Transmitter (UART) Status Register 0
  207. * (read/write).
  208. * Ser2UTSR1 Serial port 2 Universal Asynchronous
  209. * Receiver/Transmitter (UART) Status Register 1 (read).
  210. *
  211. * Ser3UTCR0 Serial port 3 Universal Asynchronous
  212. * Receiver/Transmitter (UART) Control Register 0
  213. * (read/write).
  214. * Ser3UTCR1 Serial port 3 Universal Asynchronous
  215. * Receiver/Transmitter (UART) Control Register 1
  216. * (read/write).
  217. * Ser3UTCR2 Serial port 3 Universal Asynchronous
  218. * Receiver/Transmitter (UART) Control Register 2
  219. * (read/write).
  220. * Ser3UTCR3 Serial port 3 Universal Asynchronous
  221. * Receiver/Transmitter (UART) Control Register 3
  222. * (read/write).
  223. * Ser3UTDR Serial port 3 Universal Asynchronous
  224. * Receiver/Transmitter (UART) Data Register
  225. * (read/write).
  226. * Ser3UTSR0 Serial port 3 Universal Asynchronous
  227. * Receiver/Transmitter (UART) Status Register 0
  228. * (read/write).
  229. * Ser3UTSR1 Serial port 3 Universal Asynchronous
  230. * Receiver/Transmitter (UART) Status Register 1 (read).
  231. *
  232. * Clocks
  233. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  234. * or 3.5795 MHz).
  235. * fua, Tua Frequency, period of the UART communication.
  236. */
  237. #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
  238. #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
  239. #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
  240. #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
  241. #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
  242. #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
  243. #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
  244. #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
  245. #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
  246. #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
  247. #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
  248. #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
  249. #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
  250. #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
  251. #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
  252. #define Ser2UTCR0 _UTCR0 (2) /* Ser. port 2 UART Control Reg. 0 */
  253. #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
  254. #define Ser2UTCR2 _UTCR2 (2) /* Ser. port 2 UART Control Reg. 2 */
  255. #define Ser2UTCR3 _UTCR3 (2) /* Ser. port 2 UART Control Reg. 3 */
  256. #define Ser2UTCR4 _UTCR4 (2) /* Ser. port 2 UART Control Reg. 4 */
  257. #define Ser2UTDR _UTDR (2) /* Ser. port 2 UART Data Reg. */
  258. #define Ser2UTSR0 _UTSR0 (2) /* Ser. port 2 UART Status Reg. 0 */
  259. #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
  260. #define Ser3UTCR0 _UTCR0 (3) /* Ser. port 3 UART Control Reg. 0 */
  261. #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
  262. #define Ser3UTCR2 _UTCR2 (3) /* Ser. port 3 UART Control Reg. 2 */
  263. #define Ser3UTCR3 _UTCR3 (3) /* Ser. port 3 UART Control Reg. 3 */
  264. #define Ser3UTDR _UTDR (3) /* Ser. port 3 UART Data Reg. */
  265. #define Ser3UTSR0 _UTSR0 (3) /* Ser. port 3 UART Status Reg. 0 */
  266. #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
  267. /* Those are still used in some places */
  268. #define _Ser1UTCR0 __PREG(Ser1UTCR0)
  269. #define _Ser2UTCR0 __PREG(Ser2UTCR0)
  270. #define _Ser3UTCR0 __PREG(Ser3UTCR0)
  271. /* Register offsets */
  272. #define UTCR0 0x00
  273. #define UTCR1 0x04
  274. #define UTCR2 0x08
  275. #define UTCR3 0x0c
  276. #define UTDR 0x14
  277. #define UTSR0 0x1c
  278. #define UTSR1 0x20
  279. #define UTCR0_PE 0x00000001 /* Parity Enable */
  280. #define UTCR0_OES 0x00000002 /* Odd/Even parity Select */
  281. #define UTCR0_OddPar (UTCR0_OES*0) /* Odd Parity */
  282. #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
  283. #define UTCR0_SBS 0x00000004 /* Stop Bit Select */
  284. #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
  285. #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
  286. #define UTCR0_DSS 0x00000008 /* Data Size Select */
  287. #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
  288. #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
  289. #define UTCR0_SCE 0x00000010 /* Sample Clock Enable */
  290. /* (ser. port 1: GPIO [18], */
  291. /* ser. port 3: GPIO [20]) */
  292. #define UTCR0_RCE 0x00000020 /* Receive Clock Edge select */
  293. #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
  294. #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
  295. #define UTCR0_TCE 0x00000040 /* Transmit Clock Edge select */
  296. #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
  297. #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
  298. #define UTCR0_Ser2IrDA /* Ser. port 2 IrDA settings */ \
  299. (UTCR0_1StpBit + UTCR0_8BitData)
  300. #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
  301. #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
  302. /* fua = fxtl/(16*(BRD[11:0] + 1)) */
  303. /* Tua = 16*(BRD [11:0] + 1)*Txtl */
  304. #define UTCR1_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  305. (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
  306. FShft (UTCR1_BRD))
  307. #define UTCR2_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  308. (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
  309. FShft (UTCR2_BRD))
  310. /* fua = fxtl/(16*Floor (Div/16)) */
  311. /* Tua = 16*Floor (Div/16)*Txtl */
  312. #define UTCR1_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  313. (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
  314. FShft (UTCR1_BRD))
  315. #define UTCR2_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  316. (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
  317. FShft (UTCR2_BRD))
  318. /* fua = fxtl/(16*Ceil (Div/16)) */
  319. /* Tua = 16*Ceil (Div/16)*Txtl */
  320. #define UTCR3_RXE 0x00000001 /* Receive Enable */
  321. #define UTCR3_TXE 0x00000002 /* Transmit Enable */
  322. #define UTCR3_BRK 0x00000004 /* BReaK mode */
  323. #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
  324. /* more Interrupt Enable */
  325. #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
  326. /* Interrupt Enable */
  327. #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
  328. #define UTCR3_Ser2IrDA /* Ser. port 2 IrDA settings (RIE, */ \
  329. /* TIE, LBM can be set or cleared) */ \
  330. (UTCR3_RXE + UTCR3_TXE)
  331. #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
  332. /* (HP-SIR) modulation Enable */
  333. #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
  334. #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
  335. #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
  336. #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
  337. #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
  338. #define UTDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  339. #if 0 /* Hidden receive FIFO bits */
  340. #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
  341. #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
  342. #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
  343. #endif /* 0 */
  344. #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
  345. /* Service request (read) */
  346. #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
  347. /* more Service request (read) */
  348. #define UTSR0_RID 0x00000004 /* Receiver IDle */
  349. #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
  350. #define UTSR0_REB 0x00000010 /* Receive End of Break */
  351. #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
  352. #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
  353. #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
  354. #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
  355. #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
  356. #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
  357. #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
  358. /*
  359. * Synchronous Data Link Controller (SDLC) control registers
  360. *
  361. * Registers
  362. * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
  363. * Control Register 0 (read/write).
  364. * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
  365. * Control Register 1 (read/write).
  366. * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
  367. * Control Register 2 (read/write).
  368. * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
  369. * Control Register 3 (read/write).
  370. * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
  371. * Control Register 4 (read/write).
  372. * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
  373. * Data Register (read/write).
  374. * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
  375. * Status Register 0 (read/write).
  376. * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
  377. * Status Register 1 (read/write).
  378. *
  379. * Clocks
  380. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  381. * or 3.5795 MHz).
  382. * fsd, Tsd Frequency, period of the SDLC communication.
  383. */
  384. #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
  385. #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
  386. #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
  387. #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
  388. #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
  389. #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
  390. #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
  391. #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
  392. #define SDCR0_SUS 0x00000001 /* SDLC/UART Select */
  393. #define SDCR0_SDLC (SDCR0_SUS*0) /* SDLC mode (TXD1 & RXD1) */
  394. #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
  395. #define SDCR0_SDF 0x00000002 /* Single/Double start Flag select */
  396. #define SDCR0_SglFlg (SDCR0_SDF*0) /* Single start Flag */
  397. #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
  398. #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
  399. #define SDCR0_BMS 0x00000008 /* Bit Modulation Select */
  400. #define SDCR0_FM0 (SDCR0_BMS*0) /* Freq. Modulation zero (0) */
  401. #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
  402. #define SDCR0_SCE 0x00000010 /* Sample Clock Enable (GPIO [16]) */
  403. #define SDCR0_SCD 0x00000020 /* Sample Clock Direction select */
  404. /* (GPIO [16]) */
  405. #define SDCR0_SClkIn (SDCR0_SCD*0) /* Sample Clock Input */
  406. #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
  407. #define SDCR0_RCE 0x00000040 /* Receive Clock Edge select */
  408. #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
  409. #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
  410. #define SDCR0_TCE 0x00000080 /* Transmit Clock Edge select */
  411. #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
  412. #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
  413. #define SDCR1_AAF 0x00000001 /* Abort After Frame enable */
  414. /* (GPIO [17]) */
  415. #define SDCR1_TXE 0x00000002 /* Transmit Enable */
  416. #define SDCR1_RXE 0x00000004 /* Receive Enable */
  417. #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
  418. /* more Interrupt Enable */
  419. #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
  420. /* Interrupt Enable */
  421. #define SDCR1_AME 0x00000020 /* Address Match Enable */
  422. #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
  423. #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
  424. #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
  425. #define SDCR1_RAE 0x00000080 /* Receive Abort interrupt Enable */
  426. #define SDCR2_AMV Fld (8, 0) /* Address Match Value */
  427. #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
  428. #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
  429. /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
  430. /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
  431. #define SDCR3_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  432. (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
  433. FShft (SDCR3_BRD))
  434. #define SDCR4_BdRtDiv(Div) /* Baud Rate Divisor [16..65536] */ \
  435. (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
  436. FShft (SDCR4_BRD))
  437. /* fsd = fxtl/(16*Floor (Div/16)) */
  438. /* Tsd = 16*Floor (Div/16)*Txtl */
  439. #define SDCR3_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  440. (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
  441. FShft (SDCR3_BRD))
  442. #define SDCR4_CeilBdRtDiv(Div) /* Ceil. of BdRtDiv [16..65536] */ \
  443. (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
  444. FShft (SDCR4_BRD))
  445. /* fsd = fxtl/(16*Ceil (Div/16)) */
  446. /* Tsd = 16*Ceil (Div/16)*Txtl */
  447. #define SDDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  448. #if 0 /* Hidden receive FIFO bits */
  449. #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
  450. #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
  451. #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
  452. #endif /* 0 */
  453. #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
  454. #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
  455. #define SDSR0_RAB 0x00000004 /* Receive ABort */
  456. #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
  457. /* Service request (read) */
  458. #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
  459. /* more Service request (read) */
  460. #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
  461. #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
  462. #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
  463. #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
  464. #define SDSR1_RTD 0x00000010 /* Receive Transition Detected */
  465. #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
  466. #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
  467. #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
  468. /*
  469. * High-Speed Serial to Parallel controller (HSSP) control registers
  470. *
  471. * Registers
  472. * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
  473. * controller (HSSP) Control Register 0 (read/write).
  474. * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
  475. * controller (HSSP) Control Register 1 (read/write).
  476. * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
  477. * controller (HSSP) Data Register (read/write).
  478. * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
  479. * controller (HSSP) Status Register 0 (read/write).
  480. * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
  481. * controller (HSSP) Status Register 1 (read).
  482. * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
  483. * controller (HSSP) Control Register 2 (read/write).
  484. * [The HSCR2 register is only implemented in
  485. * versions 2.0 (rev. = 8) and higher of the StrongARM
  486. * SA-1100.]
  487. */
  488. #define Ser2HSCR0 __REG(0x80040060) /* Ser. port 2 HSSP Control Reg. 0 */
  489. #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
  490. #define Ser2HSDR __REG(0x8004006C) /* Ser. port 2 HSSP Data Reg. */
  491. #define Ser2HSSR0 __REG(0x80040074) /* Ser. port 2 HSSP Status Reg. 0 */
  492. #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
  493. #define Ser2HSCR2 __REG(0x90060028) /* Ser. port 2 HSSP Control Reg. 2 */
  494. #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
  495. #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
  496. #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
  497. #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
  498. #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
  499. #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
  500. #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
  501. #define HSCR0_TXE 0x00000008 /* Transmit Enable */
  502. #define HSCR0_RXE 0x00000010 /* Receive Enable */
  503. #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
  504. /* more Interrupt Enable */
  505. #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
  506. /* Interrupt Enable */
  507. #define HSCR0_AME 0x00000080 /* Address Match Enable */
  508. #define HSCR1_AMV Fld (8, 0) /* Address Match Value */
  509. #define HSDR_DATA Fld (8, 0) /* receive/transmit DATA FIFOs */
  510. #if 0 /* Hidden receive FIFO bits */
  511. #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
  512. #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
  513. #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
  514. #endif /* 0 */
  515. #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
  516. #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
  517. #define HSSR0_RAB 0x00000004 /* Receive ABort */
  518. #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
  519. /* Service request (read) */
  520. #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
  521. /* more Service request (read) */
  522. #define HSSR0_FRE 0x00000020 /* receive FRaming Error */
  523. #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
  524. #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
  525. #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
  526. #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
  527. #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
  528. #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
  529. #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
  530. #define HSCR2_TXP 0x00040000 /* Transmit data Polarity (TXD_2) */
  531. #define HSCR2_TrDataL (HSCR2_TXP*0) /* Transmit Data active Low */
  532. /* (inverted) */
  533. #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
  534. /* (non-inverted) */
  535. #define HSCR2_RXP 0x00080000 /* Receive data Polarity (RXD_2) */
  536. #define HSCR2_RcDataL (HSCR2_RXP*0) /* Receive Data active Low */
  537. /* (inverted) */
  538. #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
  539. /* (non-inverted) */
  540. /*
  541. * Multi-media Communications Port (MCP) control registers
  542. *
  543. * Registers
  544. * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
  545. * Control Register 0 (read/write).
  546. * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
  547. * Data Register 0 (audio, read/write).
  548. * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
  549. * Data Register 1 (telecom, read/write).
  550. * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
  551. * Data Register 2 (CODEC registers, read/write).
  552. * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
  553. * Status Register (read/write).
  554. * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
  555. * Control Register 1 (read/write).
  556. * [The MCCR1 register is only implemented in
  557. * versions 2.0 (rev. = 8) and higher of the StrongARM
  558. * SA-1100.]
  559. *
  560. * Clocks
  561. * fmc, Tmc Frequency, period of the MCP communication (10 MHz,
  562. * 12 MHz, or GPIO [21]).
  563. * faud, Taud Frequency, period of the audio sampling.
  564. * ftcm, Ttcm Frequency, period of the telecom sampling.
  565. */
  566. #define Ser4MCCR0 __REG(0x80060000) /* Ser. port 4 MCP Control Reg. 0 */
  567. #define Ser4MCDR0 __REG(0x80060008) /* Ser. port 4 MCP Data Reg. 0 (audio) */
  568. #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
  569. #define Ser4MCDR2 __REG(0x80060010) /* Ser. port 4 MCP Data Reg. 2 (CODEC reg.) */
  570. #define Ser4MCSR __REG(0x80060018) /* Ser. port 4 MCP Status Reg. */
  571. #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
  572. #define MCCR0_ASD Fld (7, 0) /* Audio Sampling rate Divisor/32 */
  573. /* [6..127] */
  574. /* faud = fmc/(32*ASD) */
  575. /* Taud = 32*ASD*Tmc */
  576. #define MCCR0_AudSmpDiv(Div) /* Audio Sampling rate Divisor */ \
  577. /* [192..4064] */ \
  578. ((Div)/32 << FShft (MCCR0_ASD))
  579. /* faud = fmc/(32*Floor (Div/32)) */
  580. /* Taud = 32*Floor (Div/32)*Tmc */
  581. #define MCCR0_CeilAudSmpDiv(Div) /* Ceil. of AudSmpDiv [192..4064] */ \
  582. (((Div) + 31)/32 << FShft (MCCR0_ASD))
  583. /* faud = fmc/(32*Ceil (Div/32)) */
  584. /* Taud = 32*Ceil (Div/32)*Tmc */
  585. #define MCCR0_TSD Fld (7, 8) /* Telecom Sampling rate */
  586. /* Divisor/32 [16..127] */
  587. /* ftcm = fmc/(32*TSD) */
  588. /* Ttcm = 32*TSD*Tmc */
  589. #define MCCR0_TcmSmpDiv(Div) /* Telecom Sampling rate Divisor */ \
  590. /* [512..4064] */ \
  591. ((Div)/32 << FShft (MCCR0_TSD))
  592. /* ftcm = fmc/(32*Floor (Div/32)) */
  593. /* Ttcm = 32*Floor (Div/32)*Tmc */
  594. #define MCCR0_CeilTcmSmpDiv(Div) /* Ceil. of TcmSmpDiv [512..4064] */ \
  595. (((Div) + 31)/32 << FShft (MCCR0_TSD))
  596. /* ftcm = fmc/(32*Ceil (Div/32)) */
  597. /* Ttcm = 32*Ceil (Div/32)*Tmc */
  598. #define MCCR0_MCE 0x00010000 /* MCP Enable */
  599. #define MCCR0_ECS 0x00020000 /* External Clock Select */
  600. #define MCCR0_IntClk (MCCR0_ECS*0) /* Internal Clock (10 or 12 MHz) */
  601. #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
  602. #define MCCR0_ADM 0x00040000 /* A/D (audio/telecom) data */
  603. /* sampling/storing Mode */
  604. #define MCCR0_VldBit (MCCR0_ADM*0) /* Valid Bit storing mode */
  605. #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
  606. #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
  607. /* or less interrupt Enable */
  608. #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
  609. /* or more interrupt Enable */
  610. #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
  611. /* or less interrupt Enable */
  612. #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
  613. /* more interrupt Enable */
  614. #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
  615. #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
  616. #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
  617. (((Div) - 1) << FShft (MCCR0_ECP))
  618. #define MCDR0_DATA Fld (12, 4) /* receive/transmit audio DATA */
  619. /* FIFOs */
  620. #define MCDR1_DATA Fld (14, 2) /* receive/transmit telecom DATA */
  621. /* FIFOs */
  622. /* receive/transmit CODEC reg. */
  623. /* FIFOs: */
  624. #define MCDR2_DATA Fld (16, 0) /* reg. DATA */
  625. #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
  626. #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
  627. #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
  628. #define MCDR2_ADD Fld (4, 17) /* reg. ADDress */
  629. #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
  630. /* or less Service request (read) */
  631. #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
  632. /* more Service request (read) */
  633. #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
  634. /* or less Service request (read) */
  635. #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
  636. /* or more Service request (read) */
  637. #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
  638. #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
  639. #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
  640. #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
  641. #define MCSR_ANF 0x00000100 /* Audio transmit FIFO Not Full */
  642. /* (read) */
  643. #define MCSR_ANE 0x00000200 /* Audio receive FIFO Not Empty */
  644. /* (read) */
  645. #define MCSR_TNF 0x00000400 /* Telecom transmit FIFO Not Full */
  646. /* (read) */
  647. #define MCSR_TNE 0x00000800 /* Telecom receive FIFO Not Empty */
  648. /* (read) */
  649. #define MCSR_CWC 0x00001000 /* CODEC register Write Completed */
  650. /* (read) */
  651. #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
  652. /* (read) */
  653. #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
  654. #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
  655. #define MCCR1_CFS 0x00100000 /* Clock Freq. Select */
  656. #define MCCR1_F12MHz (MCCR1_CFS*0) /* Freq. (fmc) = ~ 12 MHz */
  657. /* (11.981 MHz) */
  658. #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
  659. /* (9.585 MHz) */
  660. /*
  661. * Synchronous Serial Port (SSP) control registers
  662. *
  663. * Registers
  664. * Ser4SSCR0 Serial port 4 Synchronous Serial Port (SSP) Control
  665. * Register 0 (read/write).
  666. * Ser4SSCR1 Serial port 4 Synchronous Serial Port (SSP) Control
  667. * Register 1 (read/write).
  668. * [Bits SPO and SP are only implemented in versions 2.0
  669. * (rev. = 8) and higher of the StrongARM SA-1100.]
  670. * Ser4SSDR Serial port 4 Synchronous Serial Port (SSP) Data
  671. * Register (read/write).
  672. * Ser4SSSR Serial port 4 Synchronous Serial Port (SSP) Status
  673. * Register (read/write).
  674. *
  675. * Clocks
  676. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  677. * or 3.5795 MHz).
  678. * fss, Tss Frequency, period of the SSP communication.
  679. */
  680. #define Ser4SSCR0 __REG(0x80070060) /* Ser. port 4 SSP Control Reg. 0 */
  681. #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
  682. #define Ser4SSDR __REG(0x8007006C) /* Ser. port 4 SSP Data Reg. */
  683. #define Ser4SSSR __REG(0x80070074) /* Ser. port 4 SSP Status Reg. */
  684. #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
  685. #define SSCR0_DataSize(Size) /* Data Size Select [4..16] */ \
  686. (((Size) - 1) << FShft (SSCR0_DSS))
  687. #define SSCR0_FRF Fld (2, 4) /* FRame Format */
  688. #define SSCR0_Motorola /* Motorola Serial Peripheral */ \
  689. /* Interface (SPI) format */ \
  690. (0 << FShft (SSCR0_FRF))
  691. #define SSCR0_TI /* Texas Instruments Synchronous */ \
  692. /* Serial format */ \
  693. (1 << FShft (SSCR0_FRF))
  694. #define SSCR0_National /* National Microwire format */ \
  695. (2 << FShft (SSCR0_FRF))
  696. #define SSCR0_SSE 0x00000080 /* SSP Enable */
  697. #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
  698. /* fss = fxtl/(2*(SCR + 1)) */
  699. /* Tss = 2*(SCR + 1)*Txtl */
  700. #define SSCR0_SerClkDiv(Div) /* Serial Clock Divisor [2..512] */ \
  701. (((Div) - 2)/2 << FShft (SSCR0_SCR))
  702. /* fss = fxtl/(2*Floor (Div/2)) */
  703. /* Tss = 2*Floor (Div/2)*Txtl */
  704. #define SSCR0_CeilSerClkDiv(Div) /* Ceil. of SerClkDiv [2..512] */ \
  705. (((Div) - 1)/2 << FShft (SSCR0_SCR))
  706. /* fss = fxtl/(2*Ceil (Div/2)) */
  707. /* Tss = 2*Ceil (Div/2)*Txtl */
  708. #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
  709. /* Interrupt Enable */
  710. #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
  711. /* Interrupt Enable */
  712. #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
  713. #define SSCR1_SPO 0x00000008 /* Sample clock (SCLK) POlarity */
  714. #define SSCR1_SClkIactL (SSCR1_SPO*0) /* Sample Clock Inactive Low */
  715. #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
  716. #define SSCR1_SP 0x00000010 /* Sample clock (SCLK) Phase */
  717. #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
  718. /* after frame (SFRM, 1st edge) */
  719. #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
  720. /* after frame (SFRM, 1st edge) */
  721. #define SSCR1_ECS 0x00000020 /* External Clock Select */
  722. #define SSCR1_IntClk (SSCR1_ECS*0) /* Internal Clock */
  723. #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
  724. #define SSDR_DATA Fld (16, 0) /* receive/transmit DATA FIFOs */
  725. #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
  726. #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
  727. #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
  728. #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
  729. /* Service request (read) */
  730. #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
  731. /* Service request (read) */
  732. #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
  733. /*
  734. * Operating System (OS) timer control registers
  735. *
  736. * Registers
  737. * OSMR0 Operating System (OS) timer Match Register 0
  738. * (read/write).
  739. * OSMR1 Operating System (OS) timer Match Register 1
  740. * (read/write).
  741. * OSMR2 Operating System (OS) timer Match Register 2
  742. * (read/write).
  743. * OSMR3 Operating System (OS) timer Match Register 3
  744. * (read/write).
  745. * OSCR Operating System (OS) timer Counter Register
  746. * (read/write).
  747. * OSSR Operating System (OS) timer Status Register
  748. * (read/write).
  749. * OWER Operating System (OS) timer Watch-dog Enable Register
  750. * (read/write).
  751. * OIER Operating System (OS) timer Interrupt Enable Register
  752. * (read/write).
  753. */
  754. #define OSMR0 __REG(0x90000000) /* OS timer Match Reg. 0 */
  755. #define OSMR1 __REG(0x90000004) /* OS timer Match Reg. 1 */
  756. #define OSMR2 __REG(0x90000008) /* OS timer Match Reg. 2 */
  757. #define OSMR3 __REG(0x9000000c) /* OS timer Match Reg. 3 */
  758. #define OSCR __REG(0x90000010) /* OS timer Counter Reg. */
  759. #define OSSR __REG(0x90000014 ) /* OS timer Status Reg. */
  760. #define OWER __REG(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
  761. #define OIER __REG(0x9000001C ) /* OS timer Interrupt Enable Reg. */
  762. #define OSSR_M(Nb) /* Match detected [0..3] */ \
  763. (0x00000001 << (Nb))
  764. #define OSSR_M0 OSSR_M (0) /* Match detected 0 */
  765. #define OSSR_M1 OSSR_M (1) /* Match detected 1 */
  766. #define OSSR_M2 OSSR_M (2) /* Match detected 2 */
  767. #define OSSR_M3 OSSR_M (3) /* Match detected 3 */
  768. #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
  769. /* (set only) */
  770. #define OIER_E(Nb) /* match interrupt Enable [0..3] */ \
  771. (0x00000001 << (Nb))
  772. #define OIER_E0 OIER_E (0) /* match interrupt Enable 0 */
  773. #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
  774. #define OIER_E2 OIER_E (2) /* match interrupt Enable 2 */
  775. #define OIER_E3 OIER_E (3) /* match interrupt Enable 3 */
  776. /*
  777. * Real-Time Clock (RTC) control registers
  778. *
  779. * Registers
  780. * RTAR Real-Time Clock (RTC) Alarm Register (read/write).
  781. * RCNR Real-Time Clock (RTC) CouNt Register (read/write).
  782. * RTTR Real-Time Clock (RTC) Trim Register (read/write).
  783. * RTSR Real-Time Clock (RTC) Status Register (read/write).
  784. *
  785. * Clocks
  786. * frtx, Trtx Frequency, period of the real-time clock crystal
  787. * (32.768 kHz nominal).
  788. * frtc, Trtc Frequency, period of the real-time clock counter
  789. * (1 Hz nominal).
  790. */
  791. #define RTAR __REG(0x90010000) /* RTC Alarm Reg. */
  792. #define RCNR __REG(0x90010004) /* RTC CouNt Reg. */
  793. #define RTTR __REG(0x90010008) /* RTC Trim Reg. */
  794. #define RTSR __REG(0x90010010) /* RTC Status Reg. */
  795. #define RTTR_C Fld (16, 0) /* clock divider Count - 1 */
  796. #define RTTR_D Fld (10, 16) /* trim Delete count */
  797. /* frtc = (1023*(C + 1) - D)*frtx/ */
  798. /* (1023*(C + 1)^2) */
  799. /* Trtc = (1023*(C + 1)^2)*Trtx/ */
  800. /* (1023*(C + 1) - D) */
  801. #define RTSR_AL 0x00000001 /* ALarm detected */
  802. #define RTSR_HZ 0x00000002 /* 1 Hz clock detected */
  803. #define RTSR_ALE 0x00000004 /* ALarm interrupt Enable */
  804. #define RTSR_HZE 0x00000008 /* 1 Hz clock interrupt Enable */
  805. /*
  806. * Power Manager (PM) control registers
  807. *
  808. * Registers
  809. * PMCR Power Manager (PM) Control Register (read/write).
  810. * PSSR Power Manager (PM) Sleep Status Register (read/write).
  811. * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
  812. * PWER Power Manager (PM) Wake-up Enable Register
  813. * (read/write).
  814. * PCFR Power Manager (PM) general ConFiguration Register
  815. * (read/write).
  816. * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
  817. * Configuration Register (read/write).
  818. * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
  819. * Sleep state Register (read/write, see GPIO pins).
  820. * POSR Power Manager (PM) Oscillator Status Register (read).
  821. *
  822. * Clocks
  823. * fxtl, Txtl Frequency, period of the system crystal (3.6864 MHz
  824. * or 3.5795 MHz).
  825. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  826. */
  827. #define PMCR __REG(0x90020000) /* PM Control Reg. */
  828. #define PSSR __REG(0x90020004) /* PM Sleep Status Reg. */
  829. #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
  830. #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
  831. #define PCFR __REG(0x90020010) /* PM general ConFiguration Reg. */
  832. #define PPCR __REG(0x90020014) /* PM PLL Configuration Reg. */
  833. #define PGSR __REG(0x90020018) /* PM GPIO Sleep state Reg. */
  834. #define POSR __REG(0x9002001C) /* PM Oscillator Status Reg. */
  835. #define PMCR_SF 0x00000001 /* Sleep Force (set only) */
  836. #define PSSR_SS 0x00000001 /* Software Sleep */
  837. #define PSSR_BFS 0x00000002 /* Battery Fault Status */
  838. /* (BATT_FAULT) */
  839. #define PSSR_VFS 0x00000004 /* Vdd Fault Status (VDD_FAULT) */
  840. #define PSSR_DH 0x00000008 /* DRAM control Hold */
  841. #define PSSR_PH 0x00000010 /* Peripheral control Hold */
  842. #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
  843. #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
  844. #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
  845. #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
  846. #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
  847. #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
  848. #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
  849. #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
  850. #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
  851. #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
  852. #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
  853. #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
  854. #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
  855. #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
  856. #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
  857. #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
  858. #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
  859. #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
  860. #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
  861. #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
  862. #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
  863. #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
  864. #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
  865. #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
  866. #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
  867. #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
  868. #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
  869. #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
  870. #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
  871. #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
  872. #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
  873. #define PCFR_ClkRun (PCFR_OPDE*0) /* Clock Running in sleep mode */
  874. #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
  875. #define PCFR_FP 0x00000002 /* Float PCMCIA pins */
  876. #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
  877. #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
  878. #define PCFR_FS 0x00000004 /* Float Static memory pins */
  879. #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
  880. #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
  881. #define PCFR_FO 0x00000008 /* Force RTC oscillator */
  882. /* (32.768 kHz) enable On */
  883. #define PPCR_CCF Fld (5, 0) /* CPU core Clock (CCLK) Freq. */
  884. #define PPCR_Fx16 /* Freq. x 16 (fcpu = 16*fxtl) */ \
  885. (0x00 << FShft (PPCR_CCF))
  886. #define PPCR_Fx20 /* Freq. x 20 (fcpu = 20*fxtl) */ \
  887. (0x01 << FShft (PPCR_CCF))
  888. #define PPCR_Fx24 /* Freq. x 24 (fcpu = 24*fxtl) */ \
  889. (0x02 << FShft (PPCR_CCF))
  890. #define PPCR_Fx28 /* Freq. x 28 (fcpu = 28*fxtl) */ \
  891. (0x03 << FShft (PPCR_CCF))
  892. #define PPCR_Fx32 /* Freq. x 32 (fcpu = 32*fxtl) */ \
  893. (0x04 << FShft (PPCR_CCF))
  894. #define PPCR_Fx36 /* Freq. x 36 (fcpu = 36*fxtl) */ \
  895. (0x05 << FShft (PPCR_CCF))
  896. #define PPCR_Fx40 /* Freq. x 40 (fcpu = 40*fxtl) */ \
  897. (0x06 << FShft (PPCR_CCF))
  898. #define PPCR_Fx44 /* Freq. x 44 (fcpu = 44*fxtl) */ \
  899. (0x07 << FShft (PPCR_CCF))
  900. #define PPCR_Fx48 /* Freq. x 48 (fcpu = 48*fxtl) */ \
  901. (0x08 << FShft (PPCR_CCF))
  902. #define PPCR_Fx52 /* Freq. x 52 (fcpu = 52*fxtl) */ \
  903. (0x09 << FShft (PPCR_CCF))
  904. #define PPCR_Fx56 /* Freq. x 56 (fcpu = 56*fxtl) */ \
  905. (0x0A << FShft (PPCR_CCF))
  906. #define PPCR_Fx60 /* Freq. x 60 (fcpu = 60*fxtl) */ \
  907. (0x0B << FShft (PPCR_CCF))
  908. #define PPCR_Fx64 /* Freq. x 64 (fcpu = 64*fxtl) */ \
  909. (0x0C << FShft (PPCR_CCF))
  910. #define PPCR_Fx68 /* Freq. x 68 (fcpu = 68*fxtl) */ \
  911. (0x0D << FShft (PPCR_CCF))
  912. #define PPCR_Fx72 /* Freq. x 72 (fcpu = 72*fxtl) */ \
  913. (0x0E << FShft (PPCR_CCF))
  914. #define PPCR_Fx76 /* Freq. x 76 (fcpu = 76*fxtl) */ \
  915. (0x0F << FShft (PPCR_CCF))
  916. /* 3.6864 MHz crystal (fxtl): */
  917. #define PPCR_F59_0MHz PPCR_Fx16 /* Freq. (fcpu) = 59.0 MHz */
  918. #define PPCR_F73_7MHz PPCR_Fx20 /* Freq. (fcpu) = 73.7 MHz */
  919. #define PPCR_F88_5MHz PPCR_Fx24 /* Freq. (fcpu) = 88.5 MHz */
  920. #define PPCR_F103_2MHz PPCR_Fx28 /* Freq. (fcpu) = 103.2 MHz */
  921. #define PPCR_F118_0MHz PPCR_Fx32 /* Freq. (fcpu) = 118.0 MHz */
  922. #define PPCR_F132_7MHz PPCR_Fx36 /* Freq. (fcpu) = 132.7 MHz */
  923. #define PPCR_F147_5MHz PPCR_Fx40 /* Freq. (fcpu) = 147.5 MHz */
  924. #define PPCR_F162_2MHz PPCR_Fx44 /* Freq. (fcpu) = 162.2 MHz */
  925. #define PPCR_F176_9MHz PPCR_Fx48 /* Freq. (fcpu) = 176.9 MHz */
  926. #define PPCR_F191_7MHz PPCR_Fx52 /* Freq. (fcpu) = 191.7 MHz */
  927. #define PPCR_F206_4MHz PPCR_Fx56 /* Freq. (fcpu) = 206.4 MHz */
  928. #define PPCR_F221_2MHz PPCR_Fx60 /* Freq. (fcpu) = 221.2 MHz */
  929. #define PPCR_F239_6MHz PPCR_Fx64 /* Freq. (fcpu) = 239.6 MHz */
  930. #define PPCR_F250_7MHz PPCR_Fx68 /* Freq. (fcpu) = 250.7 MHz */
  931. #define PPCR_F265_4MHz PPCR_Fx72 /* Freq. (fcpu) = 265.4 MHz */
  932. #define PPCR_F280_2MHz PPCR_Fx76 /* Freq. (fcpu) = 280.2 MHz */
  933. /* 3.5795 MHz crystal (fxtl): */
  934. #define PPCR_F57_3MHz PPCR_Fx16 /* Freq. (fcpu) = 57.3 MHz */
  935. #define PPCR_F71_6MHz PPCR_Fx20 /* Freq. (fcpu) = 71.6 MHz */
  936. #define PPCR_F85_9MHz PPCR_Fx24 /* Freq. (fcpu) = 85.9 MHz */
  937. #define PPCR_F100_2MHz PPCR_Fx28 /* Freq. (fcpu) = 100.2 MHz */
  938. #define PPCR_F114_5MHz PPCR_Fx32 /* Freq. (fcpu) = 114.5 MHz */
  939. #define PPCR_F128_9MHz PPCR_Fx36 /* Freq. (fcpu) = 128.9 MHz */
  940. #define PPCR_F143_2MHz PPCR_Fx40 /* Freq. (fcpu) = 143.2 MHz */
  941. #define PPCR_F157_5MHz PPCR_Fx44 /* Freq. (fcpu) = 157.5 MHz */
  942. #define PPCR_F171_8MHz PPCR_Fx48 /* Freq. (fcpu) = 171.8 MHz */
  943. #define PPCR_F186_1MHz PPCR_Fx52 /* Freq. (fcpu) = 186.1 MHz */
  944. #define PPCR_F200_5MHz PPCR_Fx56 /* Freq. (fcpu) = 200.5 MHz */
  945. #define PPCR_F214_8MHz PPCR_Fx60 /* Freq. (fcpu) = 214.8 MHz */
  946. #define PPCR_F229_1MHz PPCR_Fx64 /* Freq. (fcpu) = 229.1 MHz */
  947. #define PPCR_F243_4MHz PPCR_Fx68 /* Freq. (fcpu) = 243.4 MHz */
  948. #define PPCR_F257_7MHz PPCR_Fx72 /* Freq. (fcpu) = 257.7 MHz */
  949. #define PPCR_F272_0MHz PPCR_Fx76 /* Freq. (fcpu) = 272.0 MHz */
  950. #define POSR_OOK 0x00000001 /* RTC Oscillator (32.768 kHz) OK */
  951. /*
  952. * Reset Controller (RC) control registers
  953. *
  954. * Registers
  955. * RSRR Reset Controller (RC) Software Reset Register
  956. * (read/write).
  957. * RCSR Reset Controller (RC) Status Register (read/write).
  958. */
  959. #define RSRR __REG(0x90030000) /* RC Software Reset Reg. */
  960. #define RCSR __REG(0x90030004) /* RC Status Reg. */
  961. #define RSRR_SWR 0x00000001 /* SoftWare Reset (set only) */
  962. #define RCSR_HWR 0x00000001 /* HardWare Reset */
  963. #define RCSR_SWR 0x00000002 /* SoftWare Reset */
  964. #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
  965. #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
  966. /*
  967. * Test unit control registers
  968. *
  969. * Registers
  970. * TUCR Test Unit Control Register (read/write).
  971. */
  972. #define TUCR __REG(0x90030008) /* Test Unit Control Reg. */
  973. #define TUCR_TIC 0x00000040 /* TIC mode */
  974. #define TUCR_TTST 0x00000080 /* Trim TeST mode */
  975. #define TUCR_RCRC 0x00000100 /* Richard's Cyclic Redundancy */
  976. /* Check */
  977. #define TUCR_PMD 0x00000200 /* Power Management Disable */
  978. #define TUCR_MR 0x00000400 /* Memory Request mode */
  979. #define TUCR_NoMB (TUCR_MR*0) /* No Memory Bus request & grant */
  980. #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
  981. /* grant (MBGNT) on GPIO [22:21] */
  982. #define TUCR_CTB Fld (3, 20) /* Clock Test Bits */
  983. #define TUCR_FDC 0x00800000 /* RTC Force Delete Count */
  984. #define TUCR_FMC 0x01000000 /* Force Michelle's Control mode */
  985. #define TUCR_TMC 0x02000000 /* RTC Trimmer Multiplexer Control */
  986. #define TUCR_DPS 0x04000000 /* Disallow Pad Sleep */
  987. #define TUCR_TSEL Fld (3, 29) /* clock Test SELect on GPIO [27] */
  988. #define TUCR_32_768kHz /* 32.768 kHz osc. on GPIO [27] */ \
  989. (0 << FShft (TUCR_TSEL))
  990. #define TUCR_3_6864MHz /* 3.6864 MHz osc. on GPIO [27] */ \
  991. (1 << FShft (TUCR_TSEL))
  992. #define TUCR_VDD /* VDD ring osc./16 on GPIO [27] */ \
  993. (2 << FShft (TUCR_TSEL))
  994. #define TUCR_96MHzPLL /* 96 MHz PLL/4 on GPIO [27] */ \
  995. (3 << FShft (TUCR_TSEL))
  996. #define TUCR_Clock /* internal (fcpu/2) & 32.768 kHz */ \
  997. /* Clocks on GPIO [26:27] */ \
  998. (4 << FShft (TUCR_TSEL))
  999. #define TUCR_3_6864MHzA /* 3.6864 MHz osc. on GPIO [27] */ \
  1000. /* (Alternative) */ \
  1001. (5 << FShft (TUCR_TSEL))
  1002. #define TUCR_MainPLL /* Main PLL/16 on GPIO [27] */ \
  1003. (6 << FShft (TUCR_TSEL))
  1004. #define TUCR_VDDL /* VDDL ring osc./4 on GPIO [27] */ \
  1005. (7 << FShft (TUCR_TSEL))
  1006. /*
  1007. * General-Purpose Input/Output (GPIO) control registers
  1008. *
  1009. * Registers
  1010. * GPLR General-Purpose Input/Output (GPIO) Pin Level
  1011. * Register (read).
  1012. * GPDR General-Purpose Input/Output (GPIO) Pin Direction
  1013. * Register (read/write).
  1014. * GPSR General-Purpose Input/Output (GPIO) Pin output Set
  1015. * Register (write).
  1016. * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
  1017. * Register (write).
  1018. * GRER General-Purpose Input/Output (GPIO) Rising-Edge
  1019. * detect Register (read/write).
  1020. * GFER General-Purpose Input/Output (GPIO) Falling-Edge
  1021. * detect Register (read/write).
  1022. * GEDR General-Purpose Input/Output (GPIO) Edge Detect
  1023. * status Register (read/write).
  1024. * GAFR General-Purpose Input/Output (GPIO) Alternate
  1025. * Function Register (read/write).
  1026. *
  1027. * Clock
  1028. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1029. */
  1030. #define GPLR __REG(0x90040000) /* GPIO Pin Level Reg. */
  1031. #define GPDR __REG(0x90040004) /* GPIO Pin Direction Reg. */
  1032. #define GPSR __REG(0x90040008) /* GPIO Pin output Set Reg. */
  1033. #define GPCR __REG(0x9004000C) /* GPIO Pin output Clear Reg. */
  1034. #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
  1035. #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
  1036. #define GEDR __REG(0x90040018) /* GPIO Edge Detect status Reg. */
  1037. #define GAFR __REG(0x9004001C) /* GPIO Alternate Function Reg. */
  1038. #define GPIO_MIN (0)
  1039. #define GPIO_MAX (27)
  1040. #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
  1041. (0x00000001 << (Nb))
  1042. #define GPIO_GPIO0 GPIO_GPIO (0) /* GPIO [0] */
  1043. #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
  1044. #define GPIO_GPIO2 GPIO_GPIO (2) /* GPIO [2] */
  1045. #define GPIO_GPIO3 GPIO_GPIO (3) /* GPIO [3] */
  1046. #define GPIO_GPIO4 GPIO_GPIO (4) /* GPIO [4] */
  1047. #define GPIO_GPIO5 GPIO_GPIO (5) /* GPIO [5] */
  1048. #define GPIO_GPIO6 GPIO_GPIO (6) /* GPIO [6] */
  1049. #define GPIO_GPIO7 GPIO_GPIO (7) /* GPIO [7] */
  1050. #define GPIO_GPIO8 GPIO_GPIO (8) /* GPIO [8] */
  1051. #define GPIO_GPIO9 GPIO_GPIO (9) /* GPIO [9] */
  1052. #define GPIO_GPIO10 GPIO_GPIO (10) /* GPIO [10] */
  1053. #define GPIO_GPIO11 GPIO_GPIO (11) /* GPIO [11] */
  1054. #define GPIO_GPIO12 GPIO_GPIO (12) /* GPIO [12] */
  1055. #define GPIO_GPIO13 GPIO_GPIO (13) /* GPIO [13] */
  1056. #define GPIO_GPIO14 GPIO_GPIO (14) /* GPIO [14] */
  1057. #define GPIO_GPIO15 GPIO_GPIO (15) /* GPIO [15] */
  1058. #define GPIO_GPIO16 GPIO_GPIO (16) /* GPIO [16] */
  1059. #define GPIO_GPIO17 GPIO_GPIO (17) /* GPIO [17] */
  1060. #define GPIO_GPIO18 GPIO_GPIO (18) /* GPIO [18] */
  1061. #define GPIO_GPIO19 GPIO_GPIO (19) /* GPIO [19] */
  1062. #define GPIO_GPIO20 GPIO_GPIO (20) /* GPIO [20] */
  1063. #define GPIO_GPIO21 GPIO_GPIO (21) /* GPIO [21] */
  1064. #define GPIO_GPIO22 GPIO_GPIO (22) /* GPIO [22] */
  1065. #define GPIO_GPIO23 GPIO_GPIO (23) /* GPIO [23] */
  1066. #define GPIO_GPIO24 GPIO_GPIO (24) /* GPIO [24] */
  1067. #define GPIO_GPIO25 GPIO_GPIO (25) /* GPIO [25] */
  1068. #define GPIO_GPIO26 GPIO_GPIO (26) /* GPIO [26] */
  1069. #define GPIO_GPIO27 GPIO_GPIO (27) /* GPIO [27] */
  1070. #define GPIO_LDD(Nb) /* LCD Data [8..15] (O) */ \
  1071. GPIO_GPIO ((Nb) - 6)
  1072. #define GPIO_LDD8 GPIO_LDD (8) /* LCD Data [8] (O) */
  1073. #define GPIO_LDD9 GPIO_LDD (9) /* LCD Data [9] (O) */
  1074. #define GPIO_LDD10 GPIO_LDD (10) /* LCD Data [10] (O) */
  1075. #define GPIO_LDD11 GPIO_LDD (11) /* LCD Data [11] (O) */
  1076. #define GPIO_LDD12 GPIO_LDD (12) /* LCD Data [12] (O) */
  1077. #define GPIO_LDD13 GPIO_LDD (13) /* LCD Data [13] (O) */
  1078. #define GPIO_LDD14 GPIO_LDD (14) /* LCD Data [14] (O) */
  1079. #define GPIO_LDD15 GPIO_LDD (15) /* LCD Data [15] (O) */
  1080. /* ser. port 4: */
  1081. #define GPIO_SSP_TXD GPIO_GPIO (10) /* SSP Transmit Data (O) */
  1082. #define GPIO_SSP_RXD GPIO_GPIO (11) /* SSP Receive Data (I) */
  1083. #define GPIO_SSP_SCLK GPIO_GPIO (12) /* SSP Sample CLocK (O) */
  1084. #define GPIO_SSP_SFRM GPIO_GPIO (13) /* SSP Sample FRaMe (O) */
  1085. /* ser. port 1: */
  1086. #define GPIO_UART_TXD GPIO_GPIO (14) /* UART Transmit Data (O) */
  1087. #define GPIO_UART_RXD GPIO_GPIO (15) /* UART Receive Data (I) */
  1088. #define GPIO_SDLC_SCLK GPIO_GPIO (16) /* SDLC Sample CLocK (I/O) */
  1089. #define GPIO_SDLC_AAF GPIO_GPIO (17) /* SDLC Abort After Frame (O) */
  1090. #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
  1091. /* ser. port 4: */
  1092. #define GPIO_SSP_CLK GPIO_GPIO (19) /* SSP external CLocK (I) */
  1093. /* ser. port 3: */
  1094. #define GPIO_UART_SCLK3 GPIO_GPIO (20) /* UART Sample CLocK 3 (I) */
  1095. /* ser. port 4: */
  1096. #define GPIO_MCP_CLK GPIO_GPIO (21) /* MCP CLocK (I) */
  1097. /* test controller: */
  1098. #define GPIO_TIC_ACK GPIO_GPIO (21) /* TIC ACKnowledge (O) */
  1099. #define GPIO_MBGNT GPIO_GPIO (21) /* Memory Bus GraNT (O) */
  1100. #define GPIO_TREQA GPIO_GPIO (22) /* TIC REQuest A (I) */
  1101. #define GPIO_MBREQ GPIO_GPIO (22) /* Memory Bus REQuest (I) */
  1102. #define GPIO_TREQB GPIO_GPIO (23) /* TIC REQuest B (I) */
  1103. #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
  1104. #define GPIO_RCLK GPIO_GPIO (26) /* internal (R) CLocK (O, fcpu/2) */
  1105. #define GPIO_32_768kHz GPIO_GPIO (27) /* 32.768 kHz clock (O, RTC) */
  1106. #define GPDR_In 0 /* Input */
  1107. #define GPDR_Out 1 /* Output */
  1108. /*
  1109. * Interrupt Controller (IC) control registers
  1110. *
  1111. * Registers
  1112. * ICIP Interrupt Controller (IC) Interrupt ReQuest (IRQ)
  1113. * Pending register (read).
  1114. * ICMR Interrupt Controller (IC) Mask Register (read/write).
  1115. * ICLR Interrupt Controller (IC) Level Register (read/write).
  1116. * ICCR Interrupt Controller (IC) Control Register
  1117. * (read/write).
  1118. * [The ICCR register is only implemented in versions 2.0
  1119. * (rev. = 8) and higher of the StrongARM SA-1100.]
  1120. * ICFP Interrupt Controller (IC) Fast Interrupt reQuest
  1121. * (FIQ) Pending register (read).
  1122. * ICPR Interrupt Controller (IC) Pending Register (read).
  1123. * [The ICPR register is active low (inverted) in
  1124. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  1125. * StrongARM SA-1100, it is active high (non-inverted) in
  1126. * versions 2.0 (rev. = 8) and higher.]
  1127. */
  1128. #define ICIP __REG(0x90050000) /* IC IRQ Pending reg. */
  1129. #define ICMR __REG(0x90050004) /* IC Mask Reg. */
  1130. #define ICLR __REG(0x90050008) /* IC Level Reg. */
  1131. #define ICCR __REG(0x9005000C) /* IC Control Reg. */
  1132. #define ICFP __REG(0x90050010) /* IC FIQ Pending reg. */
  1133. #define ICPR __REG(0x90050020) /* IC Pending Reg. */
  1134. #define IC_GPIO(Nb) /* GPIO [0..10] */ \
  1135. (0x00000001 << (Nb))
  1136. #define IC_GPIO0 IC_GPIO (0) /* GPIO [0] */
  1137. #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
  1138. #define IC_GPIO2 IC_GPIO (2) /* GPIO [2] */
  1139. #define IC_GPIO3 IC_GPIO (3) /* GPIO [3] */
  1140. #define IC_GPIO4 IC_GPIO (4) /* GPIO [4] */
  1141. #define IC_GPIO5 IC_GPIO (5) /* GPIO [5] */
  1142. #define IC_GPIO6 IC_GPIO (6) /* GPIO [6] */
  1143. #define IC_GPIO7 IC_GPIO (7) /* GPIO [7] */
  1144. #define IC_GPIO8 IC_GPIO (8) /* GPIO [8] */
  1145. #define IC_GPIO9 IC_GPIO (9) /* GPIO [9] */
  1146. #define IC_GPIO10 IC_GPIO (10) /* GPIO [10] */
  1147. #define IC_GPIO11_27 0x00000800 /* GPIO [11:27] (ORed) */
  1148. #define IC_LCD 0x00001000 /* LCD controller */
  1149. #define IC_Ser0UDC 0x00002000 /* Ser. port 0 UDC */
  1150. #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
  1151. #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
  1152. #define IC_Ser2ICP 0x00010000 /* Ser. port 2 ICP */
  1153. #define IC_Ser3UART 0x00020000 /* Ser. port 3 UART */
  1154. #define IC_Ser4MCP 0x00040000 /* Ser. port 4 MCP */
  1155. #define IC_Ser4SSP 0x00080000 /* Ser. port 4 SSP */
  1156. #define IC_DMA(Nb) /* DMA controller channel [0..5] */ \
  1157. (0x00100000 << (Nb))
  1158. #define IC_DMA0 IC_DMA (0) /* DMA controller channel 0 */
  1159. #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
  1160. #define IC_DMA2 IC_DMA (2) /* DMA controller channel 2 */
  1161. #define IC_DMA3 IC_DMA (3) /* DMA controller channel 3 */
  1162. #define IC_DMA4 IC_DMA (4) /* DMA controller channel 4 */
  1163. #define IC_DMA5 IC_DMA (5) /* DMA controller channel 5 */
  1164. #define IC_OST(Nb) /* OS Timer match [0..3] */ \
  1165. (0x04000000 << (Nb))
  1166. #define IC_OST0 IC_OST (0) /* OS Timer match 0 */
  1167. #define IC_OST1 IC_OST (1) /* OS Timer match 1 */
  1168. #define IC_OST2 IC_OST (2) /* OS Timer match 2 */
  1169. #define IC_OST3 IC_OST (3) /* OS Timer match 3 */
  1170. #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
  1171. #define IC_RTCAlrm 0x80000000 /* RTC Alarm */
  1172. #define ICLR_IRQ 0 /* Interrupt ReQuest */
  1173. #define ICLR_FIQ 1 /* Fast Interrupt reQuest */
  1174. #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
  1175. /* Mask */
  1176. #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
  1177. /* (ICMR ignored) */
  1178. #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
  1179. /* enable (ICMR used) */
  1180. /*
  1181. * Peripheral Pin Controller (PPC) control registers
  1182. *
  1183. * Registers
  1184. * PPDR Peripheral Pin Controller (PPC) Pin Direction
  1185. * Register (read/write).
  1186. * PPSR Peripheral Pin Controller (PPC) Pin State Register
  1187. * (read/write).
  1188. * PPAR Peripheral Pin Controller (PPC) Pin Assignment
  1189. * Register (read/write).
  1190. * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
  1191. * Direction Register (read/write).
  1192. * PPFR Peripheral Pin Controller (PPC) Pin Flag Register
  1193. * (read).
  1194. */
  1195. #define PPDR __REG(0x90060000) /* PPC Pin Direction Reg. */
  1196. #define PPSR __REG(0x90060004) /* PPC Pin State Reg. */
  1197. #define PPAR __REG(0x90060008) /* PPC Pin Assignment Reg. */
  1198. #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
  1199. #define PPFR __REG(0x90060010) /* PPC Pin Flag Reg. */
  1200. #define PPC_LDD(Nb) /* LCD Data [0..7] */ \
  1201. (0x00000001 << (Nb))
  1202. #define PPC_LDD0 PPC_LDD (0) /* LCD Data [0] */
  1203. #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
  1204. #define PPC_LDD2 PPC_LDD (2) /* LCD Data [2] */
  1205. #define PPC_LDD3 PPC_LDD (3) /* LCD Data [3] */
  1206. #define PPC_LDD4 PPC_LDD (4) /* LCD Data [4] */
  1207. #define PPC_LDD5 PPC_LDD (5) /* LCD Data [5] */
  1208. #define PPC_LDD6 PPC_LDD (6) /* LCD Data [6] */
  1209. #define PPC_LDD7 PPC_LDD (7) /* LCD Data [7] */
  1210. #define PPC_L_PCLK 0x00000100 /* LCD Pixel CLocK */
  1211. #define PPC_L_LCLK 0x00000200 /* LCD Line CLocK */
  1212. #define PPC_L_FCLK 0x00000400 /* LCD Frame CLocK */
  1213. #define PPC_L_BIAS 0x00000800 /* LCD AC BIAS */
  1214. /* ser. port 1: */
  1215. #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
  1216. #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
  1217. /* ser. port 2: */
  1218. #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
  1219. #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
  1220. /* ser. port 3: */
  1221. #define PPC_TXD3 0x00010000 /* UART Transmit Data 3 */
  1222. #define PPC_RXD3 0x00020000 /* UART Receive Data 3 */
  1223. /* ser. port 4: */
  1224. #define PPC_TXD4 0x00040000 /* MCP/SSP Transmit Data 4 */
  1225. #define PPC_RXD4 0x00080000 /* MCP/SSP Receive Data 4 */
  1226. #define PPC_SCLK 0x00100000 /* MCP/SSP Sample CLocK */
  1227. #define PPC_SFRM 0x00200000 /* MCP/SSP Sample FRaMe */
  1228. #define PPDR_In 0 /* Input */
  1229. #define PPDR_Out 1 /* Output */
  1230. /* ser. port 1: */
  1231. #define PPAR_UPR 0x00001000 /* UART Pin Reassignment */
  1232. #define PPAR_UARTTR (PPAR_UPR*0) /* UART on TXD_1 & RXD_1 */
  1233. #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
  1234. /* ser. port 4: */
  1235. #define PPAR_SPR 0x00040000 /* SSP Pin Reassignment */
  1236. #define PPAR_SSPTRSS (PPAR_SPR*0) /* SSP on TXD_C, RXD_C, SCLK_C, */
  1237. /* & SFRM_C */
  1238. #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
  1239. #define PSDR_OutL 0 /* Output Low in sleep mode */
  1240. #define PSDR_Flt 1 /* Floating (input) in sleep mode */
  1241. #define PPFR_LCD 0x00000001 /* LCD controller */
  1242. #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
  1243. #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
  1244. #define PPFR_SP2TX 0x00004000 /* Ser. Port 2 ICP Transmit */
  1245. #define PPFR_SP2RX 0x00008000 /* Ser. Port 2 ICP Receive */
  1246. #define PPFR_SP3TX 0x00010000 /* Ser. Port 3 UART Transmit */
  1247. #define PPFR_SP3RX 0x00020000 /* Ser. Port 3 UART Receive */
  1248. #define PPFR_SP4 0x00040000 /* Ser. Port 4 MCP/SSP */
  1249. #define PPFR_PerEn 0 /* Peripheral Enabled */
  1250. #define PPFR_PPCEn 1 /* PPC Enabled */
  1251. /*
  1252. * Dynamic Random-Access Memory (DRAM) control registers
  1253. *
  1254. * Registers
  1255. * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
  1256. * CoNFiGuration register (read/write).
  1257. * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
  1258. * Column Address Strobe (CAS) shift register 0
  1259. * (read/write).
  1260. * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
  1261. * Column Address Strobe (CAS) shift register 1
  1262. * (read/write).
  1263. * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
  1264. * Column Address Strobe (CAS) shift register 2
  1265. * (read/write).
  1266. *
  1267. * Clocks
  1268. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1269. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1270. * fcas, Tcas Frequency, period of the DRAM CAS shift registers.
  1271. */
  1272. #define MDCNFG __REG(0xA0000000) /* DRAM CoNFiGuration reg. */
  1273. #define MDCAS0 __REG(0xA0000004) /* DRAM CAS shift reg. 0 */
  1274. #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
  1275. #define MDCAS2 __REG(0xA000000c) /* DRAM CAS shift reg. 2 */
  1276. /* SA1100 MDCNFG values */
  1277. #define MDCNFG_DE(Nb) /* DRAM Enable bank [0..3] */ \
  1278. (0x00000001 << (Nb))
  1279. #define MDCNFG_DE0 MDCNFG_DE (0) /* DRAM Enable bank 0 */
  1280. #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
  1281. #define MDCNFG_DE2 MDCNFG_DE (2) /* DRAM Enable bank 2 */
  1282. #define MDCNFG_DE3 MDCNFG_DE (3) /* DRAM Enable bank 3 */
  1283. #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
  1284. #define MDCNFG_RowAdd(Add) /* Row Address count [9..12] */ \
  1285. (((Add) - 9) << FShft (MDCNFG_DRAC))
  1286. #define MDCNFG_CDB2 0x00000040 /* shift reg. Clock Divide By 2 */
  1287. /* (fcas = fcpu/2) */
  1288. #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
  1289. #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
  1290. (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
  1291. #define MDCNFG_CeilPrChrg(Tcpu) /* Ceil. of PrChrg [2..32 Tcpu] */ \
  1292. (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
  1293. #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
  1294. #define MDCNFG_Ref(Tcpu) /* Refresh time [2..32 Tcpu] */ \
  1295. (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
  1296. #define MDCNFG_CeilRef(Tcpu) /* Ceil. of Ref [2..32 Tcpu] */ \
  1297. (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
  1298. #define MDCNFG_TDL Fld (2, 15) /* Time Data Latch [Tcpu] */
  1299. #define MDCNFG_DataLtch(Tcpu) /* Data Latch delay [0..3 Tcpu] */ \
  1300. ((Tcpu) << FShft (MDCNFG_TDL))
  1301. #define MDCNFG_DRI Fld (15, 17) /* min. DRAM Refresh Interval/4 */
  1302. /* [Tmem] */
  1303. #define MDCNFG_RefInt(Tcpu) /* min. Refresh Interval */ \
  1304. /* [0..262136 Tcpu] */ \
  1305. ((Tcpu)/8 << FShft (MDCNFG_DRI))
  1306. /* SA1110 MDCNFG values */
  1307. #define MDCNFG_SA1110_DE0 0x00000001 /* DRAM Enable bank 0 */
  1308. #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
  1309. #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
  1310. #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
  1311. #define MDCNFG_SA1110_DRAC0 Fld(3, 4) /* DRAM row addr bit count */
  1312. /* bank 0/1 */
  1313. #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
  1314. #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
  1315. #define MDCNFG_SA1110_TDL0 Fld(2, 12) /* Data input latch after CAS*/
  1316. /* deassertion 0/1 */
  1317. #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
  1318. #define MDCNFG_SA1110_DE2 0x00010000 /* DRAM Enable bank 0 */
  1319. #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
  1320. #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
  1321. #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
  1322. #define MDCNFG_SA1110_DRAC2 Fld(3, 20) /* DRAM row addr bit count */
  1323. /* bank 0/1 */
  1324. #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
  1325. #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
  1326. #define MDCNFG_SA1110_TDL2 Fld(2, 28) /* Data input latch after CAS*/
  1327. /* deassertion 0/1 */
  1328. #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
  1329. /*
  1330. * Static memory control registers
  1331. *
  1332. * Registers
  1333. * MSC0 Memory system: Static memory Control register 0
  1334. * (read/write).
  1335. * MSC1 Memory system: Static memory Control register 1
  1336. * (read/write).
  1337. *
  1338. * Clocks
  1339. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1340. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1341. */
  1342. #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */
  1343. #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
  1344. #define MSC2 __REG(0xa000002c) /* Static memory Control reg. 2, not contiguous */
  1345. #define MSC_Bnk(Nb) /* static memory Bank [0..3] */ \
  1346. Fld (16, ((Nb) Modulo 2)*16)
  1347. #define MSC0_Bnk0 MSC_Bnk (0) /* static memory Bank 0 */
  1348. #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
  1349. #define MSC1_Bnk2 MSC_Bnk (2) /* static memory Bank 2 */
  1350. #define MSC1_Bnk3 MSC_Bnk (3) /* static memory Bank 3 */
  1351. #define MSC_RT Fld (2, 0) /* ROM/static memory Type */
  1352. #define MSC_NonBrst /* Non-Burst static memory */ \
  1353. (0 << FShft (MSC_RT))
  1354. #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
  1355. (1 << FShft (MSC_RT))
  1356. #define MSC_Brst4 /* Burst-of-4 static memory */ \
  1357. (2 << FShft (MSC_RT))
  1358. #define MSC_Brst8 /* Burst-of-8 static memory */ \
  1359. (3 << FShft (MSC_RT))
  1360. #define MSC_RBW 0x0004 /* ROM/static memory Bus Width */
  1361. #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
  1362. #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
  1363. #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
  1364. /* First access - 1(.5) [Tmem] */
  1365. #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
  1366. /* static memory) [3..65 Tcpu] */ \
  1367. ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
  1368. #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
  1369. ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
  1370. #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
  1371. /* static memory) [2..64 Tcpu] */ \
  1372. ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
  1373. #define MSC_CeilRdAcc(Tcpu) /* Ceil. of RdAcc [2..64 Tcpu] */ \
  1374. ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
  1375. #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
  1376. /* Next access - 1 [Tmem] */
  1377. #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
  1378. /* static memory) [2..64 Tcpu] */ \
  1379. ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
  1380. #define MSC_CeilNxtRdAcc(Tcpu) /* Ceil. of NxtRdAcc [2..64 Tcpu] */ \
  1381. ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
  1382. #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
  1383. /* static memory) [2..64 Tcpu] */ \
  1384. ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
  1385. #define MSC_CeilWrAcc(Tcpu) /* Ceil. of WrAcc [2..64 Tcpu] */ \
  1386. ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
  1387. #define MSC_RRR Fld (3, 13) /* ROM/static memory RecoveRy */
  1388. /* time/2 [Tmem] */
  1389. #define MSC_Rec(Tcpu) /* Recovery time [0..28 Tcpu] */ \
  1390. (((Tcpu)/4) << FShft (MSC_RRR))
  1391. #define MSC_CeilRec(Tcpu) /* Ceil. of Rec [0..28 Tcpu] */ \
  1392. ((((Tcpu) + 3)/4) << FShft (MSC_RRR))
  1393. /*
  1394. * Personal Computer Memory Card International Association (PCMCIA) control
  1395. * register
  1396. *
  1397. * Register
  1398. * MECR Memory system: Expansion memory bus (PCMCIA)
  1399. * Configuration Register (read/write).
  1400. *
  1401. * Clocks
  1402. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1403. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1404. * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK).
  1405. */
  1406. /* Memory system: */
  1407. #define MECR __REG(0xA0000018) /* Expansion memory bus (PCMCIA) Configuration Reg. */
  1408. #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
  1409. Fld (15, (Nb)*16)
  1410. #define MECR_PCMCIA0 MECR_PCMCIA (0) /* PCMCIA 0 */
  1411. #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
  1412. #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
  1413. #define MECR_IOClk(Tcpu) /* I/O Clock [2..64 Tcpu] */ \
  1414. ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
  1415. #define MECR_CeilIOClk(Tcpu) /* Ceil. of IOClk [2..64 Tcpu] */ \
  1416. ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
  1417. #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
  1418. /* [Tmem] */
  1419. #define MECR_AttrClk(Tcpu) /* Attribute Clock [2..64 Tcpu] */ \
  1420. ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
  1421. #define MECR_CeilAttrClk(Tcpu) /* Ceil. of AttrClk [2..64 Tcpu] */ \
  1422. ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
  1423. #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
  1424. #define MECR_MemClk(Tcpu) /* Memory Clock [2..64 Tcpu] */ \
  1425. ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
  1426. #define MECR_CeilMemClk(Tcpu) /* Ceil. of MemClk [2..64 Tcpu] */ \
  1427. ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
  1428. /*
  1429. * On SA1110 only
  1430. */
  1431. #define MDREFR __REG(0xA000001C)
  1432. #define MDREFR_TRASR Fld (4, 0)
  1433. #define MDREFR_DRI Fld (12, 4)
  1434. #define MDREFR_E0PIN (1 << 16)
  1435. #define MDREFR_K0RUN (1 << 17)
  1436. #define MDREFR_K0DB2 (1 << 18)
  1437. #define MDREFR_E1PIN (1 << 20)
  1438. #define MDREFR_K1RUN (1 << 21)
  1439. #define MDREFR_K1DB2 (1 << 22)
  1440. #define MDREFR_K2RUN (1 << 25)
  1441. #define MDREFR_K2DB2 (1 << 26)
  1442. #define MDREFR_EAPD (1 << 28)
  1443. #define MDREFR_KAPD (1 << 29)
  1444. #define MDREFR_SLFRSH (1 << 31)
  1445. /*
  1446. * Direct Memory Access (DMA) control registers
  1447. *
  1448. * Registers
  1449. * DDAR0 Direct Memory Access (DMA) Device Address Register
  1450. * channel 0 (read/write).
  1451. * DCSR0 Direct Memory Access (DMA) Control and Status
  1452. * Register channel 0 (read/write).
  1453. * DBSA0 Direct Memory Access (DMA) Buffer Start address
  1454. * register A channel 0 (read/write).
  1455. * DBTA0 Direct Memory Access (DMA) Buffer Transfer count
  1456. * register A channel 0 (read/write).
  1457. * DBSB0 Direct Memory Access (DMA) Buffer Start address
  1458. * register B channel 0 (read/write).
  1459. * DBTB0 Direct Memory Access (DMA) Buffer Transfer count
  1460. * register B channel 0 (read/write).
  1461. *
  1462. * DDAR1 Direct Memory Access (DMA) Device Address Register
  1463. * channel 1 (read/write).
  1464. * DCSR1 Direct Memory Access (DMA) Control and Status
  1465. * Register channel 1 (read/write).
  1466. * DBSA1 Direct Memory Access (DMA) Buffer Start address
  1467. * register A channel 1 (read/write).
  1468. * DBTA1 Direct Memory Access (DMA) Buffer Transfer count
  1469. * register A channel 1 (read/write).
  1470. * DBSB1 Direct Memory Access (DMA) Buffer Start address
  1471. * register B channel 1 (read/write).
  1472. * DBTB1 Direct Memory Access (DMA) Buffer Transfer count
  1473. * register B channel 1 (read/write).
  1474. *
  1475. * DDAR2 Direct Memory Access (DMA) Device Address Register
  1476. * channel 2 (read/write).
  1477. * DCSR2 Direct Memory Access (DMA) Control and Status
  1478. * Register channel 2 (read/write).
  1479. * DBSA2 Direct Memory Access (DMA) Buffer Start address
  1480. * register A channel 2 (read/write).
  1481. * DBTA2 Direct Memory Access (DMA) Buffer Transfer count
  1482. * register A channel 2 (read/write).
  1483. * DBSB2 Direct Memory Access (DMA) Buffer Start address
  1484. * register B channel 2 (read/write).
  1485. * DBTB2 Direct Memory Access (DMA) Buffer Transfer count
  1486. * register B channel 2 (read/write).
  1487. *
  1488. * DDAR3 Direct Memory Access (DMA) Device Address Register
  1489. * channel 3 (read/write).
  1490. * DCSR3 Direct Memory Access (DMA) Control and Status
  1491. * Register channel 3 (read/write).
  1492. * DBSA3 Direct Memory Access (DMA) Buffer Start address
  1493. * register A channel 3 (read/write).
  1494. * DBTA3 Direct Memory Access (DMA) Buffer Transfer count
  1495. * register A channel 3 (read/write).
  1496. * DBSB3 Direct Memory Access (DMA) Buffer Start address
  1497. * register B channel 3 (read/write).
  1498. * DBTB3 Direct Memory Access (DMA) Buffer Transfer count
  1499. * register B channel 3 (read/write).
  1500. *
  1501. * DDAR4 Direct Memory Access (DMA) Device Address Register
  1502. * channel 4 (read/write).
  1503. * DCSR4 Direct Memory Access (DMA) Control and Status
  1504. * Register channel 4 (read/write).
  1505. * DBSA4 Direct Memory Access (DMA) Buffer Start address
  1506. * register A channel 4 (read/write).
  1507. * DBTA4 Direct Memory Access (DMA) Buffer Transfer count
  1508. * register A channel 4 (read/write).
  1509. * DBSB4 Direct Memory Access (DMA) Buffer Start address
  1510. * register B channel 4 (read/write).
  1511. * DBTB4 Direct Memory Access (DMA) Buffer Transfer count
  1512. * register B channel 4 (read/write).
  1513. *
  1514. * DDAR5 Direct Memory Access (DMA) Device Address Register
  1515. * channel 5 (read/write).
  1516. * DCSR5 Direct Memory Access (DMA) Control and Status
  1517. * Register channel 5 (read/write).
  1518. * DBSA5 Direct Memory Access (DMA) Buffer Start address
  1519. * register A channel 5 (read/write).
  1520. * DBTA5 Direct Memory Access (DMA) Buffer Transfer count
  1521. * register A channel 5 (read/write).
  1522. * DBSB5 Direct Memory Access (DMA) Buffer Start address
  1523. * register B channel 5 (read/write).
  1524. * DBTB5 Direct Memory Access (DMA) Buffer Transfer count
  1525. * register B channel 5 (read/write).
  1526. */
  1527. #define DMASp 0x00000020 /* DMA control reg. Space [byte] */
  1528. #define DDAR(Nb) __REG(0xB0000000 + (Nb)*DMASp) /* DMA Device Address Reg. channel [0..5] */
  1529. #define SetDCSR(Nb) __REG(0xB0000004 + (Nb)*DMASp) /* Set DMA Control & Status Reg. channel [0..5] (write) */
  1530. #define ClrDCSR(Nb) __REG(0xB0000008 + (Nb)*DMASp) /* Clear DMA Control & Status Reg. channel [0..5] (write) */
  1531. #define RdDCSR(Nb) __REG(0xB000000C + (Nb)*DMASp) /* Read DMA Control & Status Reg. channel [0..5] (read) */
  1532. #define DBSA(Nb) __REG(0xB0000010 + (Nb)*DMASp) /* DMA Buffer Start address reg. A channel [0..5] */
  1533. #define DBTA(Nb) __REG(0xB0000014 + (Nb)*DMASp) /* DMA Buffer Transfer count reg. A channel [0..5] */
  1534. #define DBSB(Nb) __REG(0xB0000018 + (Nb)*DMASp) /* DMA Buffer Start address reg. B channel [0..5] */
  1535. #define DBTB(Nb) __REG(0xB000001C + (Nb)*DMASp) /* DMA Buffer Transfer count reg. B channel [0..5] */
  1536. #define DDAR_RW 0x00000001 /* device data Read/Write */
  1537. #define DDAR_DevWr (DDAR_RW*0) /* Device data Write */
  1538. /* (memory -> device) */
  1539. #define DDAR_DevRd (DDAR_RW*1) /* Device data Read */
  1540. /* (device -> memory) */
  1541. #define DDAR_E 0x00000002 /* big/little Endian device */
  1542. #define DDAR_LtlEnd (DDAR_E*0) /* Little Endian device */
  1543. #define DDAR_BigEnd (DDAR_E*1) /* Big Endian device */
  1544. #define DDAR_BS 0x00000004 /* device Burst Size */
  1545. #define DDAR_Brst4 (DDAR_BS*0) /* Burst-of-4 device */
  1546. #define DDAR_Brst8 (DDAR_BS*1) /* Burst-of-8 device */
  1547. #define DDAR_DW 0x00000008 /* device Data Width */
  1548. #define DDAR_8BitDev (DDAR_DW*0) /* 8-Bit Device */
  1549. #define DDAR_16BitDev (DDAR_DW*1) /* 16-Bit Device */
  1550. #define DDAR_DS Fld (4, 4) /* Device Select */
  1551. #define DDAR_Ser0UDCTr /* Ser. port 0 UDC Transmit */ \
  1552. (0x0 << FShft (DDAR_DS))
  1553. #define DDAR_Ser0UDCRc /* Ser. port 0 UDC Receive */ \
  1554. (0x1 << FShft (DDAR_DS))
  1555. #define DDAR_Ser1SDLCTr /* Ser. port 1 SDLC Transmit */ \
  1556. (0x2 << FShft (DDAR_DS))
  1557. #define DDAR_Ser1SDLCRc /* Ser. port 1 SDLC Receive */ \
  1558. (0x3 << FShft (DDAR_DS))
  1559. #define DDAR_Ser1UARTTr /* Ser. port 1 UART Transmit */ \
  1560. (0x4 << FShft (DDAR_DS))
  1561. #define DDAR_Ser1UARTRc /* Ser. port 1 UART Receive */ \
  1562. (0x5 << FShft (DDAR_DS))
  1563. #define DDAR_Ser2ICPTr /* Ser. port 2 ICP Transmit */ \
  1564. (0x6 << FShft (DDAR_DS))
  1565. #define DDAR_Ser2ICPRc /* Ser. port 2 ICP Receive */ \
  1566. (0x7 << FShft (DDAR_DS))
  1567. #define DDAR_Ser3UARTTr /* Ser. port 3 UART Transmit */ \
  1568. (0x8 << FShft (DDAR_DS))
  1569. #define DDAR_Ser3UARTRc /* Ser. port 3 UART Receive */ \
  1570. (0x9 << FShft (DDAR_DS))
  1571. #define DDAR_Ser4MCP0Tr /* Ser. port 4 MCP 0 Transmit */ \
  1572. /* (audio) */ \
  1573. (0xA << FShft (DDAR_DS))
  1574. #define DDAR_Ser4MCP0Rc /* Ser. port 4 MCP 0 Receive */ \
  1575. /* (audio) */ \
  1576. (0xB << FShft (DDAR_DS))
  1577. #define DDAR_Ser4MCP1Tr /* Ser. port 4 MCP 1 Transmit */ \
  1578. /* (telecom) */ \
  1579. (0xC << FShft (DDAR_DS))
  1580. #define DDAR_Ser4MCP1Rc /* Ser. port 4 MCP 1 Receive */ \
  1581. /* (telecom) */ \
  1582. (0xD << FShft (DDAR_DS))
  1583. #define DDAR_Ser4SSPTr /* Ser. port 4 SSP Transmit */ \
  1584. (0xE << FShft (DDAR_DS))
  1585. #define DDAR_Ser4SSPRc /* Ser. port 4 SSP Receive */ \
  1586. (0xF << FShft (DDAR_DS))
  1587. #define DDAR_DA Fld (24, 8) /* Device Address */
  1588. #define DDAR_DevAdd(Add) /* Device Address */ \
  1589. (((Add) & 0xF0000000) | \
  1590. (((Add) & 0X003FFFFC) << (FShft (DDAR_DA) - 2)))
  1591. #define DDAR_Ser0UDCWr /* Ser. port 0 UDC Write */ \
  1592. (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
  1593. DDAR_Ser0UDCTr + DDAR_DevAdd (__PREG(Ser0UDCDR)))
  1594. #define DDAR_Ser0UDCRd /* Ser. port 0 UDC Read */ \
  1595. (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
  1596. DDAR_Ser0UDCRc + DDAR_DevAdd (__PREG(Ser0UDCDR)))
  1597. #define DDAR_Ser1UARTWr /* Ser. port 1 UART Write */ \
  1598. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  1599. DDAR_Ser1UARTTr + DDAR_DevAdd (__PREG(Ser1UTDR)))
  1600. #define DDAR_Ser1UARTRd /* Ser. port 1 UART Read */ \
  1601. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  1602. DDAR_Ser1UARTRc + DDAR_DevAdd (__PREG(Ser1UTDR)))
  1603. #define DDAR_Ser1SDLCWr /* Ser. port 1 SDLC Write */ \
  1604. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  1605. DDAR_Ser1SDLCTr + DDAR_DevAdd (__PREG(Ser1SDDR)))
  1606. #define DDAR_Ser1SDLCRd /* Ser. port 1 SDLC Read */ \
  1607. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  1608. DDAR_Ser1SDLCRc + DDAR_DevAdd (__PREG(Ser1SDDR)))
  1609. #define DDAR_Ser2UARTWr /* Ser. port 2 UART Write */ \
  1610. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  1611. DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2UTDR)))
  1612. #define DDAR_Ser2UARTRd /* Ser. port 2 UART Read */ \
  1613. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  1614. DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2UTDR)))
  1615. #define DDAR_Ser2HSSPWr /* Ser. port 2 HSSP Write */ \
  1616. (DDAR_DevWr + DDAR_Brst8 + DDAR_8BitDev + \
  1617. DDAR_Ser2ICPTr + DDAR_DevAdd (__PREG(Ser2HSDR)))
  1618. #define DDAR_Ser2HSSPRd /* Ser. port 2 HSSP Read */ \
  1619. (DDAR_DevRd + DDAR_Brst8 + DDAR_8BitDev + \
  1620. DDAR_Ser2ICPRc + DDAR_DevAdd (__PREG(Ser2HSDR)))
  1621. #define DDAR_Ser3UARTWr /* Ser. port 3 UART Write */ \
  1622. (DDAR_DevWr + DDAR_Brst4 + DDAR_8BitDev + \
  1623. DDAR_Ser3UARTTr + DDAR_DevAdd (__PREG(Ser3UTDR)))
  1624. #define DDAR_Ser3UARTRd /* Ser. port 3 UART Read */ \
  1625. (DDAR_DevRd + DDAR_Brst4 + DDAR_8BitDev + \
  1626. DDAR_Ser3UARTRc + DDAR_DevAdd (__PREG(Ser3UTDR)))
  1627. #define DDAR_Ser4MCP0Wr /* Ser. port 4 MCP 0 Write (audio) */ \
  1628. (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
  1629. DDAR_Ser4MCP0Tr + DDAR_DevAdd (__PREG(Ser4MCDR0)))
  1630. #define DDAR_Ser4MCP0Rd /* Ser. port 4 MCP 0 Read (audio) */ \
  1631. (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
  1632. DDAR_Ser4MCP0Rc + DDAR_DevAdd (__PREG(Ser4MCDR0)))
  1633. #define DDAR_Ser4MCP1Wr /* Ser. port 4 MCP 1 Write */ \
  1634. /* (telecom) */ \
  1635. (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
  1636. DDAR_Ser4MCP1Tr + DDAR_DevAdd (__PREG(Ser4MCDR1)))
  1637. #define DDAR_Ser4MCP1Rd /* Ser. port 4 MCP 1 Read */ \
  1638. /* (telecom) */ \
  1639. (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
  1640. DDAR_Ser4MCP1Rc + DDAR_DevAdd (__PREG(Ser4MCDR1)))
  1641. #define DDAR_Ser4SSPWr /* Ser. port 4 SSP Write (16 bits) */ \
  1642. (DDAR_DevWr + DDAR_Brst4 + DDAR_16BitDev + \
  1643. DDAR_Ser4SSPTr + DDAR_DevAdd (__PREG(Ser4SSDR)))
  1644. #define DDAR_Ser4SSPRd /* Ser. port 4 SSP Read (16 bits) */ \
  1645. (DDAR_DevRd + DDAR_Brst4 + DDAR_16BitDev + \
  1646. DDAR_Ser4SSPRc + DDAR_DevAdd (__PREG(Ser4SSDR)))
  1647. #define DCSR_RUN 0x00000001 /* DMA RUNing */
  1648. #define DCSR_IE 0x00000002 /* DMA Interrupt Enable */
  1649. #define DCSR_ERROR 0x00000004 /* DMA ERROR */
  1650. #define DCSR_DONEA 0x00000008 /* DONE DMA transfer buffer A */
  1651. #define DCSR_STRTA 0x00000010 /* STaRTed DMA transfer buffer A */
  1652. #define DCSR_DONEB 0x00000020 /* DONE DMA transfer buffer B */
  1653. #define DCSR_STRTB 0x00000040 /* STaRTed DMA transfer buffer B */
  1654. #define DCSR_BIU 0x00000080 /* DMA Buffer In Use */
  1655. #define DCSR_BufA (DCSR_BIU*0) /* DMA Buffer A in use */
  1656. #define DCSR_BufB (DCSR_BIU*1) /* DMA Buffer B in use */
  1657. #define DBT_TC Fld (13, 0) /* Transfer Count */
  1658. #define DBTA_TCA DBT_TC /* Transfer Count buffer A */
  1659. #define DBTB_TCB DBT_TC /* Transfer Count buffer B */
  1660. /*
  1661. * Liquid Crystal Display (LCD) control registers
  1662. *
  1663. * Registers
  1664. * LCCR0 Liquid Crystal Display (LCD) Control Register 0
  1665. * (read/write).
  1666. * [Bits LDM, BAM, and ERM are only implemented in
  1667. * versions 2.0 (rev. = 8) and higher of the StrongARM
  1668. * SA-1100.]
  1669. * LCSR Liquid Crystal Display (LCD) Status Register
  1670. * (read/write).
  1671. * [Bit LDD can be only read in versions 1.0 (rev. = 1)
  1672. * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
  1673. * read and written (cleared) in versions 2.0 (rev. = 8)
  1674. * and higher.]
  1675. * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
  1676. * (DMA) Base Address Register channel 1 (read/write).
  1677. * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
  1678. * (DMA) Current Address Register channel 1 (read).
  1679. * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
  1680. * (DMA) Base Address Register channel 2 (read/write).
  1681. * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
  1682. * (DMA) Current Address Register channel 2 (read).
  1683. * LCCR1 Liquid Crystal Display (LCD) Control Register 1
  1684. * (read/write).
  1685. * [The LCCR1 register can be only written in
  1686. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  1687. * StrongARM SA-1100, it can be written and read in
  1688. * versions 2.0 (rev. = 8) and higher.]
  1689. * LCCR2 Liquid Crystal Display (LCD) Control Register 2
  1690. * (read/write).
  1691. * [The LCCR1 register can be only written in
  1692. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  1693. * StrongARM SA-1100, it can be written and read in
  1694. * versions 2.0 (rev. = 8) and higher.]
  1695. * LCCR3 Liquid Crystal Display (LCD) Control Register 3
  1696. * (read/write).
  1697. * [The LCCR1 register can be only written in
  1698. * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
  1699. * StrongARM SA-1100, it can be written and read in
  1700. * versions 2.0 (rev. = 8) and higher. Bit PCP is only
  1701. * implemented in versions 2.0 (rev. = 8) and higher of
  1702. * the StrongARM SA-1100.]
  1703. *
  1704. * Clocks
  1705. * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
  1706. * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
  1707. * fpix, Tpix Frequency, period of the pixel clock.
  1708. * fln, Tln Frequency, period of the line clock.
  1709. * fac, Tac Frequency, period of the AC bias clock.
  1710. */
  1711. #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
  1712. #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
  1713. /* [byte] */ \
  1714. (16*LCD_PEntrySp)
  1715. #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
  1716. /* [byte] */ \
  1717. (256*LCD_PEntrySp)
  1718. #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
  1719. /* dummy-Palette Space [byte] */ \
  1720. (16*LCD_PEntrySp)
  1721. #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
  1722. #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
  1723. #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
  1724. #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
  1725. #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
  1726. #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
  1727. (0 << FShft (LCD_PBS))
  1728. #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
  1729. (1 << FShft (LCD_PBS))
  1730. #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
  1731. (2 << FShft (LCD_PBS))
  1732. #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
  1733. #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
  1734. #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
  1735. #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
  1736. #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
  1737. #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
  1738. #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
  1739. #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
  1740. #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
  1741. #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
  1742. #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
  1743. #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
  1744. #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
  1745. #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
  1746. #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
  1747. #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
  1748. /* (Alternative) */
  1749. #define LCCR0 __REG(0xB0100000) /* LCD Control Reg. 0 */
  1750. #define LCSR __REG(0xB0100004) /* LCD Status Reg. */
  1751. #define DBAR1 __REG(0xB0100010) /* LCD DMA Base Address Reg. channel 1 */
  1752. #define DCAR1 __REG(0xB0100014) /* LCD DMA Current Address Reg. channel 1 */
  1753. #define DBAR2 __REG(0xB0100018) /* LCD DMA Base Address Reg. channel 2 */
  1754. #define DCAR2 __REG(0xB010001C) /* LCD DMA Current Address Reg. channel 2 */
  1755. #define LCCR1 __REG(0xB0100020) /* LCD Control Reg. 1 */
  1756. #define LCCR2 __REG(0xB0100024) /* LCD Control Reg. 2 */
  1757. #define LCCR3 __REG(0xB0100028) /* LCD Control Reg. 3 */
  1758. #define LCCR0_LEN 0x00000001 /* LCD ENable */
  1759. #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
  1760. #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
  1761. #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
  1762. #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
  1763. /* Select */
  1764. #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
  1765. #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
  1766. #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
  1767. /* interrupt Mask (disable) */
  1768. #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
  1769. /* interrupt Mask (disable) */
  1770. #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
  1771. /* IUU, OOL, OUL, OOU, and OUU) */
  1772. /* interrupt Mask (disable) */
  1773. #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
  1774. #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
  1775. #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
  1776. #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
  1777. #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
  1778. #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
  1779. #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
  1780. /* display mode) */
  1781. #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
  1782. /* display */
  1783. #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
  1784. /* display */
  1785. #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
  1786. /* [Tmem] */
  1787. #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
  1788. /* [0..510 Tcpu] */ \
  1789. ((Tcpu)/2 << FShft (LCCR0_PDD))
  1790. #define LCSR_LDD 0x00000001 /* LCD Disable Done */
  1791. #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
  1792. #define LCSR_BER 0x00000004 /* Bus ERror */
  1793. #define LCSR_ABC 0x00000008 /* AC Bias clock Count */
  1794. #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
  1795. /* panel */
  1796. #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
  1797. /* panel */
  1798. #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
  1799. /* panel */
  1800. #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
  1801. /* panel */
  1802. #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
  1803. /* panel */
  1804. #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
  1805. /* panel */
  1806. #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
  1807. /* panel */
  1808. #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
  1809. /* panel */
  1810. #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
  1811. #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
  1812. (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
  1813. #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
  1814. /* pulse Width - 1 [Tpix] (L_LCLK) */
  1815. #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
  1816. /* pulse Width [1..64 Tpix] */ \
  1817. (((Tpix) - 1) << FShft (LCCR1_HSW))
  1818. #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
  1819. /* count - 1 [Tpix] */
  1820. #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
  1821. /* [1..256 Tpix] */ \
  1822. (((Tpix) - 1) << FShft (LCCR1_ELW))
  1823. #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
  1824. /* Wait count - 1 [Tpix] */
  1825. #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
  1826. /* [1..256 Tpix] */ \
  1827. (((Tpix) - 1) << FShft (LCCR1_BLW))
  1828. #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
  1829. #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
  1830. (((Line) - 1) << FShft (LCCR2_LPP))
  1831. #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
  1832. /* Width - 1 [Tln] (L_FCLK) */
  1833. #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
  1834. /* Width [1..64 Tln] */ \
  1835. (((Tln) - 1) << FShft (LCCR2_VSW))
  1836. #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
  1837. /* count [Tln] */
  1838. #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
  1839. /* [0..255 Tln] */ \
  1840. ((Tln) << FShft (LCCR2_EFW))
  1841. #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
  1842. /* Wait count [Tln] */
  1843. #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
  1844. /* [0..255 Tln] */ \
  1845. ((Tln) << FShft (LCCR2_BFW))
  1846. #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
  1847. /* [1..255] (L_PCLK) */
  1848. /* fpix = fcpu/(2*(PCD + 2)) */
  1849. /* Tpix = 2*(PCD + 2)*Tcpu */
  1850. #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
  1851. (((Div) - 4)/2 << FShft (LCCR3_PCD))
  1852. /* fpix = fcpu/(2*Floor (Div/2)) */
  1853. /* Tpix = 2*Floor (Div/2)*Tcpu */
  1854. #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
  1855. (((Div) - 3)/2 << FShft (LCCR3_PCD))
  1856. /* fpix = fcpu/(2*Ceil (Div/2)) */
  1857. /* Tpix = 2*Ceil (Div/2)*Tcpu */
  1858. #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
  1859. /* [Tln] (L_BIAS) */
  1860. #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
  1861. (((Div) - 2)/2 << FShft (LCCR3_ACB))
  1862. /* fac = fln/(2*Floor (Div/2)) */
  1863. /* Tac = 2*Floor (Div/2)*Tln */
  1864. #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
  1865. (((Div) - 1)/2 << FShft (LCCR3_ACB))
  1866. /* fac = fln/(2*Ceil (Div/2)) */
  1867. /* Tac = 2*Ceil (Div/2)*Tln */
  1868. #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
  1869. /* Interrupt */
  1870. #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
  1871. /* Off */ \
  1872. (0 << FShft (LCCR3_API))
  1873. #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
  1874. /* [1..15] */ \
  1875. ((Trans) << FShft (LCCR3_API))
  1876. #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
  1877. /* Polarity (L_FCLK) */
  1878. #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
  1879. /* active High */
  1880. #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
  1881. /* active Low */
  1882. #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
  1883. /* pulse Polarity (L_LCLK) */
  1884. #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
  1885. /* pulse active High */
  1886. #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
  1887. /* pulse active Low */
  1888. #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
  1889. #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
  1890. #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
  1891. #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
  1892. /* active display mode) */
  1893. #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
  1894. #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
  1895. #ifndef __ASSEMBLY__
  1896. extern unsigned int processor_id;
  1897. #endif
  1898. #define CPU_REVISION (processor_id & 15)
  1899. #define CPU_SA1110_A0 (0)
  1900. #define CPU_SA1110_B0 (4)
  1901. #define CPU_SA1110_B1 (5)
  1902. #define CPU_SA1110_B2 (6)
  1903. #define CPU_SA1110_B4 (8)
  1904. #define CPU_SA1100_ID (0x4401a110)
  1905. #define CPU_SA1100_MASK (0xfffffff0)
  1906. #define CPU_SA1110_ID (0x6901b110)
  1907. #define CPU_SA1110_MASK (0xfffffff0)