regs-mem.h 4.2 KB

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  1. /*
  2. * include/asm-arm/arch-ns9xxx/regs-mem.h
  3. *
  4. * Copyright (C) 2006 by Digi International Inc.
  5. * All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. */
  11. #ifndef __ASM_ARCH_REGSMEM_H
  12. #define __ASM_ARCH_REGSMEM_H
  13. #include <asm/hardware.h>
  14. /* Memory Module */
  15. /* Control register */
  16. #define MEM_CTRL __REG(0xa0700000)
  17. /* Status register */
  18. #define MEM_STAT __REG(0xa0700004)
  19. /* Configuration register */
  20. #define MEM_CONF __REG(0xa0700008)
  21. /* Dynamic Memory Control register */
  22. #define MEM_DMCTRL __REG(0xa0700020)
  23. /* Dynamic Memory Refresh Timer */
  24. #define MEM_DMRT __REG(0xa0700024)
  25. /* Dynamic Memory Read Configuration register */
  26. #define MEM_DMRC __REG(0xa0700028)
  27. /* Dynamic Memory Precharge Command Period (tRP) */
  28. #define MEM_DMPCP __REG(0xa0700030)
  29. /* Dynamic Memory Active to Precharge Command Period (tRAS) */
  30. #define MEM_DMAPCP __REG(0xa0700034)
  31. /* Dynamic Memory Self-Refresh Exit Time (tSREX) */
  32. #define MEM_DMSRET __REG(0xa0700038)
  33. /* Dynamic Memory Last Data Out to Active Time (tAPR) */
  34. #define MEM_DMLDOAT __REG(0xa070003c)
  35. /* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
  36. #define MEM_DMDIACT __REG(0xa0700040)
  37. /* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
  38. #define MEM_DMWRT __REG(0xa0700044)
  39. /* Dynamic Memory Active to Active Command Period (tRC) */
  40. #define MEM_DMAACP __REG(0xa0700048)
  41. /* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
  42. #define MEM_DMARP __REG(0xa070004c)
  43. /* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
  44. #define MEM_DMESRAC __REG(0xa0700050)
  45. /* Dynamic Memory Active Bank A to Active B Time (tRRD) */
  46. #define MEM_DMABAABT __REG(0xa0700054)
  47. /* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
  48. #define MEM_DMLMACT __REG(0xa0700058)
  49. /* Static Memory Extended Wait */
  50. #define MEM_SMEW __REG(0xa0700080)
  51. /* Dynamic Memory Configuration Register x */
  52. #define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3)
  53. /* Dynamic Memory RAS and CAS Delay x */
  54. #define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3)
  55. /* Static Memory Configuration Register x */
  56. #define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
  57. /* Static Memory Configuration Register x: Write protect */
  58. #define MEM_SMC_WSMC __REGBIT(20)
  59. #define MEM_SMC_WSMC_OFF __REGVAL(MEM_SMC_WSMC, 0)
  60. #define MEM_SMC_WSMC_ON __REGVAL(MEM_SMC_WSMC, 1)
  61. /* Static Memory Configuration Register x: Buffer enable */
  62. #define MEM_SMC_BSMC __REGBIT(19)
  63. #define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0)
  64. #define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1)
  65. /* Static Memory Configuration Register x: Extended Wait */
  66. #define MEM_SMC_EW __REGBIT(8)
  67. #define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0)
  68. #define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1)
  69. /* Static Memory Configuration Register x: Byte lane state */
  70. #define MEM_SMC_PB __REGBIT(7)
  71. #define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0)
  72. #define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1)
  73. /* Static Memory Configuration Register x: Chip select polarity */
  74. #define MEM_SMC_PC __REGBIT(6)
  75. #define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0)
  76. #define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1)
  77. /* static memory configuration register x: page mode*/
  78. #define MEM_SMC_PM __REGBIT(3)
  79. #define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0)
  80. #define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1)
  81. /* static memory configuration register x: Memory width */
  82. #define MEM_SMC_MW __REGBITS(1, 0)
  83. #define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0)
  84. #define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1)
  85. #define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2)
  86. /* Static Memory Write Enable Delay x */
  87. #define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3)
  88. /* Static Memory Output Enable Delay x */
  89. #define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3)
  90. /* Static Memory Read Delay x */
  91. #define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3)
  92. /* Static Memory Page Mode Read Delay 0 */
  93. #define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3)
  94. /* Static Memory Write Delay */
  95. #define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3)
  96. /* Static Memory Turn Round Delay x */
  97. #define MEM_SWT(x) __REG2(0xa0700218, (x) << 3)
  98. #endif /* ifndef __ASM_ARCH_REGSMEM_H */