registers.h 9.1 KB

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  1. /* include/asm-arm/arch-lh7a40x/registers.h
  2. *
  3. * Copyright (C) 2004 Coastal Environmental Systems
  4. * Copyright (C) 2004 Logic Product Development
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. */
  11. #include <asm/arch/constants.h>
  12. #ifndef __ASM_ARCH_REGISTERS_H
  13. #define __ASM_ARCH_REGISTERS_H
  14. /* Physical register base addresses */
  15. #define AC97C_PHYS (0x80000000) /* AC97 Controller */
  16. #define MMC_PHYS (0x80000100) /* Multimedia Card Controller */
  17. #define USB_PHYS (0x80000200) /* USB Client */
  18. #define SCI_PHYS (0x80000300) /* Secure Card Interface */
  19. #define CSC_PHYS (0x80000400) /* Clock/State Controller */
  20. #define INTC_PHYS (0x80000500) /* Interrupt Controller */
  21. #define UART1_PHYS (0x80000600) /* UART1 Controller */
  22. #define SIR_PHYS (0x80000600) /* IR Controller, same are UART1 */
  23. #define UART2_PHYS (0x80000700) /* UART2 Controller */
  24. #define UART3_PHYS (0x80000800) /* UART3 Controller */
  25. #define DCDC_PHYS (0x80000900) /* DC to DC Controller */
  26. #define ACI_PHYS (0x80000a00) /* Audio Codec Interface */
  27. #define SSP_PHYS (0x80000b00) /* Synchronous ... */
  28. #define TIMER_PHYS (0x80000c00) /* Timer Controller */
  29. #define RTC_PHYS (0x80000d00) /* Real-time Clock */
  30. #define GPIO_PHYS (0x80000e00) /* General Purpose IO */
  31. #define BMI_PHYS (0x80000f00) /* Battery Monitor Interface */
  32. #define HRTFTC_PHYS (0x80001000) /* High-res TFT Controller (LH7A400) */
  33. #define ALI_PHYS (0x80001000) /* Advanced LCD Interface (LH7A404) */
  34. #define WDT_PHYS (0x80001400) /* Watchdog Timer */
  35. #define SMC_PHYS (0x80002000) /* Static Memory Controller */
  36. #define SDRC_PHYS (0x80002400) /* SDRAM Controller */
  37. #define DMAC_PHYS (0x80002800) /* DMA Controller */
  38. #define CLCDC_PHYS (0x80003000) /* Color LCD Controller */
  39. /* Physical registers of the LH7A404 */
  40. #define ADC_PHYS (0x80001300) /* A/D & Touchscreen Controller */
  41. #define VIC1_PHYS (0x80008000) /* Vectored Interrupt Controller 1 */
  42. #define USBH_PHYS (0x80009000) /* USB OHCI host controller */
  43. #define VIC2_PHYS (0x8000a000) /* Vectored Interrupt Controller 2 */
  44. /*#define KBD_PHYS (0x80000e00) */
  45. /*#define LCDICP_PHYS (0x80001000) */
  46. /* Clock/State Controller register */
  47. #define CSC_PWRSR __REG(CSC_PHYS + 0x00) /* Reset register & ID */
  48. #define CSC_PWRCNT __REG(CSC_PHYS + 0x04) /* Power control */
  49. #define CSC_CLKSET __REG(CSC_PHYS + 0x20) /* Clock speed control */
  50. #define CSC_USBDRESET __REG(CSC_PHYS + 0x4c) /* USB Device resets */
  51. #define CSC_PWRCNT_USBH_EN (1<<28) /* USB Host power enable */
  52. #define CSC_PWRCNT_DMAC_M2M1_EN (1<<27)
  53. #define CSC_PWRCNT_DMAC_M2M0_EN (1<<26)
  54. #define CSC_PWRCNT_DMAC_M2P8_EN (1<<25)
  55. #define CSC_PWRCNT_DMAC_M2P9_EN (1<<24)
  56. #define CSC_PWRCNT_DMAC_M2P6_EN (1<<23)
  57. #define CSC_PWRCNT_DMAC_M2P7_EN (1<<22)
  58. #define CSC_PWRCNT_DMAC_M2P4_EN (1<<21)
  59. #define CSC_PWRCNT_DMAC_M2P5_EN (1<<20)
  60. #define CSC_PWRCNT_DMAC_M2P2_EN (1<<19)
  61. #define CSC_PWRCNT_DMAC_M2P3_EN (1<<18)
  62. #define CSC_PWRCNT_DMAC_M2P0_EN (1<<17)
  63. #define CSC_PWRCNT_DMAC_M2P1_EN (1<<16)
  64. #define CSC_PWRSR_CHIPMAN_SHIFT (24)
  65. #define CSC_PWRSR_CHIPMAN_MASK (0xff)
  66. #define CSC_PWRSR_CHIPID_SHIFT (16)
  67. #define CSC_PWRSR_CHIPID_MASK (0xff)
  68. #define CSC_USBDRESET_APBRESETREG (1<<1)
  69. #define CSC_USBDRESET_IORESETREG (1<<0)
  70. /* Interrupt Controller registers */
  71. #define INTC_INTSR __REG(INTC_PHYS + 0x00) /* Status */
  72. #define INTC_INTRSR __REG(INTC_PHYS + 0x04) /* Raw Status */
  73. #define INTC_INTENS __REG(INTC_PHYS + 0x08) /* Enable Set */
  74. #define INTC_INTENC __REG(INTC_PHYS + 0x0c) /* Enable Clear */
  75. /* Vectored Interrupted Controller registers */
  76. #define VIC1_IRQSTATUS __REG(VIC1_PHYS + 0x00)
  77. #define VIC1_FIQSTATUS __REG(VIC1_PHYS + 0x04)
  78. #define VIC1_RAWINTR __REG(VIC1_PHYS + 0x08)
  79. #define VIC1_INTSEL __REG(VIC1_PHYS + 0x0c)
  80. #define VIC1_INTEN __REG(VIC1_PHYS + 0x10)
  81. #define VIC1_INTENCLR __REG(VIC1_PHYS + 0x14)
  82. #define VIC1_SOFTINT __REG(VIC1_PHYS + 0x18)
  83. #define VIC1_SOFTINTCLR __REG(VIC1_PHYS + 0x1c)
  84. #define VIC1_PROTECT __REG(VIC1_PHYS + 0x20)
  85. #define VIC1_VECTADDR __REG(VIC1_PHYS + 0x30)
  86. #define VIC1_NVADDR __REG(VIC1_PHYS + 0x34)
  87. #define VIC1_VAD0 __REG(VIC1_PHYS + 0x100)
  88. #define VIC1_VECTCNTL0 __REG(VIC1_PHYS + 0x200)
  89. #define VIC2_IRQSTATUS __REG(VIC2_PHYS + 0x00)
  90. #define VIC2_FIQSTATUS __REG(VIC2_PHYS + 0x04)
  91. #define VIC2_RAWINTR __REG(VIC2_PHYS + 0x08)
  92. #define VIC2_INTSEL __REG(VIC2_PHYS + 0x0c)
  93. #define VIC2_INTEN __REG(VIC2_PHYS + 0x10)
  94. #define VIC2_INTENCLR __REG(VIC2_PHYS + 0x14)
  95. #define VIC2_SOFTINT __REG(VIC2_PHYS + 0x18)
  96. #define VIC2_SOFTINTCLR __REG(VIC2_PHYS + 0x1c)
  97. #define VIC2_PROTECT __REG(VIC2_PHYS + 0x20)
  98. #define VIC2_VECTADDR __REG(VIC2_PHYS + 0x30)
  99. #define VIC2_NVADDR __REG(VIC2_PHYS + 0x34)
  100. #define VIC2_VAD0 __REG(VIC2_PHYS + 0x100)
  101. #define VIC2_VECTCNTL0 __REG(VIC2_PHYS + 0x200)
  102. #define VIC_CNTL_ENABLE (0x20)
  103. /* USB Host registers (Open HCI compatible) */
  104. #define USBH_CMDSTATUS __REG(USBH_PHYS + 0x08)
  105. /* GPIO registers */
  106. #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* Interrupt Type 1 (Edge) */
  107. #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* Interrupt Type 2 */
  108. #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIO End-of-Interrupt */
  109. #define GPIO_GPIOINTEN __REG(GPIO_PHYS + 0x58) /* GPIO Interrupt Enable */
  110. #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIO Interrupt Status */
  111. #define GPIO_PINMUX __REG(GPIO_PHYS + 0x2c)
  112. #define GPIO_PADD __REG(GPIO_PHYS + 0x10)
  113. #define GPIO_PAD __REG(GPIO_PHYS + 0x00)
  114. #define GPIO_PCD __REG(GPIO_PHYS + 0x08)
  115. #define GPIO_PCDD __REG(GPIO_PHYS + 0x18)
  116. #define GPIO_PEDD __REG(GPIO_PHYS + 0x24)
  117. #define GPIO_PED __REG(GPIO_PHYS + 0x20)
  118. /* Static Memory Controller registers */
  119. #define SMC_BCR0 __REG(SMC_PHYS + 0x00) /* Bank 0 Configuration */
  120. #define SMC_BCR1 __REG(SMC_PHYS + 0x04) /* Bank 1 Configuration */
  121. #define SMC_BCR2 __REG(SMC_PHYS + 0x08) /* Bank 2 Configuration */
  122. #define SMC_BCR3 __REG(SMC_PHYS + 0x0C) /* Bank 3 Configuration */
  123. #define SMC_BCR6 __REG(SMC_PHYS + 0x18) /* Bank 6 Configuration */
  124. #define SMC_BCR7 __REG(SMC_PHYS + 0x1c) /* Bank 7 Configuration */
  125. #ifdef CONFIG_MACH_KEV7A400
  126. # define CPLD_RD_OPT_DIP_SW __REG16(CPLD_PHYS + 0x00) /* Read Option SW */
  127. # define CPLD_WR_IO_BRD_CTL __REG16(CPLD_PHYS + 0x00) /* Write Control */
  128. # define CPLD_RD_PB_KEYS __REG16(CPLD_PHYS + 0x02) /* Read Btn Keys */
  129. # define CPLD_LATCHED_INTS __REG16(CPLD_PHYS + 0x04) /* Read INTR stat. */
  130. # define CPLD_CL_INT __REG16(CPLD_PHYS + 0x04) /* Clear INTR stat */
  131. # define CPLD_BOOT_MMC_STATUS __REG16(CPLD_PHYS + 0x06) /* R/O */
  132. # define CPLD_RD_KPD_ROW_SENSE __REG16(CPLD_PHYS + 0x08)
  133. # define CPLD_WR_PB_INT_MASK __REG16(CPLD_PHYS + 0x08)
  134. # define CPLD_RD_BRD_DISP_SW __REG16(CPLD_PHYS + 0x0a)
  135. # define CPLD_WR_EXT_INT_MASK __REG16(CPLD_PHYS + 0x0a)
  136. # define CPLD_LCD_PWR_CNTL __REG16(CPLD_PHYS + 0x0c)
  137. # define CPLD_SEVEN_SEG __REG16(CPLD_PHYS + 0x0e) /* 7 seg. LED mask */
  138. #endif
  139. #if defined (CONFIG_MACH_LPD7A400) || defined (CONFIG_MACH_LPD7A404)
  140. # define CPLD_CONTROL __REG16(CPLD02_PHYS)
  141. # define CPLD_SPI_DATA __REG16(CPLD06_PHYS)
  142. # define CPLD_SPI_CONTROL __REG16(CPLD08_PHYS)
  143. # define CPLD_SPI_EEPROM __REG16(CPLD0A_PHYS)
  144. # define CPLD_INTERRUPTS __REG16(CPLD0C_PHYS) /* IRQ mask/status */
  145. # define CPLD_BOOT_MODE __REG16(CPLD0E_PHYS)
  146. # define CPLD_FLASH __REG16(CPLD10_PHYS)
  147. # define CPLD_POWER_MGMT __REG16(CPLD12_PHYS)
  148. # define CPLD_REVISION __REG16(CPLD14_PHYS)
  149. # define CPLD_GPIO_EXT __REG16(CPLD16_PHYS)
  150. # define CPLD_GPIO_DATA __REG16(CPLD18_PHYS)
  151. # define CPLD_GPIO_DIR __REG16(CPLD1A_PHYS)
  152. #endif
  153. /* Timer registers */
  154. #define TIMER_LOAD1 __REG(TIMER_PHYS + 0x00) /* Timer 1 initial value */
  155. #define TIMER_VALUE1 __REG(TIMER_PHYS + 0x04) /* Timer 1 current value */
  156. #define TIMER_CONTROL1 __REG(TIMER_PHYS + 0x08) /* Timer 1 control word */
  157. #define TIMER_EOI1 __REG(TIMER_PHYS + 0x0c) /* Timer 1 interrupt clear */
  158. #define TIMER_LOAD2 __REG(TIMER_PHYS + 0x20) /* Timer 2 initial value */
  159. #define TIMER_VALUE2 __REG(TIMER_PHYS + 0x24) /* Timer 2 current value */
  160. #define TIMER_CONTROL2 __REG(TIMER_PHYS + 0x28) /* Timer 2 control word */
  161. #define TIMER_EOI2 __REG(TIMER_PHYS + 0x2c) /* Timer 2 interrupt clear */
  162. #define TIMER_BUZZCON __REG(TIMER_PHYS + 0x40) /* Buzzer configuration */
  163. #define TIMER_LOAD3 __REG(TIMER_PHYS + 0x80) /* Timer 3 initial value */
  164. #define TIMER_VALUE3 __REG(TIMER_PHYS + 0x84) /* Timer 3 current value */
  165. #define TIMER_CONTROL3 __REG(TIMER_PHYS + 0x88) /* Timer 3 control word */
  166. #define TIMER_EOI3 __REG(TIMER_PHYS + 0x8c) /* Timer 3 interrupt clear */
  167. #define TIMER_C_ENABLE (1<<7)
  168. #define TIMER_C_PERIODIC (1<<6)
  169. #define TIMER_C_FREERUNNING (0)
  170. #define TIMER_C_2KHZ (0x00) /* 1.986 kHz */
  171. #define TIMER_C_508KHZ (0x08)
  172. /* GPIO registers */
  173. #define GPIO_PFDD __REG(GPIO_PHYS + 0x34) /* PF direction */
  174. #define GPIO_INTTYPE1 __REG(GPIO_PHYS + 0x4c) /* IRQ edge or lvl */
  175. #define GPIO_INTTYPE2 __REG(GPIO_PHYS + 0x50) /* IRQ activ hi/lo */
  176. #define GPIO_GPIOFEOI __REG(GPIO_PHYS + 0x54) /* GPIOF end of IRQ */
  177. #define GPIO_GPIOFINTEN __REG(GPIO_PHYS + 0x58) /* GPIOF IRQ enable */
  178. #define GPIO_INTSTATUS __REG(GPIO_PHYS + 0x5c) /* GPIOF IRQ latch */
  179. #define GPIO_RAWINTSTATUS __REG(GPIO_PHYS + 0x60) /* GPIOF IRQ raw */
  180. #endif /* _ASM_ARCH_REGISTERS_H */