ixp2000-regs.h 18 KB

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  1. /*
  2. * include/asm-arm/arch-ixp2000/ixp2000-regs.h
  3. *
  4. * Chipset register definitions for IXP2400/2800 based systems.
  5. *
  6. * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
  7. *
  8. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  9. *
  10. * Copyright (C) 2002 Intel Corp.
  11. * Copyright (C) 2003-2004 MontaVista Software, Inc.
  12. *
  13. * This program is free software; you can redistribute it and/or modify it
  14. * under the terms of the GNU General Public License as published by the
  15. * Free Software Foundation; either version 2 of the License, or (at your
  16. * option) any later version.
  17. */
  18. #ifndef _IXP2000_REGS_H_
  19. #define _IXP2000_REGS_H_
  20. /*
  21. * IXP2000 linux memory map:
  22. *
  23. * virt phys size
  24. * fb000000 db000000 16M PCI CFG1
  25. * fc000000 da000000 16M PCI CFG0
  26. * fd000000 d8000000 16M PCI I/O
  27. * fe[0-7]00000 8M per-platform mappings
  28. * fe900000 80000000 1M SRAM #0 (first MB)
  29. * fea00000 cb400000 1M SCRATCH ring get/put
  30. * feb00000 c8000000 1M MSF
  31. * fec00000 df000000 1M PCI CSRs
  32. * fed00000 de000000 1M PCI CREG
  33. * fee00000 d6000000 1M INTCTL
  34. * fef00000 c0000000 1M CAP
  35. */
  36. /*
  37. * Static I/O regions.
  38. *
  39. * Most of the registers are clumped in 4K regions spread throughout
  40. * the 0xc0000000 -> 0xc0100000 address range, but we just map in
  41. * the whole range using a single 1 MB section instead of small
  42. * 4K pages. This has two advantages for us:
  43. *
  44. * 1) We use only one TLB entry for large number of on-chip I/O devices.
  45. *
  46. * 2) We can easily set the Section attributes to XCB=101 on the IXP2400
  47. * as required per erratum #66. We accomplish this by using a
  48. * new MT_IXP2000_DEVICE memory type with the bits set as required.
  49. *
  50. * CAP stands for CSR Access Proxy.
  51. *
  52. * If you change the virtual address of this mapping, please propagate
  53. * the change to arch/arm/kernel/debug.S, which hardcodes the virtual
  54. * address of the UART located in this region.
  55. */
  56. #define IXP2000_CAP_PHYS_BASE 0xc0000000
  57. #define IXP2000_CAP_VIRT_BASE 0xfef00000
  58. #define IXP2000_CAP_SIZE 0x00100000
  59. /*
  60. * Addresses for specific on-chip peripherals.
  61. */
  62. #define IXP2000_SLOWPORT_CSR_VIRT_BASE 0xfef80000
  63. #define IXP2000_GLOBAL_REG_VIRT_BASE 0xfef04000
  64. #define IXP2000_UART_PHYS_BASE 0xc0030000
  65. #define IXP2000_UART_VIRT_BASE 0xfef30000
  66. #define IXP2000_TIMER_VIRT_BASE 0xfef20000
  67. #define IXP2000_UENGINE_CSR_VIRT_BASE 0xfef18000
  68. #define IXP2000_GPIO_VIRT_BASE 0xfef10000
  69. /*
  70. * Devices outside of the 0xc0000000 -> 0xc0100000 range. The virtual
  71. * addresses of the INTCTL and PCI_CSR mappings are hardcoded in
  72. * entry-macro.S, so if you ever change these please propagate
  73. * the change.
  74. */
  75. #define IXP2000_INTCTL_PHYS_BASE 0xd6000000
  76. #define IXP2000_INTCTL_VIRT_BASE 0xfee00000
  77. #define IXP2000_INTCTL_SIZE 0x00100000
  78. #define IXP2000_PCI_CREG_PHYS_BASE 0xde000000
  79. #define IXP2000_PCI_CREG_VIRT_BASE 0xfed00000
  80. #define IXP2000_PCI_CREG_SIZE 0x00100000
  81. #define IXP2000_PCI_CSR_PHYS_BASE 0xdf000000
  82. #define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
  83. #define IXP2000_PCI_CSR_SIZE 0x00100000
  84. #define IXP2000_MSF_PHYS_BASE 0xc8000000
  85. #define IXP2000_MSF_VIRT_BASE 0xfeb00000
  86. #define IXP2000_MSF_SIZE 0x00100000
  87. #define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
  88. #define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
  89. #define IXP2000_SCRATCH_RING_SIZE 0x00100000
  90. #define IXP2000_SRAM0_PHYS_BASE 0x80000000
  91. #define IXP2000_SRAM0_VIRT_BASE 0xfe900000
  92. #define IXP2000_SRAM0_SIZE 0x00100000
  93. #define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
  94. #define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
  95. #define IXP2000_PCI_IO_SIZE 0x01000000
  96. #define IXP2000_PCI_CFG0_PHYS_BASE 0xda000000
  97. #define IXP2000_PCI_CFG0_VIRT_BASE 0xfc000000
  98. #define IXP2000_PCI_CFG0_SIZE 0x01000000
  99. #define IXP2000_PCI_CFG1_PHYS_BASE 0xdb000000
  100. #define IXP2000_PCI_CFG1_VIRT_BASE 0xfb000000
  101. #define IXP2000_PCI_CFG1_SIZE 0x01000000
  102. /*
  103. * Timers
  104. */
  105. #define IXP2000_TIMER_REG(x) ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
  106. /* Timer control */
  107. #define IXP2000_T1_CTL IXP2000_TIMER_REG(0x00)
  108. #define IXP2000_T2_CTL IXP2000_TIMER_REG(0x04)
  109. #define IXP2000_T3_CTL IXP2000_TIMER_REG(0x08)
  110. #define IXP2000_T4_CTL IXP2000_TIMER_REG(0x0c)
  111. /* Store initial value */
  112. #define IXP2000_T1_CLD IXP2000_TIMER_REG(0x10)
  113. #define IXP2000_T2_CLD IXP2000_TIMER_REG(0x14)
  114. #define IXP2000_T3_CLD IXP2000_TIMER_REG(0x18)
  115. #define IXP2000_T4_CLD IXP2000_TIMER_REG(0x1c)
  116. /* Read current value */
  117. #define IXP2000_T1_CSR IXP2000_TIMER_REG(0x20)
  118. #define IXP2000_T2_CSR IXP2000_TIMER_REG(0x24)
  119. #define IXP2000_T3_CSR IXP2000_TIMER_REG(0x28)
  120. #define IXP2000_T4_CSR IXP2000_TIMER_REG(0x2c)
  121. /* Clear associated timer interrupt */
  122. #define IXP2000_T1_CLR IXP2000_TIMER_REG(0x30)
  123. #define IXP2000_T2_CLR IXP2000_TIMER_REG(0x34)
  124. #define IXP2000_T3_CLR IXP2000_TIMER_REG(0x38)
  125. #define IXP2000_T4_CLR IXP2000_TIMER_REG(0x3c)
  126. /* Timer watchdog enable for T4 */
  127. #define IXP2000_TWDE IXP2000_TIMER_REG(0x40)
  128. #define WDT_ENABLE 0x00000001
  129. #define TIMER_DIVIDER_256 0x00000008
  130. #define TIMER_ENABLE 0x00000080
  131. #define IRQ_MASK_TIMER1 (1 << 4)
  132. /*
  133. * Interrupt controller registers
  134. */
  135. #define IXP2000_INTCTL_REG(x) (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
  136. #define IXP2000_IRQ_STATUS IXP2000_INTCTL_REG(0x08)
  137. #define IXP2000_IRQ_ENABLE IXP2000_INTCTL_REG(0x10)
  138. #define IXP2000_IRQ_ENABLE_SET IXP2000_INTCTL_REG(0x10)
  139. #define IXP2000_IRQ_ENABLE_CLR IXP2000_INTCTL_REG(0x18)
  140. #define IXP2000_FIQ_ENABLE_CLR IXP2000_INTCTL_REG(0x14)
  141. #define IXP2000_IRQ_ERR_STATUS IXP2000_INTCTL_REG(0x24)
  142. #define IXP2000_IRQ_ERR_ENABLE_SET IXP2000_INTCTL_REG(0x2c)
  143. #define IXP2000_FIQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x30)
  144. #define IXP2000_IRQ_ERR_ENABLE_CLR IXP2000_INTCTL_REG(0x34)
  145. #define IXP2000_IRQ_THD_RAW_STATUS_A_0 IXP2000_INTCTL_REG(0x60)
  146. #define IXP2000_IRQ_THD_RAW_STATUS_A_1 IXP2000_INTCTL_REG(0x64)
  147. #define IXP2000_IRQ_THD_RAW_STATUS_A_2 IXP2000_INTCTL_REG(0x68)
  148. #define IXP2000_IRQ_THD_RAW_STATUS_A_3 IXP2000_INTCTL_REG(0x6c)
  149. #define IXP2000_IRQ_THD_RAW_STATUS_B_0 IXP2000_INTCTL_REG(0x80)
  150. #define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84)
  151. #define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88)
  152. #define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c)
  153. #define IXP2000_IRQ_THD_STATUS_A_0 IXP2000_INTCTL_REG(0xe0)
  154. #define IXP2000_IRQ_THD_STATUS_A_1 IXP2000_INTCTL_REG(0xe4)
  155. #define IXP2000_IRQ_THD_STATUS_A_2 IXP2000_INTCTL_REG(0xe8)
  156. #define IXP2000_IRQ_THD_STATUS_A_3 IXP2000_INTCTL_REG(0xec)
  157. #define IXP2000_IRQ_THD_STATUS_B_0 IXP2000_INTCTL_REG(0x100)
  158. #define IXP2000_IRQ_THD_STATUS_B_1 IXP2000_INTCTL_REG(0x104)
  159. #define IXP2000_IRQ_THD_STATUS_B_2 IXP2000_INTCTL_REG(0x108)
  160. #define IXP2000_IRQ_THD_STATUS_B_3 IXP2000_INTCTL_REG(0x10c)
  161. #define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160)
  162. #define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164)
  163. #define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168)
  164. #define IXP2000_IRQ_THD_ENABLE_SET_A_3 IXP2000_INTCTL_REG(0x16c)
  165. #define IXP2000_IRQ_THD_ENABLE_SET_B_0 IXP2000_INTCTL_REG(0x180)
  166. #define IXP2000_IRQ_THD_ENABLE_SET_B_1 IXP2000_INTCTL_REG(0x184)
  167. #define IXP2000_IRQ_THD_ENABLE_SET_B_2 IXP2000_INTCTL_REG(0x188)
  168. #define IXP2000_IRQ_THD_ENABLE_SET_B_3 IXP2000_INTCTL_REG(0x18c)
  169. #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_0 IXP2000_INTCTL_REG(0x1e0)
  170. #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_1 IXP2000_INTCTL_REG(0x1e4)
  171. #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_2 IXP2000_INTCTL_REG(0x1e8)
  172. #define IXP2000_IRQ_THD_ENABLE_CLEAR_A_3 IXP2000_INTCTL_REG(0x1ec)
  173. #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_0 IXP2000_INTCTL_REG(0x200)
  174. #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_1 IXP2000_INTCTL_REG(0x204)
  175. #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_2 IXP2000_INTCTL_REG(0x208)
  176. #define IXP2000_IRQ_THD_ENABLE_CLEAR_B_3 IXP2000_INTCTL_REG(0x20c)
  177. /*
  178. * Mask of valid IRQs in the 32-bit IRQ register. We use
  179. * this to mark certain IRQs as being invalid.
  180. */
  181. #define IXP2000_VALID_IRQ_MASK 0x0f0fffff
  182. /*
  183. * PCI config register access from core
  184. */
  185. #define IXP2000_PCI_CREG(x) (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
  186. #define IXP2000_PCI_CMDSTAT IXP2000_PCI_CREG(0x04)
  187. #define IXP2000_PCI_CSR_BAR IXP2000_PCI_CREG(0x10)
  188. #define IXP2000_PCI_SRAM_BAR IXP2000_PCI_CREG(0x14)
  189. #define IXP2000_PCI_SDRAM_BAR IXP2000_PCI_CREG(0x18)
  190. /*
  191. * PCI CSRs
  192. */
  193. #define IXP2000_PCI_CSR(x) (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
  194. /*
  195. * PCI outbound interrupts
  196. */
  197. #define IXP2000_PCI_OUT_INT_STATUS IXP2000_PCI_CSR(0x30)
  198. #define IXP2000_PCI_OUT_INT_MASK IXP2000_PCI_CSR(0x34)
  199. /*
  200. * PCI communications
  201. */
  202. #define IXP2000_PCI_MAILBOX0 IXP2000_PCI_CSR(0x50)
  203. #define IXP2000_PCI_MAILBOX1 IXP2000_PCI_CSR(0x54)
  204. #define IXP2000_PCI_MAILBOX2 IXP2000_PCI_CSR(0x58)
  205. #define IXP2000_PCI_MAILBOX3 IXP2000_PCI_CSR(0x5C)
  206. #define IXP2000_XSCALE_DOORBELL IXP2000_PCI_CSR(0x60)
  207. #define IXP2000_XSCALE_DOORBELL_SETUP IXP2000_PCI_CSR(0x64)
  208. #define IXP2000_PCI_DOORBELL IXP2000_PCI_CSR(0x70)
  209. #define IXP2000_PCI_DOORBELL_SETUP IXP2000_PCI_CSR(0x74)
  210. /*
  211. * DMA engines
  212. */
  213. #define IXP2000_PCI_CH1_BYTE_CNT IXP2000_PCI_CSR(0x80)
  214. #define IXP2000_PCI_CH1_ADDR IXP2000_PCI_CSR(0x84)
  215. #define IXP2000_PCI_CH1_DRAM_ADDR IXP2000_PCI_CSR(0x88)
  216. #define IXP2000_PCI_CH1_DESC_PTR IXP2000_PCI_CSR(0x8C)
  217. #define IXP2000_PCI_CH1_CNTRL IXP2000_PCI_CSR(0x90)
  218. #define IXP2000_PCI_CH1_ME_PARAM IXP2000_PCI_CSR(0x94)
  219. #define IXP2000_PCI_CH2_BYTE_CNT IXP2000_PCI_CSR(0xA0)
  220. #define IXP2000_PCI_CH2_ADDR IXP2000_PCI_CSR(0xA4)
  221. #define IXP2000_PCI_CH2_DRAM_ADDR IXP2000_PCI_CSR(0xA8)
  222. #define IXP2000_PCI_CH2_DESC_PTR IXP2000_PCI_CSR(0xAC)
  223. #define IXP2000_PCI_CH2_CNTRL IXP2000_PCI_CSR(0xB0)
  224. #define IXP2000_PCI_CH2_ME_PARAM IXP2000_PCI_CSR(0xB4)
  225. #define IXP2000_PCI_CH3_BYTE_CNT IXP2000_PCI_CSR(0xC0)
  226. #define IXP2000_PCI_CH3_ADDR IXP2000_PCI_CSR(0xC4)
  227. #define IXP2000_PCI_CH3_DRAM_ADDR IXP2000_PCI_CSR(0xC8)
  228. #define IXP2000_PCI_CH3_DESC_PTR IXP2000_PCI_CSR(0xCC)
  229. #define IXP2000_PCI_CH3_CNTRL IXP2000_PCI_CSR(0xD0)
  230. #define IXP2000_PCI_CH3_ME_PARAM IXP2000_PCI_CSR(0xD4)
  231. #define IXP2000_DMA_INF_MODE IXP2000_PCI_CSR(0xE0)
  232. /*
  233. * Size masks for BARs
  234. */
  235. #define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
  236. #define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
  237. /*
  238. * Control and uEngine related
  239. */
  240. #define IXP2000_PCI_CONTROL IXP2000_PCI_CSR(0x13C)
  241. #define IXP2000_PCI_ADDR_EXT IXP2000_PCI_CSR(0x140)
  242. #define IXP2000_PCI_ME_PUSH_STATUS IXP2000_PCI_CSR(0x148)
  243. #define IXP2000_PCI_ME_PUSH_EN IXP2000_PCI_CSR(0x14C)
  244. #define IXP2000_PCI_ERR_STATUS IXP2000_PCI_CSR(0x150)
  245. #define IXP2000_PCI_ERR_ENABLE IXP2000_PCI_CSR(0x154)
  246. /*
  247. * Inbound PCI interrupt control
  248. */
  249. #define IXP2000_PCI_XSCALE_INT_STATUS IXP2000_PCI_CSR(0x158)
  250. #define IXP2000_PCI_XSCALE_INT_ENABLE IXP2000_PCI_CSR(0x15C)
  251. #define IXP2000_PCICNTL_PNR (1<<17) /* PCI not Reset bit of PCI_CONTROL */
  252. #define IXP2000_PCICNTL_PCF (1<<28) /* PCI Central function bit */
  253. #define IXP2000_XSCALE_INT (1<<1) /* Interrupt from XScale to PCI */
  254. /* These are from the IRQ register in the PCI ISR register */
  255. #define PCI_CONTROL_BE_DEO (1 << 22) /* Big Endian Data Enable Out */
  256. #define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
  257. #define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
  258. #define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
  259. #define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
  260. #define IXP2000_PCI_RST_REL (1 << 2)
  261. #define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
  262. #define CFG_PCI_BOOT_HOST (1 << 2)
  263. #define CFG_BOOT_PROM (1 << 1)
  264. /*
  265. * SlowPort CSRs
  266. *
  267. * The slowport is used to access things like flash, SONET framer control
  268. * ports, slave microprocessors, CPLDs, and others of chip memory mapped
  269. * peripherals.
  270. */
  271. #define SLOWPORT_CSR(x) (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
  272. #define IXP2000_SLOWPORT_CCR SLOWPORT_CSR(0x00)
  273. #define IXP2000_SLOWPORT_WTC1 SLOWPORT_CSR(0x04)
  274. #define IXP2000_SLOWPORT_WTC2 SLOWPORT_CSR(0x08)
  275. #define IXP2000_SLOWPORT_RTC1 SLOWPORT_CSR(0x0c)
  276. #define IXP2000_SLOWPORT_RTC2 SLOWPORT_CSR(0x10)
  277. #define IXP2000_SLOWPORT_FSR SLOWPORT_CSR(0x14)
  278. #define IXP2000_SLOWPORT_PCR SLOWPORT_CSR(0x18)
  279. #define IXP2000_SLOWPORT_ADC SLOWPORT_CSR(0x1C)
  280. #define IXP2000_SLOWPORT_FAC SLOWPORT_CSR(0x20)
  281. #define IXP2000_SLOWPORT_FRM SLOWPORT_CSR(0x24)
  282. #define IXP2000_SLOWPORT_FIN SLOWPORT_CSR(0x28)
  283. /*
  284. * CCR values.
  285. * The CCR configures the clock division for the slowport interface.
  286. */
  287. #define SLOWPORT_CCR_DIV_1 0x00
  288. #define SLOWPORT_CCR_DIV_2 0x01
  289. #define SLOWPORT_CCR_DIV_4 0x02
  290. #define SLOWPORT_CCR_DIV_6 0x03
  291. #define SLOWPORT_CCR_DIV_8 0x04
  292. #define SLOWPORT_CCR_DIV_10 0x05
  293. #define SLOWPORT_CCR_DIV_12 0x06
  294. #define SLOWPORT_CCR_DIV_14 0x07
  295. #define SLOWPORT_CCR_DIV_16 0x08
  296. #define SLOWPORT_CCR_DIV_18 0x09
  297. #define SLOWPORT_CCR_DIV_20 0x0a
  298. #define SLOWPORT_CCR_DIV_22 0x0b
  299. #define SLOWPORT_CCR_DIV_24 0x0c
  300. #define SLOWPORT_CCR_DIV_26 0x0d
  301. #define SLOWPORT_CCR_DIV_28 0x0e
  302. #define SLOWPORT_CCR_DIV_30 0x0f
  303. /*
  304. * PCR values. PCR configure the mode of the interface.
  305. */
  306. #define SLOWPORT_MODE_FLASH 0x00
  307. #define SLOWPORT_MODE_LUCENT 0x01
  308. #define SLOWPORT_MODE_PMC_SIERRA 0x02
  309. #define SLOWPORT_MODE_INTEL_UP 0x03
  310. #define SLOWPORT_MODE_MOTOROLA_UP 0x04
  311. /*
  312. * ADC values. Defines data and address bus widths.
  313. */
  314. #define SLOWPORT_ADDR_WIDTH_8 0x00
  315. #define SLOWPORT_ADDR_WIDTH_16 0x01
  316. #define SLOWPORT_ADDR_WIDTH_24 0x02
  317. #define SLOWPORT_ADDR_WIDTH_32 0x03
  318. #define SLOWPORT_DATA_WIDTH_8 0x00
  319. #define SLOWPORT_DATA_WIDTH_16 0x10
  320. #define SLOWPORT_DATA_WIDTH_24 0x20
  321. #define SLOWPORT_DATA_WIDTH_32 0x30
  322. /*
  323. * Masks and shifts for various fields in the WTC and RTC registers.
  324. */
  325. #define SLOWPORT_WRTC_MASK_HD 0x0003
  326. #define SLOWPORT_WRTC_MASK_PW 0x003c
  327. #define SLOWPORT_WRTC_MASK_SU 0x03c0
  328. #define SLOWPORT_WRTC_SHIFT_HD 0x00
  329. #define SLOWPORT_WRTC_SHIFT_SU 0x02
  330. #define SLOWPORT_WRTC_SHFIT_PW 0x06
  331. /*
  332. * GPIO registers & GPIO interface.
  333. */
  334. #define IXP2000_GPIO_REG(x) ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
  335. #define IXP2000_GPIO_PLR IXP2000_GPIO_REG(0x00)
  336. #define IXP2000_GPIO_PDPR IXP2000_GPIO_REG(0x04)
  337. #define IXP2000_GPIO_PDSR IXP2000_GPIO_REG(0x08)
  338. #define IXP2000_GPIO_PDCR IXP2000_GPIO_REG(0x0c)
  339. #define IXP2000_GPIO_POPR IXP2000_GPIO_REG(0x10)
  340. #define IXP2000_GPIO_POSR IXP2000_GPIO_REG(0x14)
  341. #define IXP2000_GPIO_POCR IXP2000_GPIO_REG(0x18)
  342. #define IXP2000_GPIO_REDR IXP2000_GPIO_REG(0x1c)
  343. #define IXP2000_GPIO_FEDR IXP2000_GPIO_REG(0x20)
  344. #define IXP2000_GPIO_EDSR IXP2000_GPIO_REG(0x24)
  345. #define IXP2000_GPIO_LSHR IXP2000_GPIO_REG(0x28)
  346. #define IXP2000_GPIO_LSLR IXP2000_GPIO_REG(0x2c)
  347. #define IXP2000_GPIO_LDSR IXP2000_GPIO_REG(0x30)
  348. #define IXP2000_GPIO_INER IXP2000_GPIO_REG(0x34)
  349. #define IXP2000_GPIO_INSR IXP2000_GPIO_REG(0x38)
  350. #define IXP2000_GPIO_INCR IXP2000_GPIO_REG(0x3c)
  351. #define IXP2000_GPIO_INST IXP2000_GPIO_REG(0x40)
  352. /*
  353. * "Global" registers...whatever that's supposed to mean.
  354. */
  355. #define GLOBAL_REG_BASE (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
  356. #define GLOBAL_REG(x) (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
  357. #define IXP2000_MAJ_PROD_TYPE_MASK 0x001F0000
  358. #define IXP2000_MAJ_PROD_TYPE_IXP2000 0x00000000
  359. #define IXP2000_MIN_PROD_TYPE_MASK 0x0000FF00
  360. #define IXP2000_MIN_PROD_TYPE_IXP2400 0x00000200
  361. #define IXP2000_MIN_PROD_TYPE_IXP2850 0x00000100
  362. #define IXP2000_MIN_PROD_TYPE_IXP2800 0x00000000
  363. #define IXP2000_MAJ_REV_MASK 0x000000F0
  364. #define IXP2000_MIN_REV_MASK 0x0000000F
  365. #define IXP2000_PROD_ID_MASK 0xFFFFFFFF
  366. #define IXP2000_PRODUCT_ID GLOBAL_REG(0x00)
  367. #define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
  368. #define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
  369. #define IXP2000_RESET0 GLOBAL_REG(0x0c)
  370. #define IXP2000_RESET1 GLOBAL_REG(0x10)
  371. #define IXP2000_CCR GLOBAL_REG(0x14)
  372. #define IXP2000_STRAP_OPTIONS GLOBAL_REG(0x18)
  373. #define RSTALL (1 << 16)
  374. #define WDT_RESET_ENABLE 0x01000000
  375. /*
  376. * MSF registers. The IXP2400 and IXP2800 have somewhat different MSF
  377. * units, but the registers that differ between the two don't overlap,
  378. * so we can have one register list for both.
  379. */
  380. #define IXP2000_MSF_REG(x) ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
  381. #define IXP2000_MSF_RX_CONTROL IXP2000_MSF_REG(0x0000)
  382. #define IXP2000_MSF_TX_CONTROL IXP2000_MSF_REG(0x0004)
  383. #define IXP2000_MSF_INTERRUPT_STATUS IXP2000_MSF_REG(0x0008)
  384. #define IXP2000_MSF_INTERRUPT_ENABLE IXP2000_MSF_REG(0x000c)
  385. #define IXP2000_MSF_CSIX_TYPE_MAP IXP2000_MSF_REG(0x0010)
  386. #define IXP2000_MSF_FC_EGRESS_STATUS IXP2000_MSF_REG(0x0014)
  387. #define IXP2000_MSF_FC_INGRESS_STATUS IXP2000_MSF_REG(0x0018)
  388. #define IXP2000_MSF_HWM_CONTROL IXP2000_MSF_REG(0x0024)
  389. #define IXP2000_MSF_FC_STATUS_OVERRIDE IXP2000_MSF_REG(0x0028)
  390. #define IXP2000_MSF_CLOCK_CONTROL IXP2000_MSF_REG(0x002c)
  391. #define IXP2000_MSF_RX_PORT_MAP IXP2000_MSF_REG(0x0040)
  392. #define IXP2000_MSF_RBUF_ELEMENT_DONE IXP2000_MSF_REG(0x0044)
  393. #define IXP2000_MSF_RX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0048)
  394. #define IXP2000_MSF_RX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0048)
  395. #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0 IXP2000_MSF_REG(0x0050)
  396. #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1 IXP2000_MSF_REG(0x0054)
  397. #define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2 IXP2000_MSF_REG(0x0058)
  398. #define IXP2000_MSF_TX_SEQUENCE_0 IXP2000_MSF_REG(0x0060)
  399. #define IXP2000_MSF_TX_SEQUENCE_1 IXP2000_MSF_REG(0x0064)
  400. #define IXP2000_MSF_TX_SEQUENCE_2 IXP2000_MSF_REG(0x0068)
  401. #define IXP2000_MSF_TX_MPHY_POLL_LIMIT IXP2000_MSF_REG(0x0070)
  402. #define IXP2000_MSF_TX_CALENDAR_LENGTH IXP2000_MSF_REG(0x0070)
  403. #define IXP2000_MSF_RX_UP_CONTROL_0 IXP2000_MSF_REG(0x0080)
  404. #define IXP2000_MSF_RX_UP_CONTROL_1 IXP2000_MSF_REG(0x0084)
  405. #define IXP2000_MSF_RX_UP_CONTROL_2 IXP2000_MSF_REG(0x0088)
  406. #define IXP2000_MSF_RX_UP_CONTROL_3 IXP2000_MSF_REG(0x008c)
  407. #define IXP2000_MSF_TX_UP_CONTROL_0 IXP2000_MSF_REG(0x0090)
  408. #define IXP2000_MSF_TX_UP_CONTROL_1 IXP2000_MSF_REG(0x0094)
  409. #define IXP2000_MSF_TX_UP_CONTROL_2 IXP2000_MSF_REG(0x0098)
  410. #define IXP2000_MSF_TX_UP_CONTROL_3 IXP2000_MSF_REG(0x009c)
  411. #define IXP2000_MSF_TRAIN_DATA IXP2000_MSF_REG(0x00a0)
  412. #define IXP2000_MSF_TRAIN_CALENDAR IXP2000_MSF_REG(0x00a4)
  413. #define IXP2000_MSF_TRAIN_FLOW_CONTROL IXP2000_MSF_REG(0x00a8)
  414. #define IXP2000_MSF_TX_CALENDAR_0 IXP2000_MSF_REG(0x1000)
  415. #define IXP2000_MSF_RX_PORT_CALENDAR_STATUS IXP2000_MSF_REG(0x1400)
  416. #endif /* _IXP2000_H_ */