io.h 3.5 KB

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  1. /*
  2. * linux/include/asm-arm/arch-ixp2000/io.h
  3. *
  4. * Original Author: Naeem M Afzal <naeem.m.afzal@intel.com>
  5. * Maintainer: Deepak Saxena <dsaxena@plexity.net>
  6. *
  7. * Copyright (C) 2002 Intel Corp.
  8. * Copyrgiht (C) 2003-2004 MontaVista Software, Inc.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #ifndef __ASM_ARM_ARCH_IO_H
  15. #define __ASM_ARM_ARCH_IO_H
  16. #include <asm/hardware.h>
  17. #define IO_SPACE_LIMIT 0xffffffff
  18. #define __mem_pci(a) (a)
  19. /*
  20. * The A? revisions of the IXP2000s assert byte lanes for PCI I/O
  21. * transactions the other way round (MEM transactions don't have this
  22. * issue), so if we want to support those models, we need to override
  23. * the standard I/O functions.
  24. *
  25. * B0 and later have a bit that can be set to 1 to get the proper
  26. * behavior for I/O transactions, which then allows us to use the
  27. * standard I/O functions. This is what we do if the user does not
  28. * explicitly ask for support for pre-B0.
  29. */
  30. #ifdef CONFIG_IXP2000_SUPPORT_BROKEN_PCI_IO
  31. #define ___io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
  32. #define alignb(addr) (void __iomem *)((unsigned long)(addr) ^ 3)
  33. #define alignw(addr) (void __iomem *)((unsigned long)(addr) ^ 2)
  34. #define outb(v,p) __raw_writeb((v),alignb(___io(p)))
  35. #define outw(v,p) __raw_writew((v),alignw(___io(p)))
  36. #define outl(v,p) __raw_writel((v),___io(p))
  37. #define inb(p) ({ unsigned int __v = __raw_readb(alignb(___io(p))); __v; })
  38. #define inw(p) \
  39. ({ unsigned int __v = (__raw_readw(alignw(___io(p)))); __v; })
  40. #define inl(p) \
  41. ({ unsigned int __v = (__raw_readl(___io(p))); __v; })
  42. #define outsb(p,d,l) __raw_writesb(alignb(___io(p)),d,l)
  43. #define outsw(p,d,l) __raw_writesw(alignw(___io(p)),d,l)
  44. #define outsl(p,d,l) __raw_writesl(___io(p),d,l)
  45. #define insb(p,d,l) __raw_readsb(alignb(___io(p)),d,l)
  46. #define insw(p,d,l) __raw_readsw(alignw(___io(p)),d,l)
  47. #define insl(p,d,l) __raw_readsl(___io(p),d,l)
  48. #define __is_io_address(p) ((((unsigned long)(p)) & ~(IXP2000_PCI_IO_SIZE - 1)) == IXP2000_PCI_IO_VIRT_BASE)
  49. #define ioread8(p) \
  50. ({ \
  51. unsigned int __v; \
  52. \
  53. if (__is_io_address(p)) { \
  54. __v = __raw_readb(alignb(p)); \
  55. } else { \
  56. __v = __raw_readb(p); \
  57. } \
  58. \
  59. __v; \
  60. }) \
  61. #define ioread16(p) \
  62. ({ \
  63. unsigned int __v; \
  64. \
  65. if (__is_io_address(p)) { \
  66. __v = __raw_readw(alignw(p)); \
  67. } else { \
  68. __v = le16_to_cpu(__raw_readw(p)); \
  69. } \
  70. \
  71. __v; \
  72. })
  73. #define ioread32(p) \
  74. ({ \
  75. unsigned int __v; \
  76. \
  77. if (__is_io_address(p)) { \
  78. __v = __raw_readl(p); \
  79. } else { \
  80. __v = le32_to_cpu(__raw_readl(p)); \
  81. } \
  82. \
  83. __v; \
  84. })
  85. #define iowrite8(v,p) \
  86. ({ \
  87. if (__is_io_address(p)) { \
  88. __raw_writeb((v), alignb(p)); \
  89. } else { \
  90. __raw_writeb((v), p); \
  91. } \
  92. })
  93. #define iowrite16(v,p) \
  94. ({ \
  95. if (__is_io_address(p)) { \
  96. __raw_writew((v), alignw(p)); \
  97. } else { \
  98. __raw_writew(cpu_to_le16(v), p); \
  99. } \
  100. })
  101. #define iowrite32(v,p) \
  102. ({ \
  103. if (__is_io_address(p)) { \
  104. __raw_writel((v), p); \
  105. } else { \
  106. __raw_writel(cpu_to_le32(v), p); \
  107. } \
  108. })
  109. #define ioport_map(port, nr) ___io(port)
  110. #define ioport_unmap(addr)
  111. #else
  112. #define __io(p) ((void __iomem *)((p)+IXP2000_PCI_IO_VIRT_BASE))
  113. #endif
  114. #endif