imx-regs.h 28 KB

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  1. #ifndef _IMX_REGS_H
  2. #define _IMX_REGS_H
  3. /* ------------------------------------------------------------------------
  4. * Motorola IMX system registers
  5. * ------------------------------------------------------------------------
  6. *
  7. */
  8. /*
  9. * Register BASEs, based on OFFSETs
  10. *
  11. */
  12. #define IMX_AIPI1_BASE (0x00000 + IMX_IO_BASE)
  13. #define IMX_WDT_BASE (0x01000 + IMX_IO_BASE)
  14. #define IMX_TIM1_BASE (0x02000 + IMX_IO_BASE)
  15. #define IMX_TIM2_BASE (0x03000 + IMX_IO_BASE)
  16. #define IMX_RTC_BASE (0x04000 + IMX_IO_BASE)
  17. #define IMX_LCDC_BASE (0x05000 + IMX_IO_BASE)
  18. #define IMX_UART1_BASE (0x06000 + IMX_IO_BASE)
  19. #define IMX_UART2_BASE (0x07000 + IMX_IO_BASE)
  20. #define IMX_PWM_BASE (0x08000 + IMX_IO_BASE)
  21. #define IMX_DMAC_BASE (0x09000 + IMX_IO_BASE)
  22. #define IMX_AIPI2_BASE (0x10000 + IMX_IO_BASE)
  23. #define IMX_SIM_BASE (0x11000 + IMX_IO_BASE)
  24. #define IMX_USBD_BASE (0x12000 + IMX_IO_BASE)
  25. #define IMX_SPI1_BASE (0x13000 + IMX_IO_BASE)
  26. #define IMX_MMC_BASE (0x14000 + IMX_IO_BASE)
  27. #define IMX_ASP_BASE (0x15000 + IMX_IO_BASE)
  28. #define IMX_BTA_BASE (0x16000 + IMX_IO_BASE)
  29. #define IMX_I2C_BASE (0x17000 + IMX_IO_BASE)
  30. #define IMX_SSI_BASE (0x18000 + IMX_IO_BASE)
  31. #define IMX_SPI2_BASE (0x19000 + IMX_IO_BASE)
  32. #define IMX_MSHC_BASE (0x1A000 + IMX_IO_BASE)
  33. #define IMX_PLL_BASE (0x1B000 + IMX_IO_BASE)
  34. #define IMX_GPIO_BASE (0x1C000 + IMX_IO_BASE)
  35. #define IMX_EIM_BASE (0x20000 + IMX_IO_BASE)
  36. #define IMX_SDRAMC_BASE (0x21000 + IMX_IO_BASE)
  37. #define IMX_MMA_BASE (0x22000 + IMX_IO_BASE)
  38. #define IMX_AITC_BASE (0x23000 + IMX_IO_BASE)
  39. #define IMX_CSI_BASE (0x24000 + IMX_IO_BASE)
  40. /* PLL registers */
  41. #define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
  42. #define CSCR_SPLL_RESTART (1<<22)
  43. #define CSCR_MPLL_RESTART (1<<21)
  44. #define CSCR_SYSTEM_SEL (1<<16)
  45. #define CSCR_BCLK_DIV (0xf<<10)
  46. #define CSCR_MPU_PRESC (1<<15)
  47. #define CSCR_SPEN (1<<1)
  48. #define CSCR_MPEN (1<<0)
  49. #define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
  50. #define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
  51. #define SPCTL0 __REG(IMX_PLL_BASE + 0xc) /* System PLL Control Register 0 */
  52. #define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
  53. #define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
  54. /*
  55. * GPIO Module and I/O Multiplexer
  56. * x = 0..3 for reg_A, reg_B, reg_C, reg_D
  57. */
  58. #define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 3) << 8)
  59. #define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 3) << 8)
  60. #define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 3) << 8)
  61. #define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 3) << 8)
  62. #define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 3) << 8)
  63. #define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 3) << 8)
  64. #define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 3) << 8)
  65. #define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 3) << 8)
  66. #define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 3) << 8)
  67. #define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 3) << 8)
  68. #define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 3) << 8)
  69. #define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 3) << 8)
  70. #define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 3) << 8)
  71. #define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 3) << 8)
  72. #define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 3) << 8)
  73. #define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 3) << 8)
  74. #define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 3) << 8)
  75. #define GPIO_PIN_MASK 0x1f
  76. #define GPIO_PORT_MASK (0x3 << 5)
  77. #define GPIO_PORT_SHIFT 5
  78. #define GPIO_PORTA (0<<5)
  79. #define GPIO_PORTB (1<<5)
  80. #define GPIO_PORTC (2<<5)
  81. #define GPIO_PORTD (3<<5)
  82. #define GPIO_OUT (1<<7)
  83. #define GPIO_IN (0<<7)
  84. #define GPIO_PUEN (1<<8)
  85. #define GPIO_PF (0<<9)
  86. #define GPIO_AF (1<<9)
  87. #define GPIO_OCR_SHIFT 10
  88. #define GPIO_OCR_MASK (3<<10)
  89. #define GPIO_AIN (0<<10)
  90. #define GPIO_BIN (1<<10)
  91. #define GPIO_CIN (2<<10)
  92. #define GPIO_DR (3<<10)
  93. #define GPIO_AOUT_SHIFT 12
  94. #define GPIO_AOUT_MASK (3<<12)
  95. #define GPIO_AOUT (0<<12)
  96. #define GPIO_AOUT_ISR (1<<12)
  97. #define GPIO_AOUT_0 (2<<12)
  98. #define GPIO_AOUT_1 (3<<12)
  99. #define GPIO_BOUT_SHIFT 14
  100. #define GPIO_BOUT_MASK (3<<14)
  101. #define GPIO_BOUT (0<<14)
  102. #define GPIO_BOUT_ISR (1<<14)
  103. #define GPIO_BOUT_0 (2<<14)
  104. #define GPIO_BOUT_1 (3<<14)
  105. #define GPIO_GIUS (1<<16)
  106. /* assignements for GPIO alternate/primary functions */
  107. /* FIXME: This list is not completed. The correct directions are
  108. * missing on some (many) pins
  109. */
  110. #define PA0_AIN_SPI2_CLK ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0 )
  111. #define PA0_AF_ETMTRACESYNC ( GPIO_PORTA | GPIO_AF | 0 )
  112. #define PA1_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1 )
  113. #define PA1_PF_TIN ( GPIO_PORTA | GPIO_PF | 1 )
  114. #define PA2_PF_PWM0 ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 2 )
  115. #define PA3_PF_CSI_MCLK ( GPIO_PORTA | GPIO_PF | 3 )
  116. #define PA4_PF_CSI_D0 ( GPIO_PORTA | GPIO_PF | 4 )
  117. #define PA5_PF_CSI_D1 ( GPIO_PORTA | GPIO_PF | 5 )
  118. #define PA6_PF_CSI_D2 ( GPIO_PORTA | GPIO_PF | 6 )
  119. #define PA7_PF_CSI_D3 ( GPIO_PORTA | GPIO_PF | 7 )
  120. #define PA8_PF_CSI_D4 ( GPIO_PORTA | GPIO_PF | 8 )
  121. #define PA9_PF_CSI_D5 ( GPIO_PORTA | GPIO_PF | 9 )
  122. #define PA10_PF_CSI_D6 ( GPIO_PORTA | GPIO_PF | 10 )
  123. #define PA11_PF_CSI_D7 ( GPIO_PORTA | GPIO_PF | 11 )
  124. #define PA12_PF_CSI_VSYNC ( GPIO_PORTA | GPIO_PF | 12 )
  125. #define PA13_PF_CSI_HSYNC ( GPIO_PORTA | GPIO_PF | 13 )
  126. #define PA14_PF_CSI_PIXCLK ( GPIO_PORTA | GPIO_PF | 14 )
  127. #define PA15_PF_I2C_SDA ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 15 )
  128. #define PA16_PF_I2C_SCL ( GPIO_PORTA | GPIO_OUT | GPIO_PF | 16 )
  129. #define PA17_AF_ETMTRACEPKT4 ( GPIO_PORTA | GPIO_AF | 17 )
  130. #define PA17_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17 )
  131. #define PA18_AF_ETMTRACEPKT5 ( GPIO_PORTA | GPIO_AF | 18 )
  132. #define PA19_AF_ETMTRACEPKT6 ( GPIO_PORTA | GPIO_AF | 19 )
  133. #define PA20_AF_ETMTRACEPKT7 ( GPIO_PORTA | GPIO_AF | 20 )
  134. #define PA21_PF_A0 ( GPIO_PORTA | GPIO_PF | 21 )
  135. #define PA22_PF_CS4 ( GPIO_PORTA | GPIO_PF | 22 )
  136. #define PA23_PF_CS5 ( GPIO_PORTA | GPIO_PF | 23 )
  137. #define PA24_PF_A16 ( GPIO_PORTA | GPIO_PF | 24 )
  138. #define PA24_AF_ETMTRACEPKT0 ( GPIO_PORTA | GPIO_AF | 24 )
  139. #define PA25_PF_A17 ( GPIO_PORTA | GPIO_PF | 25 )
  140. #define PA25_AF_ETMTRACEPKT1 ( GPIO_PORTA | GPIO_AF | 25 )
  141. #define PA26_PF_A18 ( GPIO_PORTA | GPIO_PF | 26 )
  142. #define PA26_AF_ETMTRACEPKT2 ( GPIO_PORTA | GPIO_AF | 26 )
  143. #define PA27_PF_A19 ( GPIO_PORTA | GPIO_PF | 27 )
  144. #define PA27_AF_ETMTRACEPKT3 ( GPIO_PORTA | GPIO_AF | 27 )
  145. #define PA28_PF_A20 ( GPIO_PORTA | GPIO_PF | 28 )
  146. #define PA28_AF_ETMPIPESTAT0 ( GPIO_PORTA | GPIO_AF | 28 )
  147. #define PA29_PF_A21 ( GPIO_PORTA | GPIO_PF | 29 )
  148. #define PA29_AF_ETMPIPESTAT1 ( GPIO_PORTA | GPIO_AF | 29 )
  149. #define PA30_PF_A22 ( GPIO_PORTA | GPIO_PF | 30 )
  150. #define PA30_AF_ETMPIPESTAT2 ( GPIO_PORTA | GPIO_AF | 30 )
  151. #define PA31_PF_A23 ( GPIO_PORTA | GPIO_PF | 31 )
  152. #define PA31_AF_ETMTRACECLK ( GPIO_PORTA | GPIO_AF | 31 )
  153. #define PB8_PF_SD_DAT0 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 8 )
  154. #define PB8_AF_MS_PIO ( GPIO_PORTB | GPIO_AF | 8 )
  155. #define PB9_PF_SD_DAT1 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 9 )
  156. #define PB9_AF_MS_PI1 ( GPIO_PORTB | GPIO_AF | 9 )
  157. #define PB10_PF_SD_DAT2 ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 10 )
  158. #define PB10_AF_MS_SCLKI ( GPIO_PORTB | GPIO_AF | 10 )
  159. #define PB11_PF_SD_DAT3 ( GPIO_PORTB | GPIO_PF | 11 )
  160. #define PB11_AF_MS_SDIO ( GPIO_PORTB | GPIO_AF | 11 )
  161. #define PB12_PF_SD_CLK ( GPIO_PORTB | GPIO_PF | 12 )
  162. #define PB12_AF_MS_SCLK0 ( GPIO_PORTB | GPIO_AF | 12 )
  163. #define PB13_PF_SD_CMD ( GPIO_PORTB | GPIO_PF | GPIO_PUEN | 13 )
  164. #define PB13_AF_MS_BS ( GPIO_PORTB | GPIO_AF | 13 )
  165. #define PB14_AF_SSI_RXFS ( GPIO_PORTB | GPIO_AF | 14 )
  166. #define PB15_AF_SSI_RXCLK ( GPIO_PORTB | GPIO_AF | 15 )
  167. #define PB16_AF_SSI_RXDAT ( GPIO_PORTB | GPIO_IN | GPIO_AF | 16 )
  168. #define PB17_AF_SSI_TXDAT ( GPIO_PORTB | GPIO_OUT | GPIO_AF | 17 )
  169. #define PB18_AF_SSI_TXFS ( GPIO_PORTB | GPIO_AF | 18 )
  170. #define PB19_AF_SSI_TXCLK ( GPIO_PORTB | GPIO_AF | 19 )
  171. #define PB20_PF_USBD_AFE ( GPIO_PORTB | GPIO_PF | 20 )
  172. #define PB21_PF_USBD_OE ( GPIO_PORTB | GPIO_PF | 21 )
  173. #define PB22_PFUSBD_RCV ( GPIO_PORTB | GPIO_PF | 22 )
  174. #define PB23_PF_USBD_SUSPND ( GPIO_PORTB | GPIO_PF | 23 )
  175. #define PB24_PF_USBD_VP ( GPIO_PORTB | GPIO_PF | 24 )
  176. #define PB25_PF_USBD_VM ( GPIO_PORTB | GPIO_PF | 25 )
  177. #define PB26_PF_USBD_VPO ( GPIO_PORTB | GPIO_PF | 26 )
  178. #define PB27_PF_USBD_VMO ( GPIO_PORTB | GPIO_PF | 27 )
  179. #define PB28_PF_UART2_CTS ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 28 )
  180. #define PB29_PF_UART2_RTS ( GPIO_PORTB | GPIO_IN | GPIO_PF | 29 )
  181. #define PB30_PF_UART2_TXD ( GPIO_PORTB | GPIO_OUT | GPIO_PF | 30 )
  182. #define PB31_PF_UART2_RXD ( GPIO_PORTB | GPIO_IN | GPIO_PF | 31 )
  183. #define PC3_PF_SSI_RXFS ( GPIO_PORTC | GPIO_PF | 3 )
  184. #define PC4_PF_SSI_RXCLK ( GPIO_PORTC | GPIO_PF | 4 )
  185. #define PC5_PF_SSI_RXDAT ( GPIO_PORTC | GPIO_IN | GPIO_PF | 5 )
  186. #define PC6_PF_SSI_TXDAT ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 6 )
  187. #define PC7_PF_SSI_TXFS ( GPIO_PORTC | GPIO_PF | 7 )
  188. #define PC8_PF_SSI_TXCLK ( GPIO_PORTC | GPIO_PF | 8 )
  189. #define PC9_PF_UART1_CTS ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 9 )
  190. #define PC10_PF_UART1_RTS ( GPIO_PORTC | GPIO_IN | GPIO_PF | 10 )
  191. #define PC11_PF_UART1_TXD ( GPIO_PORTC | GPIO_OUT | GPIO_PF | 11 )
  192. #define PC12_PF_UART1_RXD ( GPIO_PORTC | GPIO_IN | GPIO_PF | 12 )
  193. #define PC13_PF_SPI1_SPI_RDY ( GPIO_PORTC | GPIO_PF | 13 )
  194. #define PC14_PF_SPI1_SCLK ( GPIO_PORTC | GPIO_PF | 14 )
  195. #define PC15_PF_SPI1_SS ( GPIO_PORTC | GPIO_PF | 15 )
  196. #define PC16_PF_SPI1_MISO ( GPIO_PORTC | GPIO_PF | 16 )
  197. #define PC17_PF_SPI1_MOSI ( GPIO_PORTC | GPIO_PF | 17 )
  198. #define PC24_BIN_UART3_RI ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24 )
  199. #define PC25_BIN_UART3_DSR ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25 )
  200. #define PC26_AOUT_UART3_DTR ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26 )
  201. #define PC27_BIN_UART3_DCD ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27 )
  202. #define PC28_BIN_UART3_CTS ( GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28 )
  203. #define PC29_AOUT_UART3_RTS ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29 )
  204. #define PC30_BIN_UART3_TX ( GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30 )
  205. #define PC31_AOUT_UART3_RX ( GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
  206. #define PD6_PF_LSCLK ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 6 )
  207. #define PD7_PF_REV ( GPIO_PORTD | GPIO_PF | 7 )
  208. #define PD7_AF_UART2_DTR ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7 )
  209. #define PD7_AIN_SPI2_SCLK ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7 )
  210. #define PD8_PF_CLS ( GPIO_PORTD | GPIO_PF | 8 )
  211. #define PD8_AF_UART2_DCD ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 8 )
  212. #define PD8_AIN_SPI2_SS ( GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8 )
  213. #define PD9_PF_PS ( GPIO_PORTD | GPIO_PF | 9 )
  214. #define PD9_AF_UART2_RI ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 9 )
  215. #define PD9_AOUT_SPI2_RXD ( GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9 )
  216. #define PD10_PF_SPL_SPR ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 10 )
  217. #define PD10_AF_UART2_DSR ( GPIO_PORTD | GPIO_OUT | GPIO_AF | 10 )
  218. #define PD10_AIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10 )
  219. #define PD11_PF_CONTRAST ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 11 )
  220. #define PD12_PF_ACD_OE ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 12 )
  221. #define PD13_PF_LP_HSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 13 )
  222. #define PD14_PF_FLM_VSYNC ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 14 )
  223. #define PD15_PF_LD0 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 15 )
  224. #define PD16_PF_LD1 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 16 )
  225. #define PD17_PF_LD2 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 17 )
  226. #define PD18_PF_LD3 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 18 )
  227. #define PD19_PF_LD4 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 19 )
  228. #define PD20_PF_LD5 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 20 )
  229. #define PD21_PF_LD6 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 21 )
  230. #define PD22_PF_LD7 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 22 )
  231. #define PD23_PF_LD8 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 23 )
  232. #define PD24_PF_LD9 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 24 )
  233. #define PD25_PF_LD10 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 25 )
  234. #define PD26_PF_LD11 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 26 )
  235. #define PD27_PF_LD12 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 27 )
  236. #define PD28_PF_LD13 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 28 )
  237. #define PD29_PF_LD14 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 29 )
  238. #define PD30_PF_LD15 ( GPIO_PORTD | GPIO_OUT | GPIO_PF | 30 )
  239. #define PD31_PF_TMR2OUT ( GPIO_PORTD | GPIO_PF | 31 )
  240. #define PD31_BIN_SPI2_TXD ( GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31 )
  241. /*
  242. * PWM controller
  243. */
  244. #define PWMC __REG(IMX_PWM_BASE + 0x00) /* PWM Control Register */
  245. #define PWMS __REG(IMX_PWM_BASE + 0x04) /* PWM Sample Register */
  246. #define PWMP __REG(IMX_PWM_BASE + 0x08) /* PWM Period Register */
  247. #define PWMCNT __REG(IMX_PWM_BASE + 0x0C) /* PWM Counter Register */
  248. #define PWMC_HCTR (0x01<<18) /* Halfword FIFO Data Swapping */
  249. #define PWMC_BCTR (0x01<<17) /* Byte FIFO Data Swapping */
  250. #define PWMC_SWR (0x01<<16) /* Software Reset */
  251. #define PWMC_CLKSRC (0x01<<15) /* Clock Source */
  252. #define PWMC_PRESCALER(x) (((x-1) & 0x7F) << 8) /* PRESCALER */
  253. #define PWMC_IRQ (0x01<< 7) /* Interrupt Request */
  254. #define PWMC_IRQEN (0x01<< 6) /* Interrupt Request Enable */
  255. #define PWMC_FIFOAV (0x01<< 5) /* FIFO Available */
  256. #define PWMC_EN (0x01<< 4) /* Enables/Disables the PWM */
  257. #define PWMC_REPEAT(x) (((x) & 0x03) << 2) /* Sample Repeats */
  258. #define PWMC_CLKSEL(x) (((x) & 0x03) << 0) /* Clock Selection */
  259. #define PWMS_SAMPLE(x) ((x) & 0xFFFF) /* Contains a two-sample word */
  260. #define PWMP_PERIOD(x) ((x) & 0xFFFF) /* Represents the PWM's period */
  261. #define PWMC_COUNTER(x) ((x) & 0xFFFF) /* Represents the current count value */
  262. /*
  263. * DMA Controller
  264. */
  265. #define DCR __REG(IMX_DMAC_BASE +0x00) /* DMA Control Register */
  266. #define DISR __REG(IMX_DMAC_BASE +0x04) /* DMA Interrupt status Register */
  267. #define DIMR __REG(IMX_DMAC_BASE +0x08) /* DMA Interrupt mask Register */
  268. #define DBTOSR __REG(IMX_DMAC_BASE +0x0c) /* DMA Burst timeout status Register */
  269. #define DRTOSR __REG(IMX_DMAC_BASE +0x10) /* DMA Request timeout Register */
  270. #define DSESR __REG(IMX_DMAC_BASE +0x14) /* DMA Transfer Error Status Register */
  271. #define DBOSR __REG(IMX_DMAC_BASE +0x18) /* DMA Buffer overflow status Register */
  272. #define DBTOCR __REG(IMX_DMAC_BASE +0x1c) /* DMA Burst timeout control Register */
  273. #define WSRA __REG(IMX_DMAC_BASE +0x40) /* W-Size Register A */
  274. #define XSRA __REG(IMX_DMAC_BASE +0x44) /* X-Size Register A */
  275. #define YSRA __REG(IMX_DMAC_BASE +0x48) /* Y-Size Register A */
  276. #define WSRB __REG(IMX_DMAC_BASE +0x4c) /* W-Size Register B */
  277. #define XSRB __REG(IMX_DMAC_BASE +0x50) /* X-Size Register B */
  278. #define YSRB __REG(IMX_DMAC_BASE +0x54) /* Y-Size Register B */
  279. #define SAR(x) __REG2( IMX_DMAC_BASE + 0x80, (x) << 6) /* Source Address Registers */
  280. #define DAR(x) __REG2( IMX_DMAC_BASE + 0x84, (x) << 6) /* Destination Address Registers */
  281. #define CNTR(x) __REG2( IMX_DMAC_BASE + 0x88, (x) << 6) /* Count Registers */
  282. #define CCR(x) __REG2( IMX_DMAC_BASE + 0x8c, (x) << 6) /* Control Registers */
  283. #define RSSR(x) __REG2( IMX_DMAC_BASE + 0x90, (x) << 6) /* Request source select Registers */
  284. #define BLR(x) __REG2( IMX_DMAC_BASE + 0x94, (x) << 6) /* Burst length Registers */
  285. #define RTOR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Request timeout Registers */
  286. #define BUCR(x) __REG2( IMX_DMAC_BASE + 0x98, (x) << 6) /* Bus Utilization Registers */
  287. #define DCR_DRST (1<<1)
  288. #define DCR_DEN (1<<0)
  289. #define DBTOCR_EN (1<<15)
  290. #define DBTOCR_CNT(x) ((x) & 0x7fff )
  291. #define CNTR_CNT(x) ((x) & 0xffffff )
  292. #define CCR_DMOD_LINEAR ( 0x0 << 12 )
  293. #define CCR_DMOD_2D ( 0x1 << 12 )
  294. #define CCR_DMOD_FIFO ( 0x2 << 12 )
  295. #define CCR_DMOD_EOBFIFO ( 0x3 << 12 )
  296. #define CCR_SMOD_LINEAR ( 0x0 << 10 )
  297. #define CCR_SMOD_2D ( 0x1 << 10 )
  298. #define CCR_SMOD_FIFO ( 0x2 << 10 )
  299. #define CCR_SMOD_EOBFIFO ( 0x3 << 10 )
  300. #define CCR_MDIR_DEC (1<<9)
  301. #define CCR_MSEL_B (1<<8)
  302. #define CCR_DSIZ_32 ( 0x0 << 6 )
  303. #define CCR_DSIZ_8 ( 0x1 << 6 )
  304. #define CCR_DSIZ_16 ( 0x2 << 6 )
  305. #define CCR_SSIZ_32 ( 0x0 << 4 )
  306. #define CCR_SSIZ_8 ( 0x1 << 4 )
  307. #define CCR_SSIZ_16 ( 0x2 << 4 )
  308. #define CCR_REN (1<<3)
  309. #define CCR_RPT (1<<2)
  310. #define CCR_FRC (1<<1)
  311. #define CCR_CEN (1<<0)
  312. #define RTOR_EN (1<<15)
  313. #define RTOR_CLK (1<<14)
  314. #define RTOR_PSC (1<<13)
  315. /*
  316. * Interrupt controller
  317. */
  318. #define IMX_INTCNTL __REG(IMX_AITC_BASE+0x00)
  319. #define INTCNTL_FIAD (1<<19)
  320. #define INTCNTL_NIAD (1<<20)
  321. #define IMX_NIMASK __REG(IMX_AITC_BASE+0x04)
  322. #define IMX_INTENNUM __REG(IMX_AITC_BASE+0x08)
  323. #define IMX_INTDISNUM __REG(IMX_AITC_BASE+0x0c)
  324. #define IMX_INTENABLEH __REG(IMX_AITC_BASE+0x10)
  325. #define IMX_INTENABLEL __REG(IMX_AITC_BASE+0x14)
  326. /*
  327. * General purpose timers
  328. */
  329. #define IMX_TCTL(x) __REG( 0x00 + (x))
  330. #define TCTL_SWR (1<<15)
  331. #define TCTL_FRR (1<<8)
  332. #define TCTL_CAP_RIS (1<<6)
  333. #define TCTL_CAP_FAL (2<<6)
  334. #define TCTL_CAP_RIS_FAL (3<<6)
  335. #define TCTL_OM (1<<5)
  336. #define TCTL_IRQEN (1<<4)
  337. #define TCTL_CLK_PCLK1 (1<<1)
  338. #define TCTL_CLK_PCLK1_16 (2<<1)
  339. #define TCTL_CLK_TIN (3<<1)
  340. #define TCTL_CLK_32 (4<<1)
  341. #define TCTL_TEN (1<<0)
  342. #define IMX_TPRER(x) __REG( 0x04 + (x))
  343. #define IMX_TCMP(x) __REG( 0x08 + (x))
  344. #define IMX_TCR(x) __REG( 0x0C + (x))
  345. #define IMX_TCN(x) __REG( 0x10 + (x))
  346. #define IMX_TSTAT(x) __REG( 0x14 + (x))
  347. #define TSTAT_CAPT (1<<1)
  348. #define TSTAT_COMP (1<<0)
  349. /*
  350. * LCD Controller
  351. */
  352. #define LCDC_SSA __REG(IMX_LCDC_BASE+0x00)
  353. #define LCDC_SIZE __REG(IMX_LCDC_BASE+0x04)
  354. #define SIZE_XMAX(x) ((((x) >> 4) & 0x3f) << 20)
  355. #define SIZE_YMAX(y) ( (y) & 0x1ff )
  356. #define LCDC_VPW __REG(IMX_LCDC_BASE+0x08)
  357. #define VPW_VPW(x) ( (x) & 0x3ff )
  358. #define LCDC_CPOS __REG(IMX_LCDC_BASE+0x0C)
  359. #define CPOS_CC1 (1<<31)
  360. #define CPOS_CC0 (1<<30)
  361. #define CPOS_OP (1<<28)
  362. #define CPOS_CXP(x) (((x) & 3ff) << 16)
  363. #define CPOS_CYP(y) ((y) & 0x1ff)
  364. #define LCDC_LCWHB __REG(IMX_LCDC_BASE+0x10)
  365. #define LCWHB_BK_EN (1<<31)
  366. #define LCWHB_CW(w) (((w) & 0x1f) << 24)
  367. #define LCWHB_CH(h) (((h) & 0x1f) << 16)
  368. #define LCWHB_BD(x) ((x) & 0xff)
  369. #define LCDC_LCHCC __REG(IMX_LCDC_BASE+0x14)
  370. #define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
  371. #define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
  372. #define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
  373. #define LCDC_PCR __REG(IMX_LCDC_BASE+0x18)
  374. #define PCR_TFT (1<<31)
  375. #define PCR_COLOR (1<<30)
  376. #define PCR_PBSIZ_1 (0<<28)
  377. #define PCR_PBSIZ_2 (1<<28)
  378. #define PCR_PBSIZ_4 (2<<28)
  379. #define PCR_PBSIZ_8 (3<<28)
  380. #define PCR_BPIX_1 (0<<25)
  381. #define PCR_BPIX_2 (1<<25)
  382. #define PCR_BPIX_4 (2<<25)
  383. #define PCR_BPIX_8 (3<<25)
  384. #define PCR_BPIX_12 (4<<25)
  385. #define PCR_BPIX_16 (4<<25)
  386. #define PCR_PIXPOL (1<<24)
  387. #define PCR_FLMPOL (1<<23)
  388. #define PCR_LPPOL (1<<22)
  389. #define PCR_CLKPOL (1<<21)
  390. #define PCR_OEPOL (1<<20)
  391. #define PCR_SCLKIDLE (1<<19)
  392. #define PCR_END_SEL (1<<18)
  393. #define PCR_END_BYTE_SWAP (1<<17)
  394. #define PCR_REV_VS (1<<16)
  395. #define PCR_ACD_SEL (1<<15)
  396. #define PCR_ACD(x) (((x) & 0x7f) << 8)
  397. #define PCR_SCLK_SEL (1<<7)
  398. #define PCR_SHARP (1<<6)
  399. #define PCR_PCD(x) ((x) & 0x3f)
  400. #define LCDC_HCR __REG(IMX_LCDC_BASE+0x1C)
  401. #define HCR_H_WIDTH(x) (((x) & 0x3f) << 26)
  402. #define HCR_H_WAIT_1(x) (((x) & 0xff) << 8)
  403. #define HCR_H_WAIT_2(x) ((x) & 0xff)
  404. #define LCDC_VCR __REG(IMX_LCDC_BASE+0x20)
  405. #define VCR_V_WIDTH(x) (((x) & 0x3f) << 26)
  406. #define VCR_V_WAIT_1(x) (((x) & 0xff) << 8)
  407. #define VCR_V_WAIT_2(x) ((x) & 0xff)
  408. #define LCDC_POS __REG(IMX_LCDC_BASE+0x24)
  409. #define POS_POS(x) ((x) & 1f)
  410. #define LCDC_LSCR1 __REG(IMX_LCDC_BASE+0x28)
  411. #define LSCR1_PS_RISE_DELAY(x) (((x) & 0x7f) << 26)
  412. #define LSCR1_CLS_RISE_DELAY(x) (((x) & 0x3f) << 16)
  413. #define LSCR1_REV_TOGGLE_DELAY(x) (((x) & 0xf) << 8)
  414. #define LSCR1_GRAY2(x) (((x) & 0xf) << 4)
  415. #define LSCR1_GRAY1(x) (((x) & 0xf))
  416. #define LCDC_PWMR __REG(IMX_LCDC_BASE+0x2C)
  417. #define PWMR_CLS(x) (((x) & 0x1ff) << 16)
  418. #define PWMR_LDMSK (1<<15)
  419. #define PWMR_SCR1 (1<<10)
  420. #define PWMR_SCR0 (1<<9)
  421. #define PWMR_CC_EN (1<<8)
  422. #define PWMR_PW(x) ((x) & 0xff)
  423. #define LCDC_DMACR __REG(IMX_LCDC_BASE+0x30)
  424. #define DMACR_BURST (1<<31)
  425. #define DMACR_HM(x) (((x) & 0xf) << 16)
  426. #define DMACR_TM(x) ((x) &0xf)
  427. #define LCDC_RMCR __REG(IMX_LCDC_BASE+0x34)
  428. #define RMCR_LCDC_EN (1<<1)
  429. #define RMCR_SELF_REF (1<<0)
  430. #define LCDC_LCDICR __REG(IMX_LCDC_BASE+0x38)
  431. #define LCDICR_INT_SYN (1<<2)
  432. #define LCDICR_INT_CON (1)
  433. #define LCDC_LCDISR __REG(IMX_LCDC_BASE+0x40)
  434. #define LCDISR_UDR_ERR (1<<3)
  435. #define LCDISR_ERR_RES (1<<2)
  436. #define LCDISR_EOF (1<<1)
  437. #define LCDISR_BOF (1<<0)
  438. /*
  439. * UART Module. Takes the UART base address as argument
  440. */
  441. #define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
  442. #define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
  443. #define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */
  444. #define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */
  445. #define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */
  446. #define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */
  447. #define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */
  448. #define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */
  449. #define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */
  450. #define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */
  451. #define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */
  452. #define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */
  453. #define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */
  454. #define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */
  455. #define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
  456. #define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
  457. #define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
  458. #define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
  459. #define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
  460. #define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
  461. #define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
  462. #define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
  463. #define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */
  464. /* UART Control Register Bit Fields.*/
  465. #define URXD_CHARRDY (1<<15)
  466. #define URXD_ERR (1<<14)
  467. #define URXD_OVRRUN (1<<13)
  468. #define URXD_FRMERR (1<<12)
  469. #define URXD_BRK (1<<11)
  470. #define URXD_PRERR (1<<10)
  471. #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */
  472. #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
  473. #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
  474. #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
  475. #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
  476. #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
  477. #define UCR1_IREN (1<<7) /* Infrared interface enable */
  478. #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
  479. #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
  480. #define UCR1_SNDBRK (1<<4) /* Send break */
  481. #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
  482. #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
  483. #define UCR1_DOZE (1<<1) /* Doze */
  484. #define UCR1_UARTEN (1<<0) /* UART enabled */
  485. #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
  486. #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
  487. #define UCR2_CTSC (1<<13) /* CTS pin control */
  488. #define UCR2_CTS (1<<12) /* Clear to send */
  489. #define UCR2_ESCEN (1<<11) /* Escape enable */
  490. #define UCR2_PREN (1<<8) /* Parity enable */
  491. #define UCR2_PROE (1<<7) /* Parity odd/even */
  492. #define UCR2_STPB (1<<6) /* Stop */
  493. #define UCR2_WS (1<<5) /* Word size */
  494. #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
  495. #define UCR2_TXEN (1<<2) /* Transmitter enabled */
  496. #define UCR2_RXEN (1<<1) /* Receiver enabled */
  497. #define UCR2_SRST (1<<0) /* SW reset */
  498. #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
  499. #define UCR3_PARERREN (1<<12) /* Parity enable */
  500. #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
  501. #define UCR3_DSR (1<<10) /* Data set ready */
  502. #define UCR3_DCD (1<<9) /* Data carrier detect */
  503. #define UCR3_RI (1<<8) /* Ring indicator */
  504. #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
  505. #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
  506. #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
  507. #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
  508. #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */
  509. #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */
  510. #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
  511. #define UCR3_BPEN (1<<0) /* Preset registers enable */
  512. #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */
  513. #define UCR4_INVR (1<<9) /* Inverted infrared reception */
  514. #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
  515. #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
  516. #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
  517. #define UCR4_IRSC (1<<5) /* IR special case */
  518. #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
  519. #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
  520. #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
  521. #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
  522. #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
  523. #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
  524. #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
  525. #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
  526. #define USR1_RTSS (1<<14) /* RTS pin status */
  527. #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
  528. #define USR1_RTSD (1<<12) /* RTS delta */
  529. #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
  530. #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
  531. #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
  532. #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
  533. #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
  534. #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
  535. #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
  536. #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
  537. #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
  538. #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
  539. #define USR2_IDLE (1<<12) /* Idle condition */
  540. #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
  541. #define USR2_WAKE (1<<7) /* Wake */
  542. #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
  543. #define USR2_TXDC (1<<3) /* Transmitter complete */
  544. #define USR2_BRCD (1<<2) /* Break condition */
  545. #define USR2_ORE (1<<1) /* Overrun error */
  546. #define USR2_RDR (1<<0) /* Recv data ready */
  547. #define UTS_FRCPERR (1<<13) /* Force parity error */
  548. #define UTS_LOOP (1<<12) /* Loop tx and rx */
  549. #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
  550. #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
  551. #define UTS_TXFULL (1<<4) /* TxFIFO full */
  552. #define UTS_RXFULL (1<<3) /* RxFIFO full */
  553. #define UTS_SOFTRST (1<<0) /* Software reset */
  554. #endif // _IMX_REGS_H