hardware.h 6.4 KB

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  1. /*
  2. * linux/include/asm-arm/arch-clps711x/hardware.h
  3. *
  4. * This file contains the hardware definitions of the Prospector P720T.
  5. *
  6. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #ifndef __ASM_ARCH_HARDWARE_H
  23. #define __ASM_ARCH_HARDWARE_H
  24. #define CLPS7111_VIRT_BASE 0xff000000
  25. #define CLPS7111_BASE CLPS7111_VIRT_BASE
  26. /*
  27. * The physical addresses that the external chip select signals map to is
  28. * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
  29. * processors. CONFIG_EP72XX_BOOT_ROM is only available if these
  30. * processors are in use.
  31. */
  32. #ifndef CONFIG_EP72XX_ROM_BOOT
  33. #define CS0_PHYS_BASE (0x00000000)
  34. #define CS1_PHYS_BASE (0x10000000)
  35. #define CS2_PHYS_BASE (0x20000000)
  36. #define CS3_PHYS_BASE (0x30000000)
  37. #define CS4_PHYS_BASE (0x40000000)
  38. #define CS5_PHYS_BASE (0x50000000)
  39. #define CS6_PHYS_BASE (0x60000000)
  40. #define CS7_PHYS_BASE (0x70000000)
  41. #else
  42. #define CS0_PHYS_BASE (0x70000000)
  43. #define CS1_PHYS_BASE (0x60000000)
  44. #define CS2_PHYS_BASE (0x50000000)
  45. #define CS3_PHYS_BASE (0x40000000)
  46. #define CS4_PHYS_BASE (0x30000000)
  47. #define CS5_PHYS_BASE (0x20000000)
  48. #define CS6_PHYS_BASE (0x10000000)
  49. #define CS7_PHYS_BASE (0x00000000)
  50. #endif
  51. #if defined (CONFIG_ARCH_EP7211)
  52. #define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
  53. #define EP7211_BASE CLPS7111_VIRT_BASE
  54. #include <asm/hardware/ep7211.h>
  55. #elif defined (CONFIG_ARCH_EP7212)
  56. #define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
  57. #define EP7212_BASE CLPS7111_VIRT_BASE
  58. #include <asm/hardware/ep7212.h>
  59. #endif
  60. #define SYSPLD_VIRT_BASE 0xfe000000
  61. #define SYSPLD_BASE SYSPLD_VIRT_BASE
  62. #ifndef __ASSEMBLER__
  63. #define PCIO_BASE IO_BASE
  64. #endif
  65. #if defined (CONFIG_ARCH_AUTCPU12)
  66. #define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
  67. #define CS89712_BASE CLPS7111_VIRT_BASE
  68. #include <asm/hardware/clps7111.h>
  69. #include <asm/hardware/ep7212.h>
  70. #include <asm/hardware/cs89712.h>
  71. #endif
  72. #if defined (CONFIG_ARCH_CDB89712)
  73. #include <asm/hardware/clps7111.h>
  74. #include <asm/hardware/ep7212.h>
  75. #include <asm/hardware/cs89712.h>
  76. /* dynamic ioremap() areas */
  77. #define FLASH_START 0x00000000
  78. #define FLASH_SIZE 0x800000
  79. #define FLASH_WIDTH 4
  80. #define SRAM_START 0x60000000
  81. #define SRAM_SIZE 0xc000
  82. #define SRAM_WIDTH 4
  83. #define BOOTROM_START 0x70000000
  84. #define BOOTROM_SIZE 0x80
  85. #define BOOTROM_WIDTH 4
  86. /* static cdb89712_map_io() areas */
  87. #define REGISTER_START 0x80000000
  88. #define REGISTER_SIZE 0x4000
  89. #define REGISTER_BASE 0xff000000
  90. #define ETHER_START 0x20000000
  91. #define ETHER_SIZE 0x1000
  92. #define ETHER_BASE 0xfe000000
  93. #endif
  94. #if defined (CONFIG_ARCH_EDB7211)
  95. /*
  96. * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
  97. * and repeat across it. This is the mapping for it.
  98. *
  99. * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
  100. * was cause for much consternation and headscratching. This should probably
  101. * be made a compile/run time kernel option.
  102. */
  103. #define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
  104. #define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
  105. /*
  106. * The CS8900A ethernet chip has its I/O registers wired to chip select 2
  107. * (nCS2). This is the mapping for it.
  108. *
  109. * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
  110. * was cause for much consternation and headscratching. This should probably
  111. * be made a compile/run time kernel option.
  112. */
  113. #define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
  114. #define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
  115. /*
  116. * The two flash banks are wired to chip selects 0 and 1. This is the mapping
  117. * for them.
  118. *
  119. * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
  120. * in jumpered boot mode.
  121. */
  122. #define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
  123. #define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
  124. #define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
  125. #define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
  126. #endif /* CONFIG_ARCH_EDB7211 */
  127. /*
  128. * Relevant bits in port D, which controls power to the various parts of
  129. * the LCD on the EDB7211.
  130. */
  131. #define EDB_PD1_LCD_DC_DC_EN (1<<1)
  132. #define EDB_PD2_LCDEN (1<<2)
  133. #define EDB_PD3_LCDBL (1<<3)
  134. #if defined (CONFIG_ARCH_CEIVA)
  135. #define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
  136. #define CEIVA_BASE CLPS7111_VIRT_BASE
  137. #include <asm/hardware/clps7111.h>
  138. #include <asm/hardware/ep7212.h>
  139. /*
  140. * The two flash banks are wired to chip selects 0 and 1. This is the mapping
  141. * for them.
  142. *
  143. * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
  144. * in jumpered boot mode.
  145. */
  146. #define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
  147. #define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
  148. #define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */
  149. #define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */
  150. #define CEIVA_FLASH_SIZE 0x100000
  151. #define CEIVA_FLASH_WIDTH 2
  152. #define SRAM_START 0x60000000
  153. #define SRAM_SIZE 0xc000
  154. #define SRAM_WIDTH 4
  155. #define BOOTROM_START 0x70000000
  156. #define BOOTROM_SIZE 0x80
  157. #define BOOTROM_WIDTH 4
  158. /*
  159. * SED1355 LCD controller
  160. */
  161. #define CEIVA_PHYS_SED1355 CS2_PHYS_BASE
  162. #define CEIVA_VIRT_SED1355 (0xfc000000)
  163. /*
  164. * Relevant bits in port D, which controls power to the various parts of
  165. * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
  166. */
  167. // Reset line to SED1355 (must be high to operate)
  168. #define CEIVA_PD1_LCDRST (1<<1)
  169. // LCD panel enable (set to one, to enable LCD)
  170. #define CEIVA_PD4_LCDEN (1<<4)
  171. // Backlight (set to one, to turn on backlight
  172. #define CEIVA_PD5_LCDBL (1<<5)
  173. /*
  174. * Relevant bits in port B, which report the status of the buttons.
  175. */
  176. // White button
  177. #define CEIVA_PB4_WHT_BTN (1<<4)
  178. // Black button
  179. #define CEIVA_PB0_BLK_BTN (1<<0)
  180. #endif // #if defined (CONFIG_ARCH_CEIVA)
  181. #endif