at91sam9263_matrix.h 7.3 KB

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  1. /*
  2. * include/asm-arm/arch-at91/at91sam9263_matrix.h
  3. *
  4. * Copyright (C) 2006 Atmel Corporation.
  5. *
  6. * Memory Controllers (MATRIX, EBI) - System peripherals registers.
  7. * Based on AT91SAM9263 datasheet revision B (Preliminary).
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #ifndef AT91SAM9263_MATRIX_H
  15. #define AT91SAM9263_MATRIX_H
  16. #define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
  17. #define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
  18. #define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
  19. #define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
  20. #define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
  21. #define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
  22. #define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
  23. #define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
  24. #define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
  25. #define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
  26. #define AT91_MATRIX_ULBT_INFINITE (0 << 0)
  27. #define AT91_MATRIX_ULBT_SINGLE (1 << 0)
  28. #define AT91_MATRIX_ULBT_FOUR (2 << 0)
  29. #define AT91_MATRIX_ULBT_EIGHT (3 << 0)
  30. #define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
  31. #define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
  32. #define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
  33. #define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
  34. #define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
  35. #define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
  36. #define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
  37. #define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
  38. #define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
  39. #define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
  40. #define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
  41. #define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
  42. #define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
  43. #define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
  44. #define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
  45. #define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
  46. #define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
  47. #define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
  48. #define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
  49. #define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
  50. #define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
  51. #define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
  52. #define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
  53. #define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
  54. #define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
  55. #define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
  56. #define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
  57. #define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
  58. #define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
  59. #define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
  60. #define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
  61. #define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
  62. #define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
  63. #define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
  64. #define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
  65. #define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
  66. #define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
  67. #define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
  68. #define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
  69. #define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
  70. #define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
  71. #define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
  72. #define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
  73. #define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
  74. #define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
  75. #define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
  76. #define AT91_MATRIX_RCB2 (1 << 2)
  77. #define AT91_MATRIX_RCB3 (1 << 3)
  78. #define AT91_MATRIX_RCB4 (1 << 4)
  79. #define AT91_MATRIX_RCB5 (1 << 5)
  80. #define AT91_MATRIX_RCB6 (1 << 6)
  81. #define AT91_MATRIX_RCB7 (1 << 7)
  82. #define AT91_MATRIX_RCB8 (1 << 8)
  83. #define AT91_MATRIX_TCMR (AT91_MATRIX + 0x114) /* TCM Configuration Register */
  84. #define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
  85. #define AT91_MATRIX_ITCM_0 (0 << 0)
  86. #define AT91_MATRIX_ITCM_16 (5 << 0)
  87. #define AT91_MATRIX_ITCM_32 (6 << 0)
  88. #define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
  89. #define AT91_MATRIX_DTCM_0 (0 << 4)
  90. #define AT91_MATRIX_DTCM_16 (5 << 4)
  91. #define AT91_MATRIX_DTCM_32 (6 << 4)
  92. #define AT91_MATRIX_EBI0CSA (AT91_MATRIX + 0x120) /* EBI0 Chip Select Assignment Register */
  93. #define AT91_MATRIX_EBI0_CS1A (1 << 1) /* Chip Select 1 Assignment */
  94. #define AT91_MATRIX_EBI0_CS1A_SMC (0 << 1)
  95. #define AT91_MATRIX_EBI0_CS1A_SDRAMC (1 << 1)
  96. #define AT91_MATRIX_EBI0_CS3A (1 << 3) /* Chip Select 3 Assignment */
  97. #define AT91_MATRIX_EBI0_CS3A_SMC (0 << 3)
  98. #define AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA (1 << 3)
  99. #define AT91_MATRIX_EBI0_CS4A (1 << 4) /* Chip Select 4 Assignment */
  100. #define AT91_MATRIX_EBI0_CS4A_SMC (0 << 4)
  101. #define AT91_MATRIX_EBI0_CS4A_SMC_CF1 (1 << 4)
  102. #define AT91_MATRIX_EBI0_CS5A (1 << 5) /* Chip Select 5 Assignment */
  103. #define AT91_MATRIX_EBI0_CS5A_SMC (0 << 5)
  104. #define AT91_MATRIX_EBI0_CS5A_SMC_CF2 (1 << 5)
  105. #define AT91_MATRIX_EBI0_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
  106. #define AT91_MATRIX_EBI0_VDDIOMSEL (1 << 16) /* Memory voltage selection */
  107. #define AT91_MATRIX_EBI0_VDDIOMSEL_1_8V (0 << 16)
  108. #define AT91_MATRIX_EBI0_VDDIOMSEL_3_3V (1 << 16)
  109. #define AT91_MATRIX_EBI1CSA (AT91_MATRIX + 0x124) /* EBI1 Chip Select Assignment Register */
  110. #define AT91_MATRIX_EBI1_CS1A (1 << 1) /* Chip Select 1 Assignment */
  111. #define AT91_MATRIX_EBI1_CS1A_SMC (0 << 1)
  112. #define AT91_MATRIX_EBI1_CS1A_SDRAMC (1 << 1)
  113. #define AT91_MATRIX_EBI1_CS2A (1 << 3) /* Chip Select 3 Assignment */
  114. #define AT91_MATRIX_EBI1_CS2A_SMC (0 << 3)
  115. #define AT91_MATRIX_EBI1_CS2A_SMC_SMARTMEDIA (1 << 3)
  116. #define AT91_MATRIX_EBI1_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
  117. #define AT91_MATRIX_EBI1_VDDIOMSEL (1 << 16) /* Memory voltage selection */
  118. #define AT91_MATRIX_EBI1_VDDIOMSEL_1_8V (0 << 16)
  119. #define AT91_MATRIX_EBI1_VDDIOMSEL_3_3V (1 << 16)
  120. #endif