at91sam9260.h 4.7 KB

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  1. /*
  2. * include/asm-arm/arch-at91/at91sam9260.h
  3. *
  4. * (C) 2006 Andrew Victor
  5. *
  6. * Common definitions.
  7. * Based on AT91SAM9260 datasheet revision A (Preliminary).
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #ifndef AT91SAM9260_H
  15. #define AT91SAM9260_H
  16. /*
  17. * Peripheral identifiers/interrupts.
  18. */
  19. #define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
  20. #define AT91_ID_SYS 1 /* System Peripherals */
  21. #define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
  22. #define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
  23. #define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
  24. #define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
  25. #define AT91SAM9260_ID_US0 6 /* USART 0 */
  26. #define AT91SAM9260_ID_US1 7 /* USART 1 */
  27. #define AT91SAM9260_ID_US2 8 /* USART 2 */
  28. #define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
  29. #define AT91SAM9260_ID_UDP 10 /* USB Device Port */
  30. #define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
  31. #define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
  32. #define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
  33. #define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
  34. #define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
  35. #define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
  36. #define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
  37. #define AT91SAM9260_ID_UHP 20 /* USB Host port */
  38. #define AT91SAM9260_ID_EMAC 21 /* Ethernet */
  39. #define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
  40. #define AT91SAM9260_ID_US3 23 /* USART 3 */
  41. #define AT91SAM9260_ID_US4 24 /* USART 4 */
  42. #define AT91SAM9260_ID_US5 25 /* USART 5 */
  43. #define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
  44. #define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
  45. #define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
  46. #define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
  47. #define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
  48. #define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
  49. /*
  50. * User Peripheral physical base addresses.
  51. */
  52. #define AT91SAM9260_BASE_TCB0 0xfffa0000
  53. #define AT91SAM9260_BASE_TC0 0xfffa0000
  54. #define AT91SAM9260_BASE_TC1 0xfffa0040
  55. #define AT91SAM9260_BASE_TC2 0xfffa0080
  56. #define AT91SAM9260_BASE_UDP 0xfffa4000
  57. #define AT91SAM9260_BASE_MCI 0xfffa8000
  58. #define AT91SAM9260_BASE_TWI 0xfffac000
  59. #define AT91SAM9260_BASE_US0 0xfffb0000
  60. #define AT91SAM9260_BASE_US1 0xfffb4000
  61. #define AT91SAM9260_BASE_US2 0xfffb8000
  62. #define AT91SAM9260_BASE_SSC 0xfffbc000
  63. #define AT91SAM9260_BASE_ISI 0xfffc0000
  64. #define AT91SAM9260_BASE_EMAC 0xfffc4000
  65. #define AT91SAM9260_BASE_SPI0 0xfffc8000
  66. #define AT91SAM9260_BASE_SPI1 0xfffcc000
  67. #define AT91SAM9260_BASE_US3 0xfffd0000
  68. #define AT91SAM9260_BASE_US4 0xfffd4000
  69. #define AT91SAM9260_BASE_US5 0xfffd8000
  70. #define AT91SAM9260_BASE_TCB1 0xfffdc000
  71. #define AT91SAM9260_BASE_TC3 0xfffdc000
  72. #define AT91SAM9260_BASE_TC4 0xfffdc040
  73. #define AT91SAM9260_BASE_TC5 0xfffdc080
  74. #define AT91SAM9260_BASE_ADC 0xfffe0000
  75. #define AT91_BASE_SYS 0xffffe800
  76. /*
  77. * System Peripherals (offset from AT91_BASE_SYS)
  78. */
  79. #define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
  80. #define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
  81. #define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
  82. #define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
  83. #define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
  84. #define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
  85. #define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
  86. #define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
  87. #define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
  88. #define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
  89. #define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
  90. #define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
  91. #define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
  92. #define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
  93. #define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
  94. #define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
  95. #define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
  96. /*
  97. * Internal Memory.
  98. */
  99. #define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
  100. #define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
  101. #define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
  102. #define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
  103. #define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
  104. #define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
  105. #define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
  106. #define AT91SAM9XE_FLASH_BASE 0x00200000 /* Internal FLASH base address */
  107. #define AT91SAM9XE_SRAM_BASE 0x00300000 /* Internal SRAM base address */
  108. #if 0
  109. /*
  110. * PIO pin definitions (peripheral A/B multiplexing).
  111. */
  112. // TODO: Add
  113. #endif
  114. #endif