at91rm9200_mc.h 7.4 KB

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  1. /*
  2. * include/asm-arm/arch-at91/at91rm9200_mc.h
  3. *
  4. * Copyright (C) 2005 Ivan Kokshaysky
  5. * Copyright (C) SAN People
  6. *
  7. * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
  8. * Based on AT91RM9200 datasheet revision E.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. */
  15. #ifndef AT91RM9200_MC_H
  16. #define AT91RM9200_MC_H
  17. /* Memory Controller */
  18. #define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
  19. #define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
  20. #define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
  21. #define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
  22. #define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
  23. #define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
  24. #define AT91_MC_ABTSZ_BYTE (0 << 8)
  25. #define AT91_MC_ABTSZ_HALFWORD (1 << 8)
  26. #define AT91_MC_ABTSZ_WORD (2 << 8)
  27. #define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
  28. #define AT91_MC_ABTTYP_DATAREAD (0 << 10)
  29. #define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
  30. #define AT91_MC_ABTTYP_FETCH (2 << 10)
  31. #define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
  32. #define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
  33. #define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
  34. #define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
  35. #define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
  36. #define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
  37. #define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
  38. #define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
  39. #define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
  40. #define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
  41. #define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
  42. #define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
  43. #define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
  44. #define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
  45. /* External Bus Interface (EBI) registers */
  46. #define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
  47. #define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
  48. #define AT91_EBI_CS0A_SMC (0 << 0)
  49. #define AT91_EBI_CS0A_BFC (1 << 0)
  50. #define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
  51. #define AT91_EBI_CS1A_SMC (0 << 1)
  52. #define AT91_EBI_CS1A_SDRAMC (1 << 1)
  53. #define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
  54. #define AT91_EBI_CS3A_SMC (0 << 3)
  55. #define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
  56. #define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
  57. #define AT91_EBI_CS4A_SMC (0 << 4)
  58. #define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
  59. #define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
  60. #define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
  61. /* Static Memory Controller (SMC) registers */
  62. #define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
  63. #define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
  64. #define AT91_SMC_NWS_(x) ((x) << 0)
  65. #define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
  66. #define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
  67. #define AT91_SMC_TDF_(x) ((x) << 8)
  68. #define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
  69. #define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
  70. #define AT91_SMC_DBW_16 (1 << 13)
  71. #define AT91_SMC_DBW_8 (2 << 13)
  72. #define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
  73. #define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
  74. #define AT91_SMC_ACSS_STD (0 << 16)
  75. #define AT91_SMC_ACSS_1 (1 << 16)
  76. #define AT91_SMC_ACSS_2 (2 << 16)
  77. #define AT91_SMC_ACSS_3 (3 << 16)
  78. #define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
  79. #define AT91_SMC_RWSETUP_(x) ((x) << 24)
  80. #define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
  81. #define AT91_SMC_RWHOLD_(x) ((x) << 28)
  82. /* SDRAM Controller registers */
  83. #define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
  84. #define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
  85. #define AT91_SDRAMC_MODE_NORMAL (0 << 0)
  86. #define AT91_SDRAMC_MODE_NOP (1 << 0)
  87. #define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
  88. #define AT91_SDRAMC_MODE_LMR (3 << 0)
  89. #define AT91_SDRAMC_MODE_REFRESH (4 << 0)
  90. #define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
  91. #define AT91_SDRAMC_DBW_32 (0 << 4)
  92. #define AT91_SDRAMC_DBW_16 (1 << 4)
  93. #define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
  94. #define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
  95. #define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
  96. #define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
  97. #define AT91_SDRAMC_NC_8 (0 << 0)
  98. #define AT91_SDRAMC_NC_9 (1 << 0)
  99. #define AT91_SDRAMC_NC_10 (2 << 0)
  100. #define AT91_SDRAMC_NC_11 (3 << 0)
  101. #define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
  102. #define AT91_SDRAMC_NR_11 (0 << 2)
  103. #define AT91_SDRAMC_NR_12 (1 << 2)
  104. #define AT91_SDRAMC_NR_13 (2 << 2)
  105. #define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
  106. #define AT91_SDRAMC_NB_2 (0 << 4)
  107. #define AT91_SDRAMC_NB_4 (1 << 4)
  108. #define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
  109. #define AT91_SDRAMC_CAS_2 (2 << 5)
  110. #define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
  111. #define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
  112. #define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
  113. #define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
  114. #define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
  115. #define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
  116. #define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
  117. #define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
  118. #define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
  119. #define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
  120. #define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
  121. #define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
  122. /* Burst Flash Controller register */
  123. #define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
  124. #define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
  125. #define AT91_BFC_BFCOM_DISABLED (0 << 0)
  126. #define AT91_BFC_BFCOM_ASYNC (1 << 0)
  127. #define AT91_BFC_BFCOM_BURST (2 << 0)
  128. #define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
  129. #define AT91_BFC_BFCC_MCK (1 << 2)
  130. #define AT91_BFC_BFCC_DIV2 (2 << 2)
  131. #define AT91_BFC_BFCC_DIV4 (3 << 2)
  132. #define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
  133. #define AT91_BFC_PAGES (7 << 8) /* Page Size */
  134. #define AT91_BFC_PAGES_NO_PAGE (0 << 8)
  135. #define AT91_BFC_PAGES_16 (1 << 8)
  136. #define AT91_BFC_PAGES_32 (2 << 8)
  137. #define AT91_BFC_PAGES_64 (3 << 8)
  138. #define AT91_BFC_PAGES_128 (4 << 8)
  139. #define AT91_BFC_PAGES_256 (5 << 8)
  140. #define AT91_BFC_PAGES_512 (6 << 8)
  141. #define AT91_BFC_PAGES_1024 (7 << 8)
  142. #define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
  143. #define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
  144. #define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
  145. #define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
  146. #define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
  147. #endif