w100fb.h 24 KB

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  1. /*
  2. * linux/drivers/video/w100fb.h
  3. *
  4. * Frame Buffer Device for ATI w100 (Wallaby)
  5. *
  6. * Copyright (C) 2002, ATI Corp.
  7. * Copyright (C) 2004-2005 Richard Purdie
  8. * Copyright (c) 2005 Ian Molton <spyro@f2s.com>
  9. *
  10. * Modified to work with 2.6 by Richard Purdie <rpurdie@rpsys.net>
  11. *
  12. * w32xx support by Ian Molton
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License version 2 as
  16. * published by the Free Software Foundation.
  17. *
  18. */
  19. #if !defined (_W100FB_H)
  20. #define _W100FB_H
  21. /* Block CIF Start: */
  22. #define mmCHIP_ID 0x0000
  23. #define mmREVISION_ID 0x0004
  24. #define mmWRAP_BUF_A 0x0008
  25. #define mmWRAP_BUF_B 0x000C
  26. #define mmWRAP_TOP_DIR 0x0010
  27. #define mmWRAP_START_DIR 0x0014
  28. #define mmCIF_CNTL 0x0018
  29. #define mmCFGREG_BASE 0x001C
  30. #define mmCIF_IO 0x0020
  31. #define mmCIF_READ_DBG 0x0024
  32. #define mmCIF_WRITE_DBG 0x0028
  33. #define cfgIND_ADDR_A_0 0x0000
  34. #define cfgIND_ADDR_A_1 0x0001
  35. #define cfgIND_ADDR_A_2 0x0002
  36. #define cfgIND_DATA_A 0x0003
  37. #define cfgREG_BASE 0x0004
  38. #define cfgINTF_CNTL 0x0005
  39. #define cfgSTATUS 0x0006
  40. #define cfgCPU_DEFAULTS 0x0007
  41. #define cfgIND_ADDR_B_0 0x0008
  42. #define cfgIND_ADDR_B_1 0x0009
  43. #define cfgIND_ADDR_B_2 0x000A
  44. #define cfgIND_DATA_B 0x000B
  45. #define cfgPM4_RPTR 0x000C
  46. #define cfgSCRATCH 0x000D
  47. #define cfgPM4_WRPTR_0 0x000E
  48. #define cfgPM4_WRPTR_1 0x000F
  49. /* Block CIF End: */
  50. /* Block CP Start: */
  51. #define mmSCRATCH_UMSK 0x0280
  52. #define mmSCRATCH_ADDR 0x0284
  53. #define mmGEN_INT_CNTL 0x0200
  54. #define mmGEN_INT_STATUS 0x0204
  55. /* Block CP End: */
  56. /* Block DISPLAY Start: */
  57. #define mmLCD_FORMAT 0x0410
  58. #define mmGRAPHIC_CTRL 0x0414
  59. #define mmGRAPHIC_OFFSET 0x0418
  60. #define mmGRAPHIC_PITCH 0x041C
  61. #define mmCRTC_TOTAL 0x0420
  62. #define mmACTIVE_H_DISP 0x0424
  63. #define mmACTIVE_V_DISP 0x0428
  64. #define mmGRAPHIC_H_DISP 0x042C
  65. #define mmGRAPHIC_V_DISP 0x0430
  66. #define mmVIDEO_CTRL 0x0434
  67. #define mmGRAPHIC_KEY 0x0438
  68. #define mmBRIGHTNESS_CNTL 0x045C
  69. #define mmDISP_INT_CNTL 0x0488
  70. #define mmCRTC_SS 0x048C
  71. #define mmCRTC_LS 0x0490
  72. #define mmCRTC_REV 0x0494
  73. #define mmCRTC_DCLK 0x049C
  74. #define mmCRTC_GS 0x04A0
  75. #define mmCRTC_VPOS_GS 0x04A4
  76. #define mmCRTC_GCLK 0x04A8
  77. #define mmCRTC_GOE 0x04AC
  78. #define mmCRTC_FRAME 0x04B0
  79. #define mmCRTC_FRAME_VPOS 0x04B4
  80. #define mmGPIO_DATA 0x04B8
  81. #define mmGPIO_CNTL1 0x04BC
  82. #define mmGPIO_CNTL2 0x04C0
  83. #define mmLCDD_CNTL1 0x04C4
  84. #define mmLCDD_CNTL2 0x04C8
  85. #define mmGENLCD_CNTL1 0x04CC
  86. #define mmGENLCD_CNTL2 0x04D0
  87. #define mmDISP_DEBUG 0x04D4
  88. #define mmDISP_DB_BUF_CNTL 0x04D8
  89. #define mmDISP_CRC_SIG 0x04DC
  90. #define mmCRTC_DEFAULT_COUNT 0x04E0
  91. #define mmLCD_BACKGROUND_COLOR 0x04E4
  92. #define mmCRTC_PS2 0x04E8
  93. #define mmCRTC_PS2_VPOS 0x04EC
  94. #define mmCRTC_PS1_ACTIVE 0x04F0
  95. #define mmCRTC_PS1_NACTIVE 0x04F4
  96. #define mmCRTC_GCLK_EXT 0x04F8
  97. #define mmCRTC_ALW 0x04FC
  98. #define mmCRTC_ALW_VPOS 0x0500
  99. #define mmCRTC_PSK 0x0504
  100. #define mmCRTC_PSK_HPOS 0x0508
  101. #define mmCRTC_CV4_START 0x050C
  102. #define mmCRTC_CV4_END 0x0510
  103. #define mmCRTC_CV4_HPOS 0x0514
  104. #define mmCRTC_ECK 0x051C
  105. #define mmREFRESH_CNTL 0x0520
  106. #define mmGENLCD_CNTL3 0x0524
  107. #define mmGPIO_DATA2 0x0528
  108. #define mmGPIO_CNTL3 0x052C
  109. #define mmGPIO_CNTL4 0x0530
  110. #define mmCHIP_STRAP 0x0534
  111. #define mmDISP_DEBUG2 0x0538
  112. #define mmDEBUG_BUS_CNTL 0x053C
  113. #define mmGAMMA_VALUE1 0x0540
  114. #define mmGAMMA_VALUE2 0x0544
  115. #define mmGAMMA_SLOPE 0x0548
  116. #define mmGEN_STATUS 0x054C
  117. #define mmHW_INT 0x0550
  118. /* Block DISPLAY End: */
  119. /* Block GFX Start: */
  120. #define mmDST_OFFSET 0x1004
  121. #define mmDST_PITCH 0x1008
  122. #define mmDST_Y_X 0x1038
  123. #define mmDST_WIDTH_HEIGHT 0x1198
  124. #define mmDP_GUI_MASTER_CNTL 0x106C
  125. #define mmBRUSH_OFFSET 0x108C
  126. #define mmBRUSH_Y_X 0x1074
  127. #define mmDP_BRUSH_FRGD_CLR 0x107C
  128. #define mmSRC_OFFSET 0x11AC
  129. #define mmSRC_PITCH 0x11B0
  130. #define mmSRC_Y_X 0x1034
  131. #define mmDEFAULT_PITCH_OFFSET 0x10A0
  132. #define mmDEFAULT_SC_BOTTOM_RIGHT 0x10A8
  133. #define mmDEFAULT2_SC_BOTTOM_RIGHT 0x10AC
  134. #define mmSC_TOP_LEFT 0x11BC
  135. #define mmSC_BOTTOM_RIGHT 0x11C0
  136. #define mmSRC_SC_BOTTOM_RIGHT 0x11C4
  137. #define mmGLOBAL_ALPHA 0x1210
  138. #define mmFILTER_COEF 0x1214
  139. #define mmMVC_CNTL_START 0x11E0
  140. #define mmE2_ARITHMETIC_CNTL 0x1220
  141. #define mmDP_CNTL 0x11C8
  142. #define mmDP_CNTL_DST_DIR 0x11CC
  143. #define mmDP_DATATYPE 0x12C4
  144. #define mmDP_MIX 0x12C8
  145. #define mmDP_WRITE_MSK 0x12CC
  146. #define mmENG_CNTL 0x13E8
  147. #define mmENG_PERF_CNT 0x13F0
  148. /* Block GFX End: */
  149. /* Block IDCT Start: */
  150. #define mmIDCT_RUNS 0x0C00
  151. #define mmIDCT_LEVELS 0x0C04
  152. #define mmIDCT_CONTROL 0x0C3C
  153. #define mmIDCT_AUTH_CONTROL 0x0C08
  154. #define mmIDCT_AUTH 0x0C0C
  155. /* Block IDCT End: */
  156. /* Block MC Start: */
  157. #define mmMEM_CNTL 0x0180
  158. #define mmMEM_ARB 0x0184
  159. #define mmMC_FB_LOCATION 0x0188
  160. #define mmMEM_EXT_CNTL 0x018C
  161. #define mmMC_EXT_MEM_LOCATION 0x0190
  162. #define mmMEM_EXT_TIMING_CNTL 0x0194
  163. #define mmMEM_SDRAM_MODE_REG 0x0198
  164. #define mmMEM_IO_CNTL 0x019C
  165. #define mmMC_DEBUG 0x01A0
  166. #define mmMC_BIST_CTRL 0x01A4
  167. #define mmMC_BIST_COLLAR_READ 0x01A8
  168. #define mmTC_MISMATCH 0x01AC
  169. #define mmMC_PERF_MON_CNTL 0x01B0
  170. #define mmMC_PERF_COUNTERS 0x01B4
  171. /* Block MC End: */
  172. /* Block BM Start: */
  173. #define mmBM_EXT_MEM_BANDWIDTH 0x0A00
  174. #define mmBM_OFFSET 0x0A04
  175. #define mmBM_MEM_EXT_TIMING_CNTL 0x0A08
  176. #define mmBM_MEM_EXT_CNTL 0x0A0C
  177. #define mmBM_MEM_MODE_REG 0x0A10
  178. #define mmBM_MEM_IO_CNTL 0x0A18
  179. #define mmBM_CONFIG 0x0A1C
  180. #define mmBM_STATUS 0x0A20
  181. #define mmBM_DEBUG 0x0A24
  182. #define mmBM_PERF_MON_CNTL 0x0A28
  183. #define mmBM_PERF_COUNTERS 0x0A2C
  184. #define mmBM_PERF2_MON_CNTL 0x0A30
  185. #define mmBM_PERF2_COUNTERS 0x0A34
  186. /* Block BM End: */
  187. /* Block RBBM Start: */
  188. #define mmWAIT_UNTIL 0x1400
  189. #define mmISYNC_CNTL 0x1404
  190. #define mmRBBM_STATUS 0x0140
  191. #define mmRBBM_CNTL 0x0144
  192. #define mmNQWAIT_UNTIL 0x0150
  193. /* Block RBBM End: */
  194. /* Block CG Start: */
  195. #define mmCLK_PIN_CNTL 0x0080
  196. #define mmPLL_REF_FB_DIV 0x0084
  197. #define mmPLL_CNTL 0x0088
  198. #define mmSCLK_CNTL 0x008C
  199. #define mmPCLK_CNTL 0x0090
  200. #define mmCLK_TEST_CNTL 0x0094
  201. #define mmPWRMGT_CNTL 0x0098
  202. #define mmPWRMGT_STATUS 0x009C
  203. /* Block CG End: */
  204. /* default value definitions */
  205. #define defWRAP_TOP_DIR 0x00000000
  206. #define defWRAP_START_DIR 0x00000000
  207. #define defCFGREG_BASE 0x00000000
  208. #define defCIF_IO 0x000C0902
  209. #define defINTF_CNTL 0x00000011
  210. #define defCPU_DEFAULTS 0x00000006
  211. #define defHW_INT 0x00000000
  212. #define defMC_EXT_MEM_LOCATION 0x07ff0000
  213. #define defTC_MISMATCH 0x00000000
  214. #define W100_CFG_BASE 0x0
  215. #define W100_CFG_LEN 0x10
  216. #define W100_REG_BASE 0x10000
  217. #define W100_REG_LEN 0x2000
  218. #define MEM_INT_BASE_VALUE 0x100000
  219. #define MEM_EXT_BASE_VALUE 0x800000
  220. #define MEM_INT_SIZE 0x05ffff
  221. #define MEM_WINDOW_BASE 0x100000
  222. #define MEM_WINDOW_SIZE 0xf00000
  223. #define WRAP_BUF_BASE_VALUE 0x80000
  224. #define WRAP_BUF_TOP_VALUE 0xbffff
  225. #define CHIP_ID_W100 0x57411002
  226. #define CHIP_ID_W3200 0x56441002
  227. #define CHIP_ID_W3220 0x57441002
  228. /* Register structure definitions */
  229. struct wrap_top_dir_t {
  230. u32 top_addr : 23;
  231. u32 : 9;
  232. } __attribute__((packed));
  233. union wrap_top_dir_u {
  234. u32 val : 32;
  235. struct wrap_top_dir_t f;
  236. } __attribute__((packed));
  237. struct wrap_start_dir_t {
  238. u32 start_addr : 23;
  239. u32 : 9;
  240. } __attribute__((packed));
  241. union wrap_start_dir_u {
  242. u32 val : 32;
  243. struct wrap_start_dir_t f;
  244. } __attribute__((packed));
  245. struct cif_cntl_t {
  246. u32 swap_reg : 2;
  247. u32 swap_fbuf_1 : 2;
  248. u32 swap_fbuf_2 : 2;
  249. u32 swap_fbuf_3 : 2;
  250. u32 pmi_int_disable : 1;
  251. u32 pmi_schmen_disable : 1;
  252. u32 intb_oe : 1;
  253. u32 en_wait_to_compensate_dq_prop_dly : 1;
  254. u32 compensate_wait_rd_size : 2;
  255. u32 wait_asserted_timeout_val : 2;
  256. u32 wait_masked_val : 2;
  257. u32 en_wait_timeout : 1;
  258. u32 en_one_clk_setup_before_wait : 1;
  259. u32 interrupt_active_high : 1;
  260. u32 en_overwrite_straps : 1;
  261. u32 strap_wait_active_hi : 1;
  262. u32 lat_busy_count : 2;
  263. u32 lat_rd_pm4_sclk_busy : 1;
  264. u32 dis_system_bits : 1;
  265. u32 dis_mr : 1;
  266. u32 cif_spare_1 : 4;
  267. } __attribute__((packed));
  268. union cif_cntl_u {
  269. u32 val : 32;
  270. struct cif_cntl_t f;
  271. } __attribute__((packed));
  272. struct cfgreg_base_t {
  273. u32 cfgreg_base : 24;
  274. u32 : 8;
  275. } __attribute__((packed));
  276. union cfgreg_base_u {
  277. u32 val : 32;
  278. struct cfgreg_base_t f;
  279. } __attribute__((packed));
  280. struct cif_io_t {
  281. u32 dq_srp : 1;
  282. u32 dq_srn : 1;
  283. u32 dq_sp : 4;
  284. u32 dq_sn : 4;
  285. u32 waitb_srp : 1;
  286. u32 waitb_srn : 1;
  287. u32 waitb_sp : 4;
  288. u32 waitb_sn : 4;
  289. u32 intb_srp : 1;
  290. u32 intb_srn : 1;
  291. u32 intb_sp : 4;
  292. u32 intb_sn : 4;
  293. u32 : 2;
  294. } __attribute__((packed));
  295. union cif_io_u {
  296. u32 val : 32;
  297. struct cif_io_t f;
  298. } __attribute__((packed));
  299. struct cif_read_dbg_t {
  300. u32 unpacker_pre_fetch_trig_gen : 2;
  301. u32 dly_second_rd_fetch_trig : 1;
  302. u32 rst_rd_burst_id : 1;
  303. u32 dis_rd_burst_id : 1;
  304. u32 en_block_rd_when_packer_is_not_emp : 1;
  305. u32 dis_pre_fetch_cntl_sm : 1;
  306. u32 rbbm_chrncy_dis : 1;
  307. u32 rbbm_rd_after_wr_lat : 2;
  308. u32 dis_be_during_rd : 1;
  309. u32 one_clk_invalidate_pulse : 1;
  310. u32 dis_chnl_priority : 1;
  311. u32 rst_read_path_a_pls : 1;
  312. u32 rst_read_path_b_pls : 1;
  313. u32 dis_reg_rd_fetch_trig : 1;
  314. u32 dis_rd_fetch_trig_from_ind_addr : 1;
  315. u32 dis_rd_same_byte_to_trig_fetch : 1;
  316. u32 dis_dir_wrap : 1;
  317. u32 dis_ring_buf_to_force_dec : 1;
  318. u32 dis_addr_comp_in_16bit : 1;
  319. u32 clr_w : 1;
  320. u32 err_rd_tag_is_3 : 1;
  321. u32 err_load_when_ful_a : 1;
  322. u32 err_load_when_ful_b : 1;
  323. u32 : 7;
  324. } __attribute__((packed));
  325. union cif_read_dbg_u {
  326. u32 val : 32;
  327. struct cif_read_dbg_t f;
  328. } __attribute__((packed));
  329. struct cif_write_dbg_t {
  330. u32 packer_timeout_count : 2;
  331. u32 en_upper_load_cond : 1;
  332. u32 en_chnl_change_cond : 1;
  333. u32 dis_addr_comp_cond : 1;
  334. u32 dis_load_same_byte_addr_cond : 1;
  335. u32 dis_timeout_cond : 1;
  336. u32 dis_timeout_during_rbbm : 1;
  337. u32 dis_packer_ful_during_rbbm_timeout : 1;
  338. u32 en_dword_split_to_rbbm : 1;
  339. u32 en_dummy_val : 1;
  340. u32 dummy_val_sel : 1;
  341. u32 mask_pm4_wrptr_dec : 1;
  342. u32 dis_mc_clean_cond : 1;
  343. u32 err_two_reqi_during_ful : 1;
  344. u32 err_reqi_during_idle_clk : 1;
  345. u32 err_global : 1;
  346. u32 en_wr_buf_dbg_load : 1;
  347. u32 en_wr_buf_dbg_path : 1;
  348. u32 sel_wr_buf_byte : 3;
  349. u32 dis_rd_flush_wr : 1;
  350. u32 dis_packer_ful_cond : 1;
  351. u32 dis_invalidate_by_ops_chnl : 1;
  352. u32 en_halt_when_reqi_err : 1;
  353. u32 cif_spare_2 : 5;
  354. u32 : 1;
  355. } __attribute__((packed));
  356. union cif_write_dbg_u {
  357. u32 val : 32;
  358. struct cif_write_dbg_t f;
  359. } __attribute__((packed));
  360. struct intf_cntl_t {
  361. unsigned char ad_inc_a : 1;
  362. unsigned char ring_buf_a : 1;
  363. unsigned char rd_fetch_trigger_a : 1;
  364. unsigned char rd_data_rdy_a : 1;
  365. unsigned char ad_inc_b : 1;
  366. unsigned char ring_buf_b : 1;
  367. unsigned char rd_fetch_trigger_b : 1;
  368. unsigned char rd_data_rdy_b : 1;
  369. } __attribute__((packed));
  370. union intf_cntl_u {
  371. unsigned char val : 8;
  372. struct intf_cntl_t f;
  373. } __attribute__((packed));
  374. struct cpu_defaults_t {
  375. unsigned char unpack_rd_data : 1;
  376. unsigned char access_ind_addr_a : 1;
  377. unsigned char access_ind_addr_b : 1;
  378. unsigned char access_scratch_reg : 1;
  379. unsigned char pack_wr_data : 1;
  380. unsigned char transition_size : 1;
  381. unsigned char en_read_buf_mode : 1;
  382. unsigned char rd_fetch_scratch : 1;
  383. } __attribute__((packed));
  384. union cpu_defaults_u {
  385. unsigned char val : 8;
  386. struct cpu_defaults_t f;
  387. } __attribute__((packed));
  388. struct crtc_total_t {
  389. u32 crtc_h_total : 10;
  390. u32 : 6;
  391. u32 crtc_v_total : 10;
  392. u32 : 6;
  393. } __attribute__((packed));
  394. union crtc_total_u {
  395. u32 val : 32;
  396. struct crtc_total_t f;
  397. } __attribute__((packed));
  398. struct crtc_ss_t {
  399. u32 ss_start : 10;
  400. u32 : 6;
  401. u32 ss_end : 10;
  402. u32 : 2;
  403. u32 ss_align : 1;
  404. u32 ss_pol : 1;
  405. u32 ss_run_mode : 1;
  406. u32 ss_en : 1;
  407. } __attribute__((packed));
  408. union crtc_ss_u {
  409. u32 val : 32;
  410. struct crtc_ss_t f;
  411. } __attribute__((packed));
  412. struct active_h_disp_t {
  413. u32 active_h_start : 10;
  414. u32 : 6;
  415. u32 active_h_end : 10;
  416. u32 : 6;
  417. } __attribute__((packed));
  418. union active_h_disp_u {
  419. u32 val : 32;
  420. struct active_h_disp_t f;
  421. } __attribute__((packed));
  422. struct active_v_disp_t {
  423. u32 active_v_start : 10;
  424. u32 : 6;
  425. u32 active_v_end : 10;
  426. u32 : 6;
  427. } __attribute__((packed));
  428. union active_v_disp_u {
  429. u32 val : 32;
  430. struct active_v_disp_t f;
  431. } __attribute__((packed));
  432. struct graphic_h_disp_t {
  433. u32 graphic_h_start : 10;
  434. u32 : 6;
  435. u32 graphic_h_end : 10;
  436. u32 : 6;
  437. } __attribute__((packed));
  438. union graphic_h_disp_u {
  439. u32 val : 32;
  440. struct graphic_h_disp_t f;
  441. } __attribute__((packed));
  442. struct graphic_v_disp_t {
  443. u32 graphic_v_start : 10;
  444. u32 : 6;
  445. u32 graphic_v_end : 10;
  446. u32 : 6;
  447. } __attribute__((packed));
  448. union graphic_v_disp_u{
  449. u32 val : 32;
  450. struct graphic_v_disp_t f;
  451. } __attribute__((packed));
  452. struct graphic_ctrl_t_w100 {
  453. u32 color_depth : 3;
  454. u32 portrait_mode : 2;
  455. u32 low_power_on : 1;
  456. u32 req_freq : 4;
  457. u32 en_crtc : 1;
  458. u32 en_graphic_req : 1;
  459. u32 en_graphic_crtc : 1;
  460. u32 total_req_graphic : 9;
  461. u32 lcd_pclk_on : 1;
  462. u32 lcd_sclk_on : 1;
  463. u32 pclk_running : 1;
  464. u32 sclk_running : 1;
  465. u32 : 6;
  466. } __attribute__((packed));
  467. struct graphic_ctrl_t_w32xx {
  468. u32 color_depth : 3;
  469. u32 portrait_mode : 2;
  470. u32 low_power_on : 1;
  471. u32 req_freq : 4;
  472. u32 en_crtc : 1;
  473. u32 en_graphic_req : 1;
  474. u32 en_graphic_crtc : 1;
  475. u32 total_req_graphic : 10;
  476. u32 lcd_pclk_on : 1;
  477. u32 lcd_sclk_on : 1;
  478. u32 pclk_running : 1;
  479. u32 sclk_running : 1;
  480. u32 : 5;
  481. } __attribute__((packed));
  482. union graphic_ctrl_u {
  483. u32 val : 32;
  484. struct graphic_ctrl_t_w100 f_w100;
  485. struct graphic_ctrl_t_w32xx f_w32xx;
  486. } __attribute__((packed));
  487. struct video_ctrl_t {
  488. u32 video_mode : 1;
  489. u32 keyer_en : 1;
  490. u32 en_video_req : 1;
  491. u32 en_graphic_req_video : 1;
  492. u32 en_video_crtc : 1;
  493. u32 video_hor_exp : 2;
  494. u32 video_ver_exp : 2;
  495. u32 uv_combine : 1;
  496. u32 total_req_video : 9;
  497. u32 video_ch_sel : 1;
  498. u32 video_portrait : 2;
  499. u32 yuv2rgb_en : 1;
  500. u32 yuv2rgb_option : 1;
  501. u32 video_inv_hor : 1;
  502. u32 video_inv_ver : 1;
  503. u32 gamma_sel : 2;
  504. u32 dis_limit : 1;
  505. u32 en_uv_hblend : 1;
  506. u32 rgb_gamma_sel : 2;
  507. } __attribute__((packed));
  508. union video_ctrl_u {
  509. u32 val : 32;
  510. struct video_ctrl_t f;
  511. } __attribute__((packed));
  512. struct disp_db_buf_cntl_rd_t {
  513. u32 en_db_buf : 1;
  514. u32 update_db_buf_done : 1;
  515. u32 db_buf_cntl : 6;
  516. u32 : 24;
  517. } __attribute__((packed));
  518. union disp_db_buf_cntl_rd_u {
  519. u32 val : 32;
  520. struct disp_db_buf_cntl_rd_t f;
  521. } __attribute__((packed));
  522. struct disp_db_buf_cntl_wr_t {
  523. u32 en_db_buf : 1;
  524. u32 update_db_buf : 1;
  525. u32 db_buf_cntl : 6;
  526. u32 : 24;
  527. } __attribute__((packed));
  528. union disp_db_buf_cntl_wr_u {
  529. u32 val : 32;
  530. struct disp_db_buf_cntl_wr_t f;
  531. } __attribute__((packed));
  532. struct gamma_value1_t {
  533. u32 gamma1 : 8;
  534. u32 gamma2 : 8;
  535. u32 gamma3 : 8;
  536. u32 gamma4 : 8;
  537. } __attribute__((packed));
  538. union gamma_value1_u {
  539. u32 val : 32;
  540. struct gamma_value1_t f;
  541. } __attribute__((packed));
  542. struct gamma_value2_t {
  543. u32 gamma5 : 8;
  544. u32 gamma6 : 8;
  545. u32 gamma7 : 8;
  546. u32 gamma8 : 8;
  547. } __attribute__((packed));
  548. union gamma_value2_u {
  549. u32 val : 32;
  550. struct gamma_value2_t f;
  551. } __attribute__((packed));
  552. struct gamma_slope_t {
  553. u32 slope1 : 3;
  554. u32 slope2 : 3;
  555. u32 slope3 : 3;
  556. u32 slope4 : 3;
  557. u32 slope5 : 3;
  558. u32 slope6 : 3;
  559. u32 slope7 : 3;
  560. u32 slope8 : 3;
  561. u32 : 8;
  562. } __attribute__((packed));
  563. union gamma_slope_u {
  564. u32 val : 32;
  565. struct gamma_slope_t f;
  566. } __attribute__((packed));
  567. struct mc_ext_mem_location_t {
  568. u32 mc_ext_mem_start : 16;
  569. u32 mc_ext_mem_top : 16;
  570. } __attribute__((packed));
  571. union mc_ext_mem_location_u {
  572. u32 val : 32;
  573. struct mc_ext_mem_location_t f;
  574. } __attribute__((packed));
  575. struct mc_fb_location_t {
  576. u32 mc_fb_start : 16;
  577. u32 mc_fb_top : 16;
  578. } __attribute__((packed));
  579. union mc_fb_location_u {
  580. u32 val : 32;
  581. struct mc_fb_location_t f;
  582. } __attribute__((packed));
  583. struct clk_pin_cntl_t {
  584. u32 osc_en : 1;
  585. u32 osc_gain : 5;
  586. u32 dont_use_xtalin : 1;
  587. u32 xtalin_pm_en : 1;
  588. u32 xtalin_dbl_en : 1;
  589. u32 : 7;
  590. u32 cg_debug : 16;
  591. } __attribute__((packed));
  592. union clk_pin_cntl_u {
  593. u32 val : 32;
  594. struct clk_pin_cntl_t f;
  595. } __attribute__((packed));
  596. struct pll_ref_fb_div_t {
  597. u32 pll_ref_div : 4;
  598. u32 : 4;
  599. u32 pll_fb_div_int : 6;
  600. u32 : 2;
  601. u32 pll_fb_div_frac : 3;
  602. u32 : 1;
  603. u32 pll_reset_time : 4;
  604. u32 pll_lock_time : 8;
  605. } __attribute__((packed));
  606. union pll_ref_fb_div_u {
  607. u32 val : 32;
  608. struct pll_ref_fb_div_t f;
  609. } __attribute__((packed));
  610. struct pll_cntl_t {
  611. u32 pll_pwdn : 1;
  612. u32 pll_reset : 1;
  613. u32 pll_pm_en : 1;
  614. u32 pll_mode : 1;
  615. u32 pll_refclk_sel : 1;
  616. u32 pll_fbclk_sel : 1;
  617. u32 pll_tcpoff : 1;
  618. u32 pll_pcp : 3;
  619. u32 pll_pvg : 3;
  620. u32 pll_vcofr : 1;
  621. u32 pll_ioffset : 2;
  622. u32 pll_pecc_mode : 2;
  623. u32 pll_pecc_scon : 2;
  624. u32 pll_dactal : 4;
  625. u32 pll_cp_clip : 2;
  626. u32 pll_conf : 3;
  627. u32 pll_mbctrl : 2;
  628. u32 pll_ring_off : 1;
  629. } __attribute__((packed));
  630. union pll_cntl_u {
  631. u32 val : 32;
  632. struct pll_cntl_t f;
  633. } __attribute__((packed));
  634. struct sclk_cntl_t {
  635. u32 sclk_src_sel : 2;
  636. u32 : 2;
  637. u32 sclk_post_div_fast : 4;
  638. u32 sclk_clkon_hys : 3;
  639. u32 sclk_post_div_slow : 4;
  640. u32 disp_cg_ok2switch_en : 1;
  641. u32 sclk_force_reg : 1;
  642. u32 sclk_force_disp : 1;
  643. u32 sclk_force_mc : 1;
  644. u32 sclk_force_extmc : 1;
  645. u32 sclk_force_cp : 1;
  646. u32 sclk_force_e2 : 1;
  647. u32 sclk_force_e3 : 1;
  648. u32 sclk_force_idct : 1;
  649. u32 sclk_force_bist : 1;
  650. u32 busy_extend_cp : 1;
  651. u32 busy_extend_e2 : 1;
  652. u32 busy_extend_e3 : 1;
  653. u32 busy_extend_idct : 1;
  654. u32 : 3;
  655. } __attribute__((packed));
  656. union sclk_cntl_u {
  657. u32 val : 32;
  658. struct sclk_cntl_t f;
  659. } __attribute__((packed));
  660. struct pclk_cntl_t {
  661. u32 pclk_src_sel : 2;
  662. u32 : 2;
  663. u32 pclk_post_div : 4;
  664. u32 : 8;
  665. u32 pclk_force_disp : 1;
  666. u32 : 15;
  667. } __attribute__((packed));
  668. union pclk_cntl_u {
  669. u32 val : 32;
  670. struct pclk_cntl_t f;
  671. } __attribute__((packed));
  672. #define TESTCLK_SRC_PLL 0x01
  673. #define TESTCLK_SRC_SCLK 0x02
  674. #define TESTCLK_SRC_PCLK 0x03
  675. /* 4 and 5 seem to by XTAL/M */
  676. #define TESTCLK_SRC_XTAL 0x06
  677. struct clk_test_cntl_t {
  678. u32 testclk_sel : 4;
  679. u32 : 3;
  680. u32 start_check_freq : 1;
  681. u32 tstcount_rst : 1;
  682. u32 : 15;
  683. u32 test_count : 8;
  684. } __attribute__((packed));
  685. union clk_test_cntl_u {
  686. u32 val : 32;
  687. struct clk_test_cntl_t f;
  688. } __attribute__((packed));
  689. struct pwrmgt_cntl_t {
  690. u32 pwm_enable : 1;
  691. u32 : 1;
  692. u32 pwm_mode_req : 2;
  693. u32 pwm_wakeup_cond : 2;
  694. u32 pwm_fast_noml_hw_en : 1;
  695. u32 pwm_noml_fast_hw_en : 1;
  696. u32 pwm_fast_noml_cond : 4;
  697. u32 pwm_noml_fast_cond : 4;
  698. u32 pwm_idle_timer : 8;
  699. u32 pwm_busy_timer : 8;
  700. } __attribute__((packed));
  701. union pwrmgt_cntl_u {
  702. u32 val : 32;
  703. struct pwrmgt_cntl_t f;
  704. } __attribute__((packed));
  705. #define SRC_DATATYPE_EQU_DST 3
  706. #define ROP3_SRCCOPY 0xcc
  707. #define ROP3_PATCOPY 0xf0
  708. #define GMC_BRUSH_SOLID_COLOR 13
  709. #define GMC_BRUSH_NONE 15
  710. #define DP_SRC_MEM_RECTANGULAR 2
  711. #define DP_OP_ROP 0
  712. struct dp_gui_master_cntl_t {
  713. u32 gmc_src_pitch_offset_cntl : 1;
  714. u32 gmc_dst_pitch_offset_cntl : 1;
  715. u32 gmc_src_clipping : 1;
  716. u32 gmc_dst_clipping : 1;
  717. u32 gmc_brush_datatype : 4;
  718. u32 gmc_dst_datatype : 4;
  719. u32 gmc_src_datatype : 3;
  720. u32 gmc_byte_pix_order : 1;
  721. u32 gmc_default_sel : 1;
  722. u32 gmc_rop3 : 8;
  723. u32 gmc_dp_src_source : 3;
  724. u32 gmc_clr_cmp_fcn_dis : 1;
  725. u32 : 1;
  726. u32 gmc_wr_msk_dis : 1;
  727. u32 gmc_dp_op : 1;
  728. } __attribute__((packed));
  729. union dp_gui_master_cntl_u {
  730. u32 val : 32;
  731. struct dp_gui_master_cntl_t f;
  732. } __attribute__((packed));
  733. struct rbbm_status_t {
  734. u32 cmdfifo_avail : 7;
  735. u32 : 1;
  736. u32 hirq_on_rbb : 1;
  737. u32 cprq_on_rbb : 1;
  738. u32 cfrq_on_rbb : 1;
  739. u32 hirq_in_rtbuf : 1;
  740. u32 cprq_in_rtbuf : 1;
  741. u32 cfrq_in_rtbuf : 1;
  742. u32 cf_pipe_busy : 1;
  743. u32 eng_ev_busy : 1;
  744. u32 cp_cmdstrm_busy : 1;
  745. u32 e2_busy : 1;
  746. u32 rb2d_busy : 1;
  747. u32 rb3d_busy : 1;
  748. u32 se_busy : 1;
  749. u32 re_busy : 1;
  750. u32 tam_busy : 1;
  751. u32 tdm_busy : 1;
  752. u32 pb_busy : 1;
  753. u32 : 6;
  754. u32 gui_active : 1;
  755. } __attribute__((packed));
  756. union rbbm_status_u {
  757. u32 val : 32;
  758. struct rbbm_status_t f;
  759. } __attribute__((packed));
  760. struct dp_datatype_t {
  761. u32 dp_dst_datatype : 4;
  762. u32 : 4;
  763. u32 dp_brush_datatype : 4;
  764. u32 dp_src2_type : 1;
  765. u32 dp_src2_datatype : 3;
  766. u32 dp_src_datatype : 3;
  767. u32 : 11;
  768. u32 dp_byte_pix_order : 1;
  769. u32 : 1;
  770. } __attribute__((packed));
  771. union dp_datatype_u {
  772. u32 val : 32;
  773. struct dp_datatype_t f;
  774. } __attribute__((packed));
  775. struct dp_mix_t {
  776. u32 : 8;
  777. u32 dp_src_source : 3;
  778. u32 dp_src2_source : 3;
  779. u32 : 2;
  780. u32 dp_rop3 : 8;
  781. u32 dp_op : 1;
  782. u32 : 7;
  783. } __attribute__((packed));
  784. union dp_mix_u {
  785. u32 val : 32;
  786. struct dp_mix_t f;
  787. } __attribute__((packed));
  788. struct eng_cntl_t {
  789. u32 erc_reg_rd_ws : 1;
  790. u32 erc_reg_wr_ws : 1;
  791. u32 erc_idle_reg_wr : 1;
  792. u32 dis_engine_triggers : 1;
  793. u32 dis_rop_src_uses_dst_w_h : 1;
  794. u32 dis_src_uses_dst_dirmaj : 1;
  795. u32 : 6;
  796. u32 force_3dclk_when_2dclk : 1;
  797. u32 : 19;
  798. } __attribute__((packed));
  799. union eng_cntl_u {
  800. u32 val : 32;
  801. struct eng_cntl_t f;
  802. } __attribute__((packed));
  803. struct dp_cntl_t {
  804. u32 dst_x_dir : 1;
  805. u32 dst_y_dir : 1;
  806. u32 src_x_dir : 1;
  807. u32 src_y_dir : 1;
  808. u32 dst_major_x : 1;
  809. u32 src_major_x : 1;
  810. u32 : 26;
  811. } __attribute__((packed));
  812. union dp_cntl_u {
  813. u32 val : 32;
  814. struct dp_cntl_t f;
  815. } __attribute__((packed));
  816. struct dp_cntl_dst_dir_t {
  817. u32 : 15;
  818. u32 dst_y_dir : 1;
  819. u32 : 15;
  820. u32 dst_x_dir : 1;
  821. } __attribute__((packed));
  822. union dp_cntl_dst_dir_u {
  823. u32 val : 32;
  824. struct dp_cntl_dst_dir_t f;
  825. } __attribute__((packed));
  826. #endif