tdfxfb.c 38 KB

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  1. /*
  2. *
  3. * tdfxfb.c
  4. *
  5. * Author: Hannu Mallat <hmallat@cc.hut.fi>
  6. *
  7. * Copyright © 1999 Hannu Mallat
  8. * All rights reserved
  9. *
  10. * Created : Thu Sep 23 18:17:43 1999, hmallat
  11. * Last modified: Tue Nov 2 21:19:47 1999, hmallat
  12. *
  13. * Lots of the information here comes from the Daryll Strauss' Banshee
  14. * patches to the XF86 server, and the rest comes from the 3dfx
  15. * Banshee specification. I'm very much indebted to Daryll for his
  16. * work on the X server.
  17. *
  18. * Voodoo3 support was contributed Harold Oga. Lots of additions
  19. * (proper acceleration, 24 bpp, hardware cursor) and bug fixes by Attila
  20. * Kesmarki. Thanks guys!
  21. *
  22. * Voodoo1 and Voodoo2 support aren't relevant to this driver as they
  23. * behave very differently from the Voodoo3/4/5. For anyone wanting to
  24. * use frame buffer on the Voodoo1/2, see the sstfb driver (which is
  25. * located at http://www.sourceforge.net/projects/sstfb).
  26. *
  27. * While I _am_ grateful to 3Dfx for releasing the specs for Banshee,
  28. * I do wish the next version is a bit more complete. Without the XF86
  29. * patches I couldn't have gotten even this far... for instance, the
  30. * extensions to the VGA register set go completely unmentioned in the
  31. * spec! Also, lots of references are made to the 'SST core', but no
  32. * spec is publicly available, AFAIK.
  33. *
  34. * The structure of this driver comes pretty much from the Permedia
  35. * driver by Ilario Nardinocchi, which in turn is based on skeletonfb.
  36. *
  37. * TODO:
  38. * - support for 16/32 bpp needs fixing (funky bootup penguin)
  39. * - multihead support (basically need to support an array of fb_infos)
  40. * - support other architectures (PPC, Alpha); does the fact that the VGA
  41. * core can be accessed only thru I/O (not memory mapped) complicate
  42. * things?
  43. *
  44. * Version history:
  45. *
  46. * 0.1.4 (released 2002-05-28) ported over to new fbdev api by James Simmons
  47. *
  48. * 0.1.3 (released 1999-11-02) added Attila's panning support, code
  49. * reorg, hwcursor address page size alignment
  50. * (for mmaping both frame buffer and regs),
  51. * and my changes to get rid of hardcoded
  52. * VGA i/o register locations (uses PCI
  53. * configuration info now)
  54. * 0.1.2 (released 1999-10-19) added Attila Kesmarki's bug fixes and
  55. * improvements
  56. * 0.1.1 (released 1999-10-07) added Voodoo3 support by Harold Oga.
  57. * 0.1.0 (released 1999-10-06) initial version
  58. *
  59. */
  60. #include <linux/module.h>
  61. #include <linux/kernel.h>
  62. #include <linux/errno.h>
  63. #include <linux/string.h>
  64. #include <linux/mm.h>
  65. #include <linux/slab.h>
  66. #include <linux/delay.h>
  67. #include <linux/interrupt.h>
  68. #include <linux/fb.h>
  69. #include <linux/init.h>
  70. #include <linux/pci.h>
  71. #include <linux/nvram.h>
  72. #include <asm/io.h>
  73. #include <linux/timer.h>
  74. #include <linux/spinlock.h>
  75. #include <video/tdfx.h>
  76. #undef TDFXFB_DEBUG
  77. #ifdef TDFXFB_DEBUG
  78. #define DPRINTK(a,b...) printk(KERN_DEBUG "fb: %s: " a, __FUNCTION__ , ## b)
  79. #else
  80. #define DPRINTK(a,b...)
  81. #endif
  82. #define BANSHEE_MAX_PIXCLOCK 270000
  83. #define VOODOO3_MAX_PIXCLOCK 300000
  84. #define VOODOO5_MAX_PIXCLOCK 350000
  85. static struct fb_fix_screeninfo tdfx_fix __devinitdata = {
  86. .id = "3Dfx",
  87. .type = FB_TYPE_PACKED_PIXELS,
  88. .visual = FB_VISUAL_PSEUDOCOLOR,
  89. .ypanstep = 1,
  90. .ywrapstep = 1,
  91. .accel = FB_ACCEL_3DFX_BANSHEE
  92. };
  93. static struct fb_var_screeninfo tdfx_var __devinitdata = {
  94. /* "640x480, 8 bpp @ 60 Hz */
  95. .xres = 640,
  96. .yres = 480,
  97. .xres_virtual = 640,
  98. .yres_virtual = 1024,
  99. .bits_per_pixel =8,
  100. .red = {0, 8, 0},
  101. .blue = {0, 8, 0},
  102. .green = {0, 8, 0},
  103. .activate = FB_ACTIVATE_NOW,
  104. .height = -1,
  105. .width = -1,
  106. .accel_flags = FB_ACCELF_TEXT,
  107. .pixclock = 39722,
  108. .left_margin = 40,
  109. .right_margin = 24,
  110. .upper_margin = 32,
  111. .lower_margin = 11,
  112. .hsync_len = 96,
  113. .vsync_len = 2,
  114. .vmode = FB_VMODE_NONINTERLACED
  115. };
  116. /*
  117. * PCI driver prototypes
  118. */
  119. static int __devinit tdfxfb_probe(struct pci_dev *pdev,
  120. const struct pci_device_id *id);
  121. static void __devexit tdfxfb_remove(struct pci_dev *pdev);
  122. static struct pci_device_id tdfxfb_id_table[] = {
  123. { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_BANSHEE,
  124. PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
  125. 0xff0000, 0 },
  126. { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO3,
  127. PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
  128. 0xff0000, 0 },
  129. { PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO5,
  130. PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
  131. 0xff0000, 0 },
  132. { 0, }
  133. };
  134. static struct pci_driver tdfxfb_driver = {
  135. .name = "tdfxfb",
  136. .id_table = tdfxfb_id_table,
  137. .probe = tdfxfb_probe,
  138. .remove = __devexit_p(tdfxfb_remove),
  139. };
  140. MODULE_DEVICE_TABLE(pci, tdfxfb_id_table);
  141. /*
  142. * Frame buffer device API
  143. */
  144. static int tdfxfb_check_var(struct fb_var_screeninfo *var, struct fb_info *fb);
  145. static int tdfxfb_set_par(struct fb_info *info);
  146. static int tdfxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  147. u_int transp, struct fb_info *info);
  148. static int tdfxfb_blank(int blank, struct fb_info *info);
  149. static int tdfxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
  150. static int banshee_wait_idle(struct fb_info *info);
  151. #ifdef CONFIG_FB_3DFX_ACCEL
  152. static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
  153. static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
  154. static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image);
  155. #endif /* CONFIG_FB_3DFX_ACCEL */
  156. static struct fb_ops tdfxfb_ops = {
  157. .owner = THIS_MODULE,
  158. .fb_check_var = tdfxfb_check_var,
  159. .fb_set_par = tdfxfb_set_par,
  160. .fb_setcolreg = tdfxfb_setcolreg,
  161. .fb_blank = tdfxfb_blank,
  162. .fb_pan_display = tdfxfb_pan_display,
  163. .fb_sync = banshee_wait_idle,
  164. #ifdef CONFIG_FB_3DFX_ACCEL
  165. .fb_fillrect = tdfxfb_fillrect,
  166. .fb_copyarea = tdfxfb_copyarea,
  167. .fb_imageblit = tdfxfb_imageblit,
  168. #else
  169. .fb_fillrect = cfb_fillrect,
  170. .fb_copyarea = cfb_copyarea,
  171. .fb_imageblit = cfb_imageblit,
  172. #endif
  173. };
  174. /*
  175. * do_xxx: Hardware-specific functions
  176. */
  177. static u32 do_calc_pll(int freq, int *freq_out);
  178. static void do_write_regs(struct fb_info *info, struct banshee_reg *reg);
  179. static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short);
  180. /*
  181. * Driver data
  182. */
  183. static int nopan = 0;
  184. static int nowrap = 1; // not implemented (yet)
  185. static char *mode_option __devinitdata = NULL;
  186. /* -------------------------------------------------------------------------
  187. * Hardware-specific funcions
  188. * ------------------------------------------------------------------------- */
  189. #ifdef VGA_REG_IO
  190. static inline u8 vga_inb(struct tdfx_par *par, u32 reg) { return inb(reg); }
  191. static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) { outb(val, reg); }
  192. #else
  193. static inline u8 vga_inb(struct tdfx_par *par, u32 reg) {
  194. return inb(par->iobase + reg - 0x300);
  195. }
  196. static inline void vga_outb(struct tdfx_par *par, u32 reg, u8 val) {
  197. outb(val, par->iobase + reg - 0x300);
  198. }
  199. #endif
  200. static inline void gra_outb(struct tdfx_par *par, u32 idx, u8 val) {
  201. vga_outb(par, GRA_I, idx); vga_outb(par, GRA_D, val);
  202. }
  203. static inline void seq_outb(struct tdfx_par *par, u32 idx, u8 val) {
  204. vga_outb(par, SEQ_I, idx); vga_outb(par, SEQ_D, val);
  205. }
  206. static inline u8 seq_inb(struct tdfx_par *par, u32 idx) {
  207. vga_outb(par, SEQ_I, idx); return vga_inb(par, SEQ_D);
  208. }
  209. static inline void crt_outb(struct tdfx_par *par, u32 idx, u8 val) {
  210. vga_outb(par, CRT_I, idx); vga_outb(par, CRT_D, val);
  211. }
  212. static inline u8 crt_inb(struct tdfx_par *par, u32 idx) {
  213. vga_outb(par, CRT_I, idx); return vga_inb(par, CRT_D);
  214. }
  215. static inline void att_outb(struct tdfx_par *par, u32 idx, u8 val)
  216. {
  217. unsigned char tmp;
  218. tmp = vga_inb(par, IS1_R);
  219. vga_outb(par, ATT_IW, idx);
  220. vga_outb(par, ATT_IW, val);
  221. }
  222. static inline void vga_disable_video(struct tdfx_par *par)
  223. {
  224. unsigned char s;
  225. s = seq_inb(par, 0x01) | 0x20;
  226. seq_outb(par, 0x00, 0x01);
  227. seq_outb(par, 0x01, s);
  228. seq_outb(par, 0x00, 0x03);
  229. }
  230. static inline void vga_enable_video(struct tdfx_par *par)
  231. {
  232. unsigned char s;
  233. s = seq_inb(par, 0x01) & 0xdf;
  234. seq_outb(par, 0x00, 0x01);
  235. seq_outb(par, 0x01, s);
  236. seq_outb(par, 0x00, 0x03);
  237. }
  238. static inline void vga_enable_palette(struct tdfx_par *par)
  239. {
  240. vga_inb(par, IS1_R);
  241. vga_outb(par, ATT_IW, 0x20);
  242. }
  243. static inline u32 tdfx_inl(struct tdfx_par *par, unsigned int reg)
  244. {
  245. return readl(par->regbase_virt + reg);
  246. }
  247. static inline void tdfx_outl(struct tdfx_par *par, unsigned int reg, u32 val)
  248. {
  249. writel(val, par->regbase_virt + reg);
  250. }
  251. static inline void banshee_make_room(struct tdfx_par *par, int size)
  252. {
  253. /* Note: The Voodoo3's onboard FIFO has 32 slots. This loop
  254. * won't quit if you ask for more. */
  255. while((tdfx_inl(par, STATUS) & 0x1f) < size-1);
  256. }
  257. static int banshee_wait_idle(struct fb_info *info)
  258. {
  259. struct tdfx_par *par = info->par;
  260. int i = 0;
  261. banshee_make_room(par, 1);
  262. tdfx_outl(par, COMMAND_3D, COMMAND_3D_NOP);
  263. while(1) {
  264. i = (tdfx_inl(par, STATUS) & STATUS_BUSY) ? 0 : i + 1;
  265. if(i == 3) break;
  266. }
  267. return 0;
  268. }
  269. /*
  270. * Set the color of a palette entry in 8bpp mode
  271. */
  272. static inline void do_setpalentry(struct tdfx_par *par, unsigned regno, u32 c)
  273. {
  274. banshee_make_room(par, 2);
  275. tdfx_outl(par, DACADDR, regno);
  276. tdfx_outl(par, DACDATA, c);
  277. }
  278. static u32 do_calc_pll(int freq, int* freq_out)
  279. {
  280. int m, n, k, best_m, best_n, best_k, best_error;
  281. int fref = 14318;
  282. best_error = freq;
  283. best_n = best_m = best_k = 0;
  284. for (k = 3; k >= 0; k--) {
  285. for (m = 63; m >= 0; m--) {
  286. /*
  287. * Estimate value of n that produces target frequency
  288. * with current m and k
  289. */
  290. int n_estimated = (freq * (m + 2) * (1 << k) / fref) - 2;
  291. /* Search neighborhood of estimated n */
  292. for (n = max(0, n_estimated - 1);
  293. n <= min(255, n_estimated + 1); n++) {
  294. /*
  295. * Calculate PLL freqency with current m, k and
  296. * estimated n
  297. */
  298. int f = fref * (n + 2) / (m + 2) / (1 << k);
  299. int error = abs (f - freq);
  300. /*
  301. * If this is the closest we've come to the
  302. * target frequency then remember n, m and k
  303. */
  304. if (error < best_error) {
  305. best_error = error;
  306. best_n = n;
  307. best_m = m;
  308. best_k = k;
  309. }
  310. }
  311. }
  312. }
  313. n = best_n;
  314. m = best_m;
  315. k = best_k;
  316. *freq_out = fref*(n + 2)/(m + 2)/(1 << k);
  317. return (n << 8) | (m << 2) | k;
  318. }
  319. static void do_write_regs(struct fb_info *info, struct banshee_reg* reg)
  320. {
  321. struct tdfx_par *par = info->par;
  322. int i;
  323. banshee_wait_idle(info);
  324. tdfx_outl(par, MISCINIT1, tdfx_inl(par, MISCINIT1) | 0x01);
  325. crt_outb(par, 0x11, crt_inb(par, 0x11) & 0x7f); /* CRT unprotect */
  326. banshee_make_room(par, 3);
  327. tdfx_outl(par, VGAINIT1, reg->vgainit1 & 0x001FFFFF);
  328. tdfx_outl(par, VIDPROCCFG, reg->vidcfg & ~0x00000001);
  329. #if 0
  330. tdfx_outl(par, PLLCTRL1, reg->mempll);
  331. tdfx_outl(par, PLLCTRL2, reg->gfxpll);
  332. #endif
  333. tdfx_outl(par, PLLCTRL0, reg->vidpll);
  334. vga_outb(par, MISC_W, reg->misc[0x00] | 0x01);
  335. for (i = 0; i < 5; i++)
  336. seq_outb(par, i, reg->seq[i]);
  337. for (i = 0; i < 25; i++)
  338. crt_outb(par, i, reg->crt[i]);
  339. for (i = 0; i < 9; i++)
  340. gra_outb(par, i, reg->gra[i]);
  341. for (i = 0; i < 21; i++)
  342. att_outb(par, i, reg->att[i]);
  343. crt_outb(par, 0x1a, reg->ext[0]);
  344. crt_outb(par, 0x1b, reg->ext[1]);
  345. vga_enable_palette(par);
  346. vga_enable_video(par);
  347. banshee_make_room(par, 11);
  348. tdfx_outl(par, VGAINIT0, reg->vgainit0);
  349. tdfx_outl(par, DACMODE, reg->dacmode);
  350. tdfx_outl(par, VIDDESKSTRIDE, reg->stride);
  351. tdfx_outl(par, HWCURPATADDR, 0);
  352. tdfx_outl(par, VIDSCREENSIZE,reg->screensize);
  353. tdfx_outl(par, VIDDESKSTART, reg->startaddr);
  354. tdfx_outl(par, VIDPROCCFG, reg->vidcfg);
  355. tdfx_outl(par, VGAINIT1, reg->vgainit1);
  356. tdfx_outl(par, MISCINIT0, reg->miscinit0);
  357. banshee_make_room(par, 8);
  358. tdfx_outl(par, SRCBASE, reg->srcbase);
  359. tdfx_outl(par, DSTBASE, reg->dstbase);
  360. tdfx_outl(par, COMMANDEXTRA_2D, 0);
  361. tdfx_outl(par, CLIP0MIN, 0);
  362. tdfx_outl(par, CLIP0MAX, 0x0fff0fff);
  363. tdfx_outl(par, CLIP1MIN, 0);
  364. tdfx_outl(par, CLIP1MAX, 0x0fff0fff);
  365. tdfx_outl(par, SRCXY, 0);
  366. banshee_wait_idle(info);
  367. }
  368. static unsigned long do_lfb_size(struct tdfx_par *par, unsigned short dev_id)
  369. {
  370. u32 draminit0;
  371. u32 draminit1;
  372. u32 miscinit1;
  373. int num_chips;
  374. int chip_size; /* in MB */
  375. u32 lfbsize;
  376. int has_sgram;
  377. draminit0 = tdfx_inl(par, DRAMINIT0);
  378. draminit1 = tdfx_inl(par, DRAMINIT1);
  379. num_chips = (draminit0 & DRAMINIT0_SGRAM_NUM) ? 8 : 4;
  380. if (dev_id < PCI_DEVICE_ID_3DFX_VOODOO5) {
  381. /* Banshee/Voodoo3 */
  382. has_sgram = draminit1 & DRAMINIT1_MEM_SDRAM;
  383. chip_size = has_sgram ? ((draminit0 & DRAMINIT0_SGRAM_TYPE) ? 2 : 1)
  384. : 2;
  385. } else {
  386. /* Voodoo4/5 */
  387. has_sgram = 0;
  388. chip_size = 1 << ((draminit0 & DRAMINIT0_SGRAM_TYPE_MASK) >> DRAMINIT0_SGRAM_TYPE_SHIFT);
  389. }
  390. lfbsize = num_chips * chip_size * 1024 * 1024;
  391. /* disable block writes for SDRAM */
  392. miscinit1 = tdfx_inl(par, MISCINIT1);
  393. miscinit1 |= has_sgram ? 0 : MISCINIT1_2DBLOCK_DIS;
  394. miscinit1 |= MISCINIT1_CLUT_INV;
  395. banshee_make_room(par, 1);
  396. tdfx_outl(par, MISCINIT1, miscinit1);
  397. return lfbsize;
  398. }
  399. /* ------------------------------------------------------------------------- */
  400. static int tdfxfb_check_var(struct fb_var_screeninfo *var,struct fb_info *info)
  401. {
  402. struct tdfx_par *par = info->par;
  403. u32 lpitch;
  404. if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
  405. var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
  406. DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
  407. return -EINVAL;
  408. }
  409. if (var->xres != var->xres_virtual)
  410. var->xres_virtual = var->xres;
  411. if (var->yres > var->yres_virtual)
  412. var->yres_virtual = var->yres;
  413. if (var->xoffset) {
  414. DPRINTK("xoffset not supported\n");
  415. return -EINVAL;
  416. }
  417. /* Banshee doesn't support interlace, but Voodoo4/5 and probably Voodoo3 do. */
  418. /* no direct information about device id now? use max_pixclock for this... */
  419. if (((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) &&
  420. (par->max_pixclock < VOODOO3_MAX_PIXCLOCK)) {
  421. DPRINTK("interlace not supported\n");
  422. return -EINVAL;
  423. }
  424. var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
  425. lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
  426. if (var->xres < 320 || var->xres > 2048) {
  427. DPRINTK("width not supported: %u\n", var->xres);
  428. return -EINVAL;
  429. }
  430. if (var->yres < 200 || var->yres > 2048) {
  431. DPRINTK("height not supported: %u\n", var->yres);
  432. return -EINVAL;
  433. }
  434. if (lpitch * var->yres_virtual > info->fix.smem_len) {
  435. var->yres_virtual = info->fix.smem_len/lpitch;
  436. if (var->yres_virtual < var->yres) {
  437. DPRINTK("no memory for screen (%ux%ux%u)\n",
  438. var->xres, var->yres_virtual, var->bits_per_pixel);
  439. return -EINVAL;
  440. }
  441. }
  442. if (PICOS2KHZ(var->pixclock) > par->max_pixclock) {
  443. DPRINTK("pixclock too high (%ldKHz)\n",PICOS2KHZ(var->pixclock));
  444. return -EINVAL;
  445. }
  446. switch(var->bits_per_pixel) {
  447. case 8:
  448. var->red.length = var->green.length = var->blue.length = 8;
  449. break;
  450. case 16:
  451. var->red.offset = 11;
  452. var->red.length = 5;
  453. var->green.offset = 5;
  454. var->green.length = 6;
  455. var->blue.offset = 0;
  456. var->blue.length = 5;
  457. break;
  458. case 24:
  459. var->red.offset=16;
  460. var->green.offset=8;
  461. var->blue.offset=0;
  462. var->red.length = var->green.length = var->blue.length = 8;
  463. case 32:
  464. var->red.offset = 16;
  465. var->green.offset = 8;
  466. var->blue.offset = 0;
  467. var->red.length = var->green.length = var->blue.length = 8;
  468. break;
  469. }
  470. var->height = var->width = -1;
  471. var->accel_flags = FB_ACCELF_TEXT;
  472. DPRINTK("Checking graphics mode at %dx%d depth %d\n", var->xres, var->yres, var->bits_per_pixel);
  473. return 0;
  474. }
  475. static int tdfxfb_set_par(struct fb_info *info)
  476. {
  477. struct tdfx_par *par = info->par;
  478. u32 hdispend, hsyncsta, hsyncend, htotal;
  479. u32 hd, hs, he, ht, hbs, hbe;
  480. u32 vd, vs, ve, vt, vbs, vbe;
  481. struct banshee_reg reg;
  482. int fout, freq;
  483. u32 wd, cpp;
  484. par->baseline = 0;
  485. memset(&reg, 0, sizeof(reg));
  486. cpp = (info->var.bits_per_pixel + 7)/8;
  487. reg.vidcfg = VIDCFG_VIDPROC_ENABLE | VIDCFG_DESK_ENABLE | VIDCFG_CURS_X11 | ((cpp - 1) << VIDCFG_PIXFMT_SHIFT) | (cpp != 1 ? VIDCFG_CLUT_BYPASS : 0);
  488. /* PLL settings */
  489. freq = PICOS2KHZ(info->var.pixclock);
  490. reg.dacmode = 0;
  491. reg.vidcfg &= ~VIDCFG_2X;
  492. hdispend = info->var.xres;
  493. hsyncsta = hdispend + info->var.right_margin;
  494. hsyncend = hsyncsta + info->var.hsync_len;
  495. htotal = hsyncend + info->var.left_margin;
  496. if (freq > par->max_pixclock/2) {
  497. freq = freq > par->max_pixclock ? par->max_pixclock : freq;
  498. reg.dacmode |= DACMODE_2X;
  499. reg.vidcfg |= VIDCFG_2X;
  500. hdispend >>= 1;
  501. hsyncsta >>= 1;
  502. hsyncend >>= 1;
  503. htotal >>= 1;
  504. }
  505. hd = wd = (hdispend >> 3) - 1;
  506. hs = (hsyncsta >> 3) - 1;
  507. he = (hsyncend >> 3) - 1;
  508. ht = (htotal >> 3) - 1;
  509. hbs = hd;
  510. hbe = ht;
  511. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
  512. vbs = vd = (info->var.yres << 1) - 1;
  513. vs = vd + (info->var.lower_margin << 1);
  514. ve = vs + (info->var.vsync_len << 1);
  515. vbe = vt = ve + (info->var.upper_margin << 1) - 1;
  516. } else {
  517. vbs = vd = info->var.yres - 1;
  518. vs = vd + info->var.lower_margin;
  519. ve = vs + info->var.vsync_len;
  520. vbe = vt = ve + info->var.upper_margin - 1;
  521. }
  522. /* this is all pretty standard VGA register stuffing */
  523. reg.misc[0x00] = 0x0f |
  524. (info->var.xres < 400 ? 0xa0 :
  525. info->var.xres < 480 ? 0x60 :
  526. info->var.xres < 768 ? 0xe0 : 0x20);
  527. reg.gra[0x00] = 0x00;
  528. reg.gra[0x01] = 0x00;
  529. reg.gra[0x02] = 0x00;
  530. reg.gra[0x03] = 0x00;
  531. reg.gra[0x04] = 0x00;
  532. reg.gra[0x05] = 0x40;
  533. reg.gra[0x06] = 0x05;
  534. reg.gra[0x07] = 0x0f;
  535. reg.gra[0x08] = 0xff;
  536. reg.att[0x00] = 0x00;
  537. reg.att[0x01] = 0x01;
  538. reg.att[0x02] = 0x02;
  539. reg.att[0x03] = 0x03;
  540. reg.att[0x04] = 0x04;
  541. reg.att[0x05] = 0x05;
  542. reg.att[0x06] = 0x06;
  543. reg.att[0x07] = 0x07;
  544. reg.att[0x08] = 0x08;
  545. reg.att[0x09] = 0x09;
  546. reg.att[0x0a] = 0x0a;
  547. reg.att[0x0b] = 0x0b;
  548. reg.att[0x0c] = 0x0c;
  549. reg.att[0x0d] = 0x0d;
  550. reg.att[0x0e] = 0x0e;
  551. reg.att[0x0f] = 0x0f;
  552. reg.att[0x10] = 0x41;
  553. reg.att[0x11] = 0x00;
  554. reg.att[0x12] = 0x0f;
  555. reg.att[0x13] = 0x00;
  556. reg.att[0x14] = 0x00;
  557. reg.seq[0x00] = 0x03;
  558. reg.seq[0x01] = 0x01; /* fixme: clkdiv2? */
  559. reg.seq[0x02] = 0x0f;
  560. reg.seq[0x03] = 0x00;
  561. reg.seq[0x04] = 0x0e;
  562. reg.crt[0x00] = ht - 4;
  563. reg.crt[0x01] = hd;
  564. reg.crt[0x02] = hbs;
  565. reg.crt[0x03] = 0x80 | (hbe & 0x1f);
  566. reg.crt[0x04] = hs;
  567. reg.crt[0x05] = ((hbe & 0x20) << 2) | (he & 0x1f);
  568. reg.crt[0x06] = vt;
  569. reg.crt[0x07] = ((vs & 0x200) >> 2) |
  570. ((vd & 0x200) >> 3) |
  571. ((vt & 0x200) >> 4) | 0x10 |
  572. ((vbs & 0x100) >> 5) |
  573. ((vs & 0x100) >> 6) |
  574. ((vd & 0x100) >> 7) |
  575. ((vt & 0x100) >> 8);
  576. reg.crt[0x08] = 0x00;
  577. reg.crt[0x09] = 0x40 | ((vbs & 0x200) >> 4);
  578. reg.crt[0x0a] = 0x00;
  579. reg.crt[0x0b] = 0x00;
  580. reg.crt[0x0c] = 0x00;
  581. reg.crt[0x0d] = 0x00;
  582. reg.crt[0x0e] = 0x00;
  583. reg.crt[0x0f] = 0x00;
  584. reg.crt[0x10] = vs;
  585. reg.crt[0x11] = (ve & 0x0f) | 0x20;
  586. reg.crt[0x12] = vd;
  587. reg.crt[0x13] = wd;
  588. reg.crt[0x14] = 0x00;
  589. reg.crt[0x15] = vbs;
  590. reg.crt[0x16] = vbe + 1;
  591. reg.crt[0x17] = 0xc3;
  592. reg.crt[0x18] = 0xff;
  593. /* Banshee's nonvga stuff */
  594. reg.ext[0x00] = (((ht & 0x100) >> 8) |
  595. ((hd & 0x100) >> 6) |
  596. ((hbs & 0x100) >> 4) |
  597. ((hbe & 0x40) >> 1) |
  598. ((hs & 0x100) >> 2) |
  599. ((he & 0x20) << 2));
  600. reg.ext[0x01] = (((vt & 0x400) >> 10) |
  601. ((vd & 0x400) >> 8) |
  602. ((vbs & 0x400) >> 6) |
  603. ((vbe & 0x400) >> 4));
  604. reg.vgainit0 = VGAINIT0_8BIT_DAC |
  605. VGAINIT0_EXT_ENABLE |
  606. VGAINIT0_WAKEUP_3C3 |
  607. VGAINIT0_ALT_READBACK |
  608. VGAINIT0_EXTSHIFTOUT;
  609. reg.vgainit1 = tdfx_inl(par, VGAINIT1) & 0x1fffff;
  610. reg.cursloc = 0;
  611. reg.cursc0 = 0;
  612. reg.cursc1 = 0xffffff;
  613. reg.stride = info->var.xres * cpp;
  614. reg.startaddr = par->baseline * reg.stride;
  615. reg.srcbase = reg.startaddr;
  616. reg.dstbase = reg.startaddr;
  617. /* PLL settings */
  618. freq = PICOS2KHZ(info->var.pixclock);
  619. reg.dacmode &= ~DACMODE_2X;
  620. reg.vidcfg &= ~VIDCFG_2X;
  621. if (freq > par->max_pixclock/2) {
  622. freq = freq > par->max_pixclock ? par->max_pixclock : freq;
  623. reg.dacmode |= DACMODE_2X;
  624. reg.vidcfg |= VIDCFG_2X;
  625. }
  626. reg.vidpll = do_calc_pll(freq, &fout);
  627. #if 0
  628. reg.mempll = do_calc_pll(..., &fout);
  629. reg.gfxpll = do_calc_pll(..., &fout);
  630. #endif
  631. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
  632. reg.screensize = info->var.xres | (info->var.yres << 13);
  633. reg.vidcfg |= VIDCFG_HALF_MODE;
  634. reg.crt[0x09] |= 0x80;
  635. } else {
  636. reg.screensize = info->var.xres | (info->var.yres << 12);
  637. reg.vidcfg &= ~VIDCFG_HALF_MODE;
  638. }
  639. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
  640. reg.vidcfg |= VIDCFG_INTERLACE;
  641. reg.miscinit0 = tdfx_inl(par, MISCINIT0);
  642. #if defined(__BIG_ENDIAN)
  643. switch (info->var.bits_per_pixel) {
  644. case 8:
  645. case 24:
  646. reg.miscinit0 &= ~(1 << 30);
  647. reg.miscinit0 &= ~(1 << 31);
  648. break;
  649. case 16:
  650. reg.miscinit0 |= (1 << 30);
  651. reg.miscinit0 |= (1 << 31);
  652. break;
  653. case 32:
  654. reg.miscinit0 |= (1 << 30);
  655. reg.miscinit0 &= ~(1 << 31);
  656. break;
  657. }
  658. #endif
  659. do_write_regs(info, &reg);
  660. /* Now change fb_fix_screeninfo according to changes in par */
  661. info->fix.line_length = info->var.xres * ((info->var.bits_per_pixel + 7)>>3);
  662. info->fix.visual = (info->var.bits_per_pixel == 8)
  663. ? FB_VISUAL_PSEUDOCOLOR
  664. : FB_VISUAL_TRUECOLOR;
  665. DPRINTK("Graphics mode is now set at %dx%d depth %d\n", info->var.xres, info->var.yres, info->var.bits_per_pixel);
  666. return 0;
  667. }
  668. /* A handy macro shamelessly pinched from matroxfb */
  669. #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
  670. static int tdfxfb_setcolreg(unsigned regno, unsigned red, unsigned green,
  671. unsigned blue,unsigned transp,struct fb_info *info)
  672. {
  673. struct tdfx_par *par = info->par;
  674. u32 rgbcol;
  675. if (regno >= info->cmap.len || regno > 255) return 1;
  676. switch (info->fix.visual) {
  677. case FB_VISUAL_PSEUDOCOLOR:
  678. rgbcol =(((u32)red & 0xff00) << 8) |
  679. (((u32)green & 0xff00) << 0) |
  680. (((u32)blue & 0xff00) >> 8);
  681. do_setpalentry(par, regno, rgbcol);
  682. break;
  683. /* Truecolor has no hardware color palettes. */
  684. case FB_VISUAL_TRUECOLOR:
  685. if (regno < 16) {
  686. rgbcol = (CNVT_TOHW( red, info->var.red.length) <<
  687. info->var.red.offset) |
  688. (CNVT_TOHW( green, info->var.green.length) <<
  689. info->var.green.offset) |
  690. (CNVT_TOHW( blue, info->var.blue.length) <<
  691. info->var.blue.offset) |
  692. (CNVT_TOHW( transp, info->var.transp.length) <<
  693. info->var.transp.offset);
  694. par->palette[regno] = rgbcol;
  695. }
  696. break;
  697. default:
  698. DPRINTK("bad depth %u\n", info->var.bits_per_pixel);
  699. break;
  700. }
  701. return 0;
  702. }
  703. /* 0 unblank, 1 blank, 2 no vsync, 3 no hsync, 4 off */
  704. static int tdfxfb_blank(int blank, struct fb_info *info)
  705. {
  706. struct tdfx_par *par = info->par;
  707. u32 dacmode, state = 0, vgablank = 0;
  708. dacmode = tdfx_inl(par, DACMODE);
  709. switch (blank) {
  710. case FB_BLANK_UNBLANK: /* Screen: On; HSync: On, VSync: On */
  711. state = 0;
  712. vgablank = 0;
  713. break;
  714. case FB_BLANK_NORMAL: /* Screen: Off; HSync: On, VSync: On */
  715. state = 0;
  716. vgablank = 1;
  717. break;
  718. case FB_BLANK_VSYNC_SUSPEND: /* Screen: Off; HSync: On, VSync: Off */
  719. state = BIT(3);
  720. vgablank = 1;
  721. break;
  722. case FB_BLANK_HSYNC_SUSPEND: /* Screen: Off; HSync: Off, VSync: On */
  723. state = BIT(1);
  724. vgablank = 1;
  725. break;
  726. case FB_BLANK_POWERDOWN: /* Screen: Off; HSync: Off, VSync: Off */
  727. state = BIT(1) | BIT(3);
  728. vgablank = 1;
  729. break;
  730. }
  731. dacmode &= ~(BIT(1) | BIT(3));
  732. dacmode |= state;
  733. banshee_make_room(par, 1);
  734. tdfx_outl(par, DACMODE, dacmode);
  735. if (vgablank)
  736. vga_disable_video(par);
  737. else
  738. vga_enable_video(par);
  739. return 0;
  740. }
  741. /*
  742. * Set the starting position of the visible screen to var->yoffset
  743. */
  744. static int tdfxfb_pan_display(struct fb_var_screeninfo *var,
  745. struct fb_info *info)
  746. {
  747. struct tdfx_par *par = info->par;
  748. u32 addr;
  749. if (nopan || var->xoffset || (var->yoffset > var->yres_virtual))
  750. return -EINVAL;
  751. if ((var->yoffset + var->yres > var->yres_virtual && nowrap))
  752. return -EINVAL;
  753. addr = var->yoffset * info->fix.line_length;
  754. banshee_make_room(par, 1);
  755. tdfx_outl(par, VIDDESKSTART, addr);
  756. info->var.xoffset = var->xoffset;
  757. info->var.yoffset = var->yoffset;
  758. return 0;
  759. }
  760. #ifdef CONFIG_FB_3DFX_ACCEL
  761. /*
  762. * FillRect 2D command (solidfill or invert (via ROP_XOR))
  763. */
  764. static void tdfxfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  765. {
  766. struct tdfx_par *par = info->par;
  767. u32 bpp = info->var.bits_per_pixel;
  768. u32 stride = info->fix.line_length;
  769. u32 fmt= stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
  770. int tdfx_rop;
  771. if (rect->rop == ROP_COPY)
  772. tdfx_rop = TDFX_ROP_COPY;
  773. else
  774. tdfx_rop = TDFX_ROP_XOR;
  775. banshee_make_room(par, 5);
  776. tdfx_outl(par, DSTFORMAT, fmt);
  777. if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
  778. tdfx_outl(par, COLORFORE, rect->color);
  779. } else { /* FB_VISUAL_TRUECOLOR */
  780. tdfx_outl(par, COLORFORE, par->palette[rect->color]);
  781. }
  782. tdfx_outl(par, COMMAND_2D, COMMAND_2D_FILLRECT | (tdfx_rop << 24));
  783. tdfx_outl(par, DSTSIZE, rect->width | (rect->height << 16));
  784. tdfx_outl(par, LAUNCH_2D, rect->dx | (rect->dy << 16));
  785. }
  786. /*
  787. * Screen-to-Screen BitBlt 2D command (for the bmove fb op.)
  788. */
  789. static void tdfxfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  790. {
  791. struct tdfx_par *par = info->par;
  792. u32 sx = area->sx, sy = area->sy, dx = area->dx, dy = area->dy;
  793. u32 bpp = info->var.bits_per_pixel;
  794. u32 stride = info->fix.line_length;
  795. u32 blitcmd = COMMAND_2D_S2S_BITBLT | (TDFX_ROP_COPY << 24);
  796. u32 fmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
  797. if (area->sx <= area->dx) {
  798. //-X
  799. blitcmd |= BIT(14);
  800. sx += area->width - 1;
  801. dx += area->width - 1;
  802. }
  803. if (area->sy <= area->dy) {
  804. //-Y
  805. blitcmd |= BIT(15);
  806. sy += area->height - 1;
  807. dy += area->height - 1;
  808. }
  809. banshee_make_room(par, 6);
  810. tdfx_outl(par, SRCFORMAT, fmt);
  811. tdfx_outl(par, DSTFORMAT, fmt);
  812. tdfx_outl(par, COMMAND_2D, blitcmd);
  813. tdfx_outl(par, DSTSIZE, area->width | (area->height << 16));
  814. tdfx_outl(par, DSTXY, dx | (dy << 16));
  815. tdfx_outl(par, LAUNCH_2D, sx | (sy << 16));
  816. }
  817. static void tdfxfb_imageblit(struct fb_info *info, const struct fb_image *image)
  818. {
  819. struct tdfx_par *par = info->par;
  820. int size = image->height * ((image->width * image->depth + 7)>>3);
  821. int fifo_free;
  822. int i, stride = info->fix.line_length;
  823. u32 bpp = info->var.bits_per_pixel;
  824. u32 dstfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13);
  825. u8 *chardata = (u8 *) image->data;
  826. u32 srcfmt;
  827. if (image->depth != 1) {
  828. //banshee_make_room(par, 6 + ((size + 3) >> 2));
  829. //srcfmt = stride | ((bpp+((bpp==8) ? 0 : 8)) << 13) | 0x400000;
  830. cfb_imageblit(info, image);
  831. return;
  832. } else {
  833. banshee_make_room(par, 8);
  834. switch (info->fix.visual) {
  835. case FB_VISUAL_PSEUDOCOLOR:
  836. tdfx_outl(par, COLORFORE, image->fg_color);
  837. tdfx_outl(par, COLORBACK, image->bg_color);
  838. break;
  839. case FB_VISUAL_TRUECOLOR:
  840. default:
  841. tdfx_outl(par, COLORFORE,
  842. par->palette[image->fg_color]);
  843. tdfx_outl(par, COLORBACK,
  844. par->palette[image->bg_color]);
  845. }
  846. #ifdef __BIG_ENDIAN
  847. srcfmt = 0x400000 | BIT(20);
  848. #else
  849. srcfmt = 0x400000;
  850. #endif
  851. }
  852. tdfx_outl(par, SRCXY, 0);
  853. tdfx_outl(par, DSTXY, image->dx | (image->dy << 16));
  854. tdfx_outl(par, COMMAND_2D, COMMAND_2D_H2S_BITBLT | (TDFX_ROP_COPY << 24));
  855. tdfx_outl(par, SRCFORMAT, srcfmt);
  856. tdfx_outl(par, DSTFORMAT, dstfmt);
  857. tdfx_outl(par, DSTSIZE, image->width | (image->height << 16));
  858. /* A count of how many free FIFO entries we've requested.
  859. * When this goes negative, we need to request more. */
  860. fifo_free = 0;
  861. /* Send four bytes at a time of data */
  862. for (i = (size >> 2) ; i > 0; i--) {
  863. if(--fifo_free < 0) {
  864. fifo_free=31;
  865. banshee_make_room(par,fifo_free);
  866. }
  867. tdfx_outl(par, LAUNCH_2D,*(u32*)chardata);
  868. chardata += 4;
  869. }
  870. /* Send the leftovers now */
  871. banshee_make_room(par,3);
  872. i = size%4;
  873. switch (i) {
  874. case 0: break;
  875. case 1: tdfx_outl(par, LAUNCH_2D,*chardata); break;
  876. case 2: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata); break;
  877. case 3: tdfx_outl(par, LAUNCH_2D,*(u16*)chardata | ((chardata[3]) << 24)); break;
  878. }
  879. }
  880. #endif /* CONFIG_FB_3DFX_ACCEL */
  881. #ifdef TDFX_HARDWARE_CURSOR
  882. static int tdfxfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  883. {
  884. struct tdfx_par *par = info->par;
  885. unsigned long flags;
  886. /*
  887. * If the cursor is not be changed this means either we want the
  888. * current cursor state (if enable is set) or we want to query what
  889. * we can do with the cursor (if enable is not set)
  890. */
  891. if (!cursor->set) return 0;
  892. /* Too large of a cursor :-( */
  893. if (cursor->image.width > 64 || cursor->image.height > 64)
  894. return -ENXIO;
  895. /*
  896. * If we are going to be changing things we should disable
  897. * the cursor first
  898. */
  899. if (info->cursor.enable) {
  900. spin_lock_irqsave(&par->DAClock, flags);
  901. info->cursor.enable = 0;
  902. del_timer(&(par->hwcursor.timer));
  903. tdfx_outl(par, VIDPROCCFG, par->hwcursor.disable);
  904. spin_unlock_irqrestore(&par->DAClock, flags);
  905. }
  906. /* Disable the Cursor */
  907. if ((cursor->set && FB_CUR_SETCUR) && !cursor->enable)
  908. return 0;
  909. /* fix cursor color - XFree86 forgets to restore it properly */
  910. if (cursor->set && FB_CUR_SETCMAP) {
  911. struct fb_cmap cmap = cursor->image.cmap;
  912. unsigned long bg_color, fg_color;
  913. cmap.len = 2; /* Voodoo 3+ only support 2 color cursors */
  914. fg_color = ((cmap.red[cmap.start] << 16) |
  915. (cmap.green[cmap.start] << 8) |
  916. (cmap.blue[cmap.start]));
  917. bg_color = ((cmap.red[cmap.start+1] << 16) |
  918. (cmap.green[cmap.start+1] << 8) |
  919. (cmap.blue[cmap.start+1]));
  920. fb_copy_cmap(&cmap, &info->cursor.image.cmap);
  921. spin_lock_irqsave(&par->DAClock, flags);
  922. banshee_make_room(par, 2);
  923. tdfx_outl(par, HWCURC0, bg_color);
  924. tdfx_outl(par, HWCURC1, fg_color);
  925. spin_unlock_irqrestore(&par->DAClock, flags);
  926. }
  927. if (cursor->set && FB_CUR_SETPOS) {
  928. int x, y;
  929. x = cursor->image.dx;
  930. y = cursor->image.dy;
  931. y -= info->var.yoffset;
  932. info->cursor.image.dx = x;
  933. info->cursor.image.dy = y;
  934. x += 63;
  935. y += 63;
  936. spin_lock_irqsave(&par->DAClock, flags);
  937. banshee_make_room(par, 1);
  938. tdfx_outl(par, HWCURLOC, (y << 16) + x);
  939. spin_unlock_irqrestore(&par->DAClock, flags);
  940. }
  941. /* Not supported so we fake it */
  942. if (cursor->set && FB_CUR_SETHOT) {
  943. info->cursor.hot.x = cursor->hot.x;
  944. info->cursor.hot.y = cursor->hot.y;
  945. }
  946. if (cursor->set && FB_CUR_SETSHAPE) {
  947. /*
  948. * Voodoo 3 and above cards use 2 monochrome cursor patterns.
  949. * The reason is so the card can fetch 8 words at a time
  950. * and are stored on chip for use for the next 8 scanlines.
  951. * This reduces the number of times for access to draw the
  952. * cursor for each screen refresh.
  953. * Each pattern is a bitmap of 64 bit wide and 64 bit high
  954. * (total of 8192 bits or 1024 Kbytes). The two patterns are
  955. * stored in such a way that pattern 0 always resides in the
  956. * lower half (least significant 64 bits) of a 128 bit word
  957. * and pattern 1 the upper half. If you examine the data of
  958. * the cursor image the graphics card uses then from the
  959. * begining you see line one of pattern 0, line one of
  960. * pattern 1, line two of pattern 0, line two of pattern 1,
  961. * etc etc. The linear stride for the cursor is always 16 bytes
  962. * (128 bits) which is the maximum cursor width times two for
  963. * the two monochrome patterns.
  964. */
  965. u8 *cursorbase = (u8 *) info->cursor.image.data;
  966. char *bitmap = (char *)cursor->image.data;
  967. char *mask = (char *) cursor->mask;
  968. int i, j, k, h = 0;
  969. for (i = 0; i < 64; i++) {
  970. if (i < cursor->image.height) {
  971. j = (cursor->image.width + 7) >> 3;
  972. k = 8 - j;
  973. for (;j > 0; j--) {
  974. /* Pattern 0. Copy the cursor bitmap to it */
  975. fb_writeb(*bitmap, cursorbase + h);
  976. bitmap++;
  977. /* Pattern 1. Copy the cursor mask to it */
  978. fb_writeb(*mask, cursorbase + h + 8);
  979. mask++;
  980. h++;
  981. }
  982. for (;k > 0; k--) {
  983. fb_writeb(0, cursorbase + h);
  984. fb_writeb(~0, cursorbase + h + 8);
  985. h++;
  986. }
  987. } else {
  988. fb_writel(0, cursorbase + h);
  989. fb_writel(0, cursorbase + h + 4);
  990. fb_writel(~0, cursorbase + h + 8);
  991. fb_writel(~0, cursorbase + h + 12);
  992. h += 16;
  993. }
  994. }
  995. }
  996. /* Turn the cursor on */
  997. cursor->enable = 1;
  998. info->cursor = *cursor;
  999. mod_timer(&par->hwcursor.timer, jiffies+HZ/2);
  1000. spin_lock_irqsave(&par->DAClock, flags);
  1001. banshee_make_room(par, 1);
  1002. tdfx_outl(par, VIDPROCCFG, par->hwcursor.enable);
  1003. spin_unlock_irqrestore(&par->DAClock, flags);
  1004. return 0;
  1005. }
  1006. #endif
  1007. /**
  1008. * tdfxfb_probe - Device Initializiation
  1009. *
  1010. * @pdev: PCI Device to initialize
  1011. * @id: PCI Device ID
  1012. *
  1013. * Initializes and allocates resources for PCI device @pdev.
  1014. *
  1015. */
  1016. static int __devinit tdfxfb_probe(struct pci_dev *pdev,
  1017. const struct pci_device_id *id)
  1018. {
  1019. struct tdfx_par *default_par;
  1020. struct fb_info *info;
  1021. int err, lpitch;
  1022. if ((err = pci_enable_device(pdev))) {
  1023. printk(KERN_WARNING "tdfxfb: Can't enable pdev: %d\n", err);
  1024. return err;
  1025. }
  1026. info = framebuffer_alloc(sizeof(struct tdfx_par), &pdev->dev);
  1027. if (!info)
  1028. return -ENOMEM;
  1029. default_par = info->par;
  1030. /* Configure the default fb_fix_screeninfo first */
  1031. switch (pdev->device) {
  1032. case PCI_DEVICE_ID_3DFX_BANSHEE:
  1033. strcat(tdfx_fix.id, " Banshee");
  1034. default_par->max_pixclock = BANSHEE_MAX_PIXCLOCK;
  1035. break;
  1036. case PCI_DEVICE_ID_3DFX_VOODOO3:
  1037. strcat(tdfx_fix.id, " Voodoo3");
  1038. default_par->max_pixclock = VOODOO3_MAX_PIXCLOCK;
  1039. break;
  1040. case PCI_DEVICE_ID_3DFX_VOODOO5:
  1041. strcat(tdfx_fix.id, " Voodoo5");
  1042. default_par->max_pixclock = VOODOO5_MAX_PIXCLOCK;
  1043. break;
  1044. }
  1045. tdfx_fix.mmio_start = pci_resource_start(pdev, 0);
  1046. tdfx_fix.mmio_len = pci_resource_len(pdev, 0);
  1047. default_par->regbase_virt = ioremap_nocache(tdfx_fix.mmio_start, tdfx_fix.mmio_len);
  1048. if (!default_par->regbase_virt) {
  1049. printk("fb: Can't remap %s register area.\n", tdfx_fix.id);
  1050. goto out_err;
  1051. }
  1052. if (!request_mem_region(pci_resource_start(pdev, 0),
  1053. pci_resource_len(pdev, 0), "tdfx regbase")) {
  1054. printk(KERN_WARNING "tdfxfb: Can't reserve regbase\n");
  1055. goto out_err;
  1056. }
  1057. tdfx_fix.smem_start = pci_resource_start(pdev, 1);
  1058. if (!(tdfx_fix.smem_len = do_lfb_size(default_par, pdev->device))) {
  1059. printk("fb: Can't count %s memory.\n", tdfx_fix.id);
  1060. release_mem_region(pci_resource_start(pdev, 0),
  1061. pci_resource_len(pdev, 0));
  1062. goto out_err;
  1063. }
  1064. if (!request_mem_region(pci_resource_start(pdev, 1),
  1065. pci_resource_len(pdev, 1), "tdfx smem")) {
  1066. printk(KERN_WARNING "tdfxfb: Can't reserve smem\n");
  1067. release_mem_region(pci_resource_start(pdev, 0),
  1068. pci_resource_len(pdev, 0));
  1069. goto out_err;
  1070. }
  1071. info->screen_base = ioremap_nocache(tdfx_fix.smem_start,
  1072. tdfx_fix.smem_len);
  1073. if (!info->screen_base) {
  1074. printk("fb: Can't remap %s framebuffer.\n", tdfx_fix.id);
  1075. release_mem_region(pci_resource_start(pdev, 1),
  1076. pci_resource_len(pdev, 1));
  1077. release_mem_region(pci_resource_start(pdev, 0),
  1078. pci_resource_len(pdev, 0));
  1079. goto out_err;
  1080. }
  1081. default_par->iobase = pci_resource_start(pdev, 2);
  1082. if (!request_region(pci_resource_start(pdev, 2),
  1083. pci_resource_len(pdev, 2), "tdfx iobase")) {
  1084. printk(KERN_WARNING "tdfxfb: Can't reserve iobase\n");
  1085. release_mem_region(pci_resource_start(pdev, 1),
  1086. pci_resource_len(pdev, 1));
  1087. release_mem_region(pci_resource_start(pdev, 0),
  1088. pci_resource_len(pdev, 0));
  1089. goto out_err;
  1090. }
  1091. printk("fb: %s memory = %dK\n", tdfx_fix.id, tdfx_fix.smem_len >> 10);
  1092. tdfx_fix.ypanstep = nopan ? 0 : 1;
  1093. tdfx_fix.ywrapstep = nowrap ? 0 : 1;
  1094. info->fbops = &tdfxfb_ops;
  1095. info->fix = tdfx_fix;
  1096. info->pseudo_palette = default_par->palette;
  1097. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  1098. #ifdef CONFIG_FB_3DFX_ACCEL
  1099. info->flags |= FBINFO_HWACCEL_FILLRECT |
  1100. FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_IMAGEBLIT;
  1101. #endif
  1102. if (!mode_option)
  1103. mode_option = "640x480@60";
  1104. err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
  1105. if (!err || err == 4)
  1106. info->var = tdfx_var;
  1107. /* maximize virtual vertical length */
  1108. lpitch = info->var.xres_virtual * ((info->var.bits_per_pixel + 7) >> 3);
  1109. info->var.yres_virtual = info->fix.smem_len/lpitch;
  1110. if (info->var.yres_virtual < info->var.yres)
  1111. goto out_err;
  1112. #ifdef CONFIG_FB_3DFX_ACCEL
  1113. /*
  1114. * FIXME: Limit var->yres_virtual to 4096 because of screen artifacts
  1115. * during scrolling. This is only present if 2D acceleration is
  1116. * enabled.
  1117. */
  1118. if (info->var.yres_virtual > 4096)
  1119. info->var.yres_virtual = 4096;
  1120. #endif /* CONFIG_FB_3DFX_ACCEL */
  1121. if (fb_alloc_cmap(&info->cmap, 256, 0) < 0) {
  1122. printk(KERN_WARNING "tdfxfb: Can't allocate color map\n");
  1123. goto out_err;
  1124. }
  1125. if (register_framebuffer(info) < 0) {
  1126. printk("tdfxfb: can't register framebuffer\n");
  1127. fb_dealloc_cmap(&info->cmap);
  1128. goto out_err;
  1129. }
  1130. /*
  1131. * Our driver data
  1132. */
  1133. pci_set_drvdata(pdev, info);
  1134. return 0;
  1135. out_err:
  1136. /*
  1137. * Cleanup after anything that was remapped/allocated.
  1138. */
  1139. if (default_par->regbase_virt)
  1140. iounmap(default_par->regbase_virt);
  1141. if (info->screen_base)
  1142. iounmap(info->screen_base);
  1143. framebuffer_release(info);
  1144. return -ENXIO;
  1145. }
  1146. #ifndef MODULE
  1147. static void tdfxfb_setup(char *options)
  1148. {
  1149. char* this_opt;
  1150. if (!options || !*options)
  1151. return;
  1152. while ((this_opt = strsep(&options, ",")) != NULL) {
  1153. if (!*this_opt)
  1154. continue;
  1155. if(!strcmp(this_opt, "nopan")) {
  1156. nopan = 1;
  1157. } else if(!strcmp(this_opt, "nowrap")) {
  1158. nowrap = 1;
  1159. } else {
  1160. mode_option = this_opt;
  1161. }
  1162. }
  1163. }
  1164. #endif
  1165. /**
  1166. * tdfxfb_remove - Device removal
  1167. *
  1168. * @pdev: PCI Device to cleanup
  1169. *
  1170. * Releases all resources allocated during the course of the driver's
  1171. * lifetime for the PCI device @pdev.
  1172. *
  1173. */
  1174. static void __devexit tdfxfb_remove(struct pci_dev *pdev)
  1175. {
  1176. struct fb_info *info = pci_get_drvdata(pdev);
  1177. struct tdfx_par *par = info->par;
  1178. unregister_framebuffer(info);
  1179. iounmap(par->regbase_virt);
  1180. iounmap(info->screen_base);
  1181. /* Clean up after reserved regions */
  1182. release_region(pci_resource_start(pdev, 2),
  1183. pci_resource_len(pdev, 2));
  1184. release_mem_region(pci_resource_start(pdev, 1),
  1185. pci_resource_len(pdev, 1));
  1186. release_mem_region(pci_resource_start(pdev, 0),
  1187. pci_resource_len(pdev, 0));
  1188. pci_set_drvdata(pdev, NULL);
  1189. framebuffer_release(info);
  1190. }
  1191. static int __init tdfxfb_init(void)
  1192. {
  1193. #ifndef MODULE
  1194. char *option = NULL;
  1195. if (fb_get_options("tdfxfb", &option))
  1196. return -ENODEV;
  1197. tdfxfb_setup(option);
  1198. #endif
  1199. return pci_register_driver(&tdfxfb_driver);
  1200. }
  1201. static void __exit tdfxfb_exit(void)
  1202. {
  1203. pci_unregister_driver(&tdfxfb_driver);
  1204. }
  1205. MODULE_AUTHOR("Hannu Mallat <hmallat@cc.hut.fi>");
  1206. MODULE_DESCRIPTION("3Dfx framebuffer device driver");
  1207. MODULE_LICENSE("GPL");
  1208. module_init(tdfxfb_init);
  1209. module_exit(tdfxfb_exit);