stifb.c 35 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408
  1. /*
  2. * linux/drivers/video/stifb.c -
  3. * Low level Frame buffer driver for HP workstations with
  4. * STI (standard text interface) video firmware.
  5. *
  6. * Copyright (C) 2001-2006 Helge Deller <deller@gmx.de>
  7. * Portions Copyright (C) 2001 Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  8. *
  9. * Based on:
  10. * - linux/drivers/video/artistfb.c -- Artist frame buffer driver
  11. * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
  12. * - based on skeletonfb, which was
  13. * Created 28 Dec 1997 by Geert Uytterhoeven
  14. * - HP Xhp cfb-based X11 window driver for XFree86
  15. * (c)Copyright 1992 Hewlett-Packard Co.
  16. *
  17. *
  18. * The following graphics display devices (NGLE family) are supported by this driver:
  19. *
  20. * HPA4070A known as "HCRX", a 1280x1024 color device with 8 planes
  21. * HPA4071A known as "HCRX24", a 1280x1024 color device with 24 planes,
  22. * optionally available with a hardware accelerator as HPA4071A_Z
  23. * HPA1659A known as "CRX", a 1280x1024 color device with 8 planes
  24. * HPA1439A known as "CRX24", a 1280x1024 color device with 24 planes,
  25. * optionally available with a hardware accelerator.
  26. * HPA1924A known as "GRX", a 1280x1024 grayscale device with 8 planes
  27. * HPA2269A known as "Dual CRX", a 1280x1024 color device with 8 planes,
  28. * implements support for two displays on a single graphics card.
  29. * HP710C internal graphics support optionally available on the HP9000s710 SPU,
  30. * supports 1280x1024 color displays with 8 planes.
  31. * HP710G same as HP710C, 1280x1024 grayscale only
  32. * HP710L same as HP710C, 1024x768 color only
  33. * HP712 internal graphics support on HP9000s712 SPU, supports 640x480,
  34. * 1024x768 or 1280x1024 color displays on 8 planes (Artist)
  35. *
  36. * This file is subject to the terms and conditions of the GNU General Public
  37. * License. See the file COPYING in the main directory of this archive
  38. * for more details.
  39. */
  40. /* TODO:
  41. * - 1bpp mode is completely untested
  42. * - add support for h/w acceleration
  43. * - add hardware cursor
  44. * - automatically disable double buffering (e.g. on RDI precisionbook laptop)
  45. */
  46. /* on supported graphic devices you may:
  47. * #define FALLBACK_TO_1BPP to fall back to 1 bpp, or
  48. * #undef FALLBACK_TO_1BPP to reject support for unsupported cards */
  49. #undef FALLBACK_TO_1BPP
  50. #undef DEBUG_STIFB_REGS /* debug sti register accesses */
  51. #include <linux/module.h>
  52. #include <linux/kernel.h>
  53. #include <linux/errno.h>
  54. #include <linux/string.h>
  55. #include <linux/mm.h>
  56. #include <linux/slab.h>
  57. #include <linux/delay.h>
  58. #include <linux/fb.h>
  59. #include <linux/init.h>
  60. #include <linux/ioport.h>
  61. #include <linux/pci.h>
  62. #include <asm/grfioctl.h> /* for HP-UX compatibility */
  63. #include <asm/uaccess.h>
  64. #include "sticore.h"
  65. /* REGION_BASE(fb_info, index) returns the virtual address for region <index> */
  66. #define REGION_BASE(fb_info, index) \
  67. F_EXTEND(fb_info->sti->glob_cfg->region_ptrs[index])
  68. #define NGLEDEVDEPROM_CRT_REGION 1
  69. #define NR_PALETTE 256
  70. typedef struct {
  71. __s32 video_config_reg;
  72. __s32 misc_video_start;
  73. __s32 horiz_timing_fmt;
  74. __s32 serr_timing_fmt;
  75. __s32 vert_timing_fmt;
  76. __s32 horiz_state;
  77. __s32 vert_state;
  78. __s32 vtg_state_elements;
  79. __s32 pipeline_delay;
  80. __s32 misc_video_end;
  81. } video_setup_t;
  82. typedef struct {
  83. __s16 sizeof_ngle_data;
  84. __s16 x_size_visible; /* visible screen dim in pixels */
  85. __s16 y_size_visible;
  86. __s16 pad2[15];
  87. __s16 cursor_pipeline_delay;
  88. __s16 video_interleaves;
  89. __s32 pad3[11];
  90. } ngle_rom_t;
  91. struct stifb_info {
  92. struct fb_info info;
  93. unsigned int id;
  94. ngle_rom_t ngle_rom;
  95. struct sti_struct *sti;
  96. int deviceSpecificConfig;
  97. u32 pseudo_palette[16];
  98. };
  99. static int __initdata stifb_bpp_pref[MAX_STI_ROMS];
  100. /* ------------------- chipset specific functions -------------------------- */
  101. /* offsets to graphic-chip internal registers */
  102. #define REG_1 0x000118
  103. #define REG_2 0x000480
  104. #define REG_3 0x0004a0
  105. #define REG_4 0x000600
  106. #define REG_6 0x000800
  107. #define REG_8 0x000820
  108. #define REG_9 0x000a04
  109. #define REG_10 0x018000
  110. #define REG_11 0x018004
  111. #define REG_12 0x01800c
  112. #define REG_13 0x018018
  113. #define REG_14 0x01801c
  114. #define REG_15 0x200000
  115. #define REG_15b0 0x200000
  116. #define REG_16b1 0x200005
  117. #define REG_16b3 0x200007
  118. #define REG_21 0x200218
  119. #define REG_22 0x0005a0
  120. #define REG_23 0x0005c0
  121. #define REG_26 0x200118
  122. #define REG_27 0x200308
  123. #define REG_32 0x21003c
  124. #define REG_33 0x210040
  125. #define REG_34 0x200008
  126. #define REG_35 0x018010
  127. #define REG_38 0x210020
  128. #define REG_39 0x210120
  129. #define REG_40 0x210130
  130. #define REG_42 0x210028
  131. #define REG_43 0x21002c
  132. #define REG_44 0x210030
  133. #define REG_45 0x210034
  134. #define READ_BYTE(fb,reg) gsc_readb((fb)->info.fix.mmio_start + (reg))
  135. #define READ_WORD(fb,reg) gsc_readl((fb)->info.fix.mmio_start + (reg))
  136. #ifndef DEBUG_STIFB_REGS
  137. # define DEBUG_OFF()
  138. # define DEBUG_ON()
  139. # define WRITE_BYTE(value,fb,reg) gsc_writeb((value),(fb)->info.fix.mmio_start + (reg))
  140. # define WRITE_WORD(value,fb,reg) gsc_writel((value),(fb)->info.fix.mmio_start + (reg))
  141. #else
  142. static int debug_on = 1;
  143. # define DEBUG_OFF() debug_on=0
  144. # define DEBUG_ON() debug_on=1
  145. # define WRITE_BYTE(value,fb,reg) do { if (debug_on) \
  146. printk(KERN_DEBUG "%30s: WRITE_BYTE(0x%06x) = 0x%02x (old=0x%02x)\n", \
  147. __FUNCTION__, reg, value, READ_BYTE(fb,reg)); \
  148. gsc_writeb((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
  149. # define WRITE_WORD(value,fb,reg) do { if (debug_on) \
  150. printk(KERN_DEBUG "%30s: WRITE_WORD(0x%06x) = 0x%08x (old=0x%08x)\n", \
  151. __FUNCTION__, reg, value, READ_WORD(fb,reg)); \
  152. gsc_writel((value),(fb)->info.fix.mmio_start + (reg)); } while (0)
  153. #endif /* DEBUG_STIFB_REGS */
  154. #define ENABLE 1 /* for enabling/disabling screen */
  155. #define DISABLE 0
  156. #define NGLE_LOCK(fb_info) do { } while (0)
  157. #define NGLE_UNLOCK(fb_info) do { } while (0)
  158. static void
  159. SETUP_HW(struct stifb_info *fb)
  160. {
  161. char stat;
  162. do {
  163. stat = READ_BYTE(fb, REG_15b0);
  164. if (!stat)
  165. stat = READ_BYTE(fb, REG_15b0);
  166. } while (stat);
  167. }
  168. static void
  169. SETUP_FB(struct stifb_info *fb)
  170. {
  171. unsigned int reg10_value = 0;
  172. SETUP_HW(fb);
  173. switch (fb->id)
  174. {
  175. case CRT_ID_VISUALIZE_EG:
  176. case S9000_ID_ARTIST:
  177. case S9000_ID_A1659A:
  178. reg10_value = 0x13601000;
  179. break;
  180. case S9000_ID_A1439A:
  181. if (fb->info.var.bits_per_pixel == 32)
  182. reg10_value = 0xBBA0A000;
  183. else
  184. reg10_value = 0x13601000;
  185. break;
  186. case S9000_ID_HCRX:
  187. if (fb->info.var.bits_per_pixel == 32)
  188. reg10_value = 0xBBA0A000;
  189. else
  190. reg10_value = 0x13602000;
  191. break;
  192. case S9000_ID_TIMBER:
  193. case CRX24_OVERLAY_PLANES:
  194. reg10_value = 0x13602000;
  195. break;
  196. }
  197. if (reg10_value)
  198. WRITE_WORD(reg10_value, fb, REG_10);
  199. WRITE_WORD(0x83000300, fb, REG_14);
  200. SETUP_HW(fb);
  201. WRITE_BYTE(1, fb, REG_16b1);
  202. }
  203. static void
  204. START_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
  205. {
  206. SETUP_HW(fb);
  207. WRITE_WORD(0xBBE0F000, fb, REG_10);
  208. WRITE_WORD(0x03000300, fb, REG_14);
  209. WRITE_WORD(~0, fb, REG_13);
  210. }
  211. static void
  212. WRITE_IMAGE_COLOR(struct stifb_info *fb, int index, int color)
  213. {
  214. SETUP_HW(fb);
  215. WRITE_WORD(((0x100+index)<<2), fb, REG_3);
  216. WRITE_WORD(color, fb, REG_4);
  217. }
  218. static void
  219. FINISH_IMAGE_COLORMAP_ACCESS(struct stifb_info *fb)
  220. {
  221. WRITE_WORD(0x400, fb, REG_2);
  222. if (fb->info.var.bits_per_pixel == 32) {
  223. WRITE_WORD(0x83000100, fb, REG_1);
  224. } else {
  225. if (fb->id == S9000_ID_ARTIST || fb->id == CRT_ID_VISUALIZE_EG)
  226. WRITE_WORD(0x80000100, fb, REG_26);
  227. else
  228. WRITE_WORD(0x80000100, fb, REG_1);
  229. }
  230. SETUP_FB(fb);
  231. }
  232. static void
  233. SETUP_RAMDAC(struct stifb_info *fb)
  234. {
  235. SETUP_HW(fb);
  236. WRITE_WORD(0x04000000, fb, 0x1020);
  237. WRITE_WORD(0xff000000, fb, 0x1028);
  238. }
  239. static void
  240. CRX24_SETUP_RAMDAC(struct stifb_info *fb)
  241. {
  242. SETUP_HW(fb);
  243. WRITE_WORD(0x04000000, fb, 0x1000);
  244. WRITE_WORD(0x02000000, fb, 0x1004);
  245. WRITE_WORD(0xff000000, fb, 0x1008);
  246. WRITE_WORD(0x05000000, fb, 0x1000);
  247. WRITE_WORD(0x02000000, fb, 0x1004);
  248. WRITE_WORD(0x03000000, fb, 0x1008);
  249. }
  250. #if 0
  251. static void
  252. HCRX_SETUP_RAMDAC(struct stifb_info *fb)
  253. {
  254. WRITE_WORD(0xffffffff, fb, REG_32);
  255. }
  256. #endif
  257. static void
  258. CRX24_SET_OVLY_MASK(struct stifb_info *fb)
  259. {
  260. SETUP_HW(fb);
  261. WRITE_WORD(0x13a02000, fb, REG_11);
  262. WRITE_WORD(0x03000300, fb, REG_14);
  263. WRITE_WORD(0x000017f0, fb, REG_3);
  264. WRITE_WORD(0xffffffff, fb, REG_13);
  265. WRITE_WORD(0xffffffff, fb, REG_22);
  266. WRITE_WORD(0x00000000, fb, REG_23);
  267. }
  268. static void
  269. ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
  270. {
  271. unsigned int value = enable ? 0x43000000 : 0x03000000;
  272. SETUP_HW(fb);
  273. WRITE_WORD(0x06000000, fb, 0x1030);
  274. WRITE_WORD(value, fb, 0x1038);
  275. }
  276. static void
  277. CRX24_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
  278. {
  279. unsigned int value = enable ? 0x10000000 : 0x30000000;
  280. SETUP_HW(fb);
  281. WRITE_WORD(0x01000000, fb, 0x1000);
  282. WRITE_WORD(0x02000000, fb, 0x1004);
  283. WRITE_WORD(value, fb, 0x1008);
  284. }
  285. static void
  286. ARTIST_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
  287. {
  288. u32 DregsMiscVideo = REG_21;
  289. u32 DregsMiscCtl = REG_27;
  290. SETUP_HW(fb);
  291. if (enable) {
  292. WRITE_WORD(READ_WORD(fb, DregsMiscVideo) | 0x0A000000, fb, DregsMiscVideo);
  293. WRITE_WORD(READ_WORD(fb, DregsMiscCtl) | 0x00800000, fb, DregsMiscCtl);
  294. } else {
  295. WRITE_WORD(READ_WORD(fb, DregsMiscVideo) & ~0x0A000000, fb, DregsMiscVideo);
  296. WRITE_WORD(READ_WORD(fb, DregsMiscCtl) & ~0x00800000, fb, DregsMiscCtl);
  297. }
  298. }
  299. #define GET_ROMTABLE_INDEX(fb) \
  300. (READ_BYTE(fb, REG_16b3) - 1)
  301. #define HYPER_CONFIG_PLANES_24 0x00000100
  302. #define IS_24_DEVICE(fb) \
  303. (fb->deviceSpecificConfig & HYPER_CONFIG_PLANES_24)
  304. #define IS_888_DEVICE(fb) \
  305. (!(IS_24_DEVICE(fb)))
  306. #define GET_FIFO_SLOTS(fb, cnt, numslots) \
  307. { while (cnt < numslots) \
  308. cnt = READ_WORD(fb, REG_34); \
  309. cnt -= numslots; \
  310. }
  311. #define IndexedDcd 0 /* Pixel data is indexed (pseudo) color */
  312. #define Otc04 2 /* Pixels in each longword transfer (4) */
  313. #define Otc32 5 /* Pixels in each longword transfer (32) */
  314. #define Ots08 3 /* Each pixel is size (8)d transfer (1) */
  315. #define OtsIndirect 6 /* Each bit goes through FG/BG color(8) */
  316. #define AddrLong 5 /* FB address is Long aligned (pixel) */
  317. #define BINovly 0x2 /* 8 bit overlay */
  318. #define BINapp0I 0x0 /* Application Buffer 0, Indexed */
  319. #define BINapp1I 0x1 /* Application Buffer 1, Indexed */
  320. #define BINapp0F8 0xa /* Application Buffer 0, Fractional 8-8-8 */
  321. #define BINattr 0xd /* Attribute Bitmap */
  322. #define RopSrc 0x3
  323. #define BitmapExtent08 3 /* Each write hits ( 8) bits in depth */
  324. #define BitmapExtent32 5 /* Each write hits (32) bits in depth */
  325. #define DataDynamic 0 /* Data register reloaded by direct access */
  326. #define MaskDynamic 1 /* Mask register reloaded by direct access */
  327. #define MaskOtc 0 /* Mask contains Object Count valid bits */
  328. #define MaskAddrOffset(offset) (offset)
  329. #define StaticReg(en) (en)
  330. #define BGx(en) (en)
  331. #define FGx(en) (en)
  332. #define BAJustPoint(offset) (offset)
  333. #define BAIndexBase(base) (base)
  334. #define BA(F,C,S,A,J,B,I) \
  335. (((F)<<31)|((C)<<27)|((S)<<24)|((A)<<21)|((J)<<16)|((B)<<12)|(I))
  336. #define IBOvals(R,M,X,S,D,L,B,F) \
  337. (((R)<<8)|((M)<<16)|((X)<<24)|((S)<<29)|((D)<<28)|((L)<<31)|((B)<<1)|(F))
  338. #define NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb, val) \
  339. WRITE_WORD(val, fb, REG_14)
  340. #define NGLE_QUICK_SET_DST_BM_ACCESS(fb, val) \
  341. WRITE_WORD(val, fb, REG_11)
  342. #define NGLE_QUICK_SET_CTL_PLN_REG(fb, val) \
  343. WRITE_WORD(val, fb, REG_12)
  344. #define NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, plnmsk32) \
  345. WRITE_WORD(plnmsk32, fb, REG_13)
  346. #define NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, fg32) \
  347. WRITE_WORD(fg32, fb, REG_35)
  348. #define NGLE_SET_TRANSFERDATA(fb, val) \
  349. WRITE_WORD(val, fb, REG_8)
  350. #define NGLE_SET_DSTXY(fb, val) \
  351. WRITE_WORD(val, fb, REG_6)
  352. #define NGLE_LONG_FB_ADDRESS(fbaddrbase, x, y) ( \
  353. (u32) (fbaddrbase) + \
  354. ( (unsigned int) ( (y) << 13 ) | \
  355. (unsigned int) ( (x) << 2 ) ) \
  356. )
  357. #define NGLE_BINC_SET_DSTADDR(fb, addr) \
  358. WRITE_WORD(addr, fb, REG_3)
  359. #define NGLE_BINC_SET_SRCADDR(fb, addr) \
  360. WRITE_WORD(addr, fb, REG_2)
  361. #define NGLE_BINC_SET_DSTMASK(fb, mask) \
  362. WRITE_WORD(mask, fb, REG_22)
  363. #define NGLE_BINC_WRITE32(fb, data32) \
  364. WRITE_WORD(data32, fb, REG_23)
  365. #define START_COLORMAPLOAD(fb, cmapBltCtlData32) \
  366. WRITE_WORD((cmapBltCtlData32), fb, REG_38)
  367. #define SET_LENXY_START_RECFILL(fb, lenxy) \
  368. WRITE_WORD(lenxy, fb, REG_9)
  369. static void
  370. HYPER_ENABLE_DISABLE_DISPLAY(struct stifb_info *fb, int enable)
  371. {
  372. u32 DregsHypMiscVideo = REG_33;
  373. unsigned int value;
  374. SETUP_HW(fb);
  375. value = READ_WORD(fb, DregsHypMiscVideo);
  376. if (enable)
  377. value |= 0x0A000000;
  378. else
  379. value &= ~0x0A000000;
  380. WRITE_WORD(value, fb, DregsHypMiscVideo);
  381. }
  382. /* BufferNumbers used by SETUP_ATTR_ACCESS() */
  383. #define BUFF0_CMAP0 0x00001e02
  384. #define BUFF1_CMAP0 0x02001e02
  385. #define BUFF1_CMAP3 0x0c001e02
  386. #define ARTIST_CMAP0 0x00000102
  387. #define HYPER_CMAP8 0x00000100
  388. #define HYPER_CMAP24 0x00000800
  389. static void
  390. SETUP_ATTR_ACCESS(struct stifb_info *fb, unsigned BufferNumber)
  391. {
  392. SETUP_HW(fb);
  393. WRITE_WORD(0x2EA0D000, fb, REG_11);
  394. WRITE_WORD(0x23000302, fb, REG_14);
  395. WRITE_WORD(BufferNumber, fb, REG_12);
  396. WRITE_WORD(0xffffffff, fb, REG_8);
  397. }
  398. static void
  399. SET_ATTR_SIZE(struct stifb_info *fb, int width, int height)
  400. {
  401. /* REG_6 seems to have special values when run on a
  402. RDI precisionbook parisc laptop (INTERNAL_EG_DX1024 or
  403. INTERNAL_EG_X1024). The values are:
  404. 0x2f0: internal (LCD) & external display enabled
  405. 0x2a0: external display only
  406. 0x000: zero on standard artist graphic cards
  407. */
  408. WRITE_WORD(0x00000000, fb, REG_6);
  409. WRITE_WORD((width<<16) | height, fb, REG_9);
  410. WRITE_WORD(0x05000000, fb, REG_6);
  411. WRITE_WORD(0x00040001, fb, REG_9);
  412. }
  413. static void
  414. FINISH_ATTR_ACCESS(struct stifb_info *fb)
  415. {
  416. SETUP_HW(fb);
  417. WRITE_WORD(0x00000000, fb, REG_12);
  418. }
  419. static void
  420. elkSetupPlanes(struct stifb_info *fb)
  421. {
  422. SETUP_RAMDAC(fb);
  423. SETUP_FB(fb);
  424. }
  425. static void
  426. ngleSetupAttrPlanes(struct stifb_info *fb, int BufferNumber)
  427. {
  428. SETUP_ATTR_ACCESS(fb, BufferNumber);
  429. SET_ATTR_SIZE(fb, fb->info.var.xres, fb->info.var.yres);
  430. FINISH_ATTR_ACCESS(fb);
  431. SETUP_FB(fb);
  432. }
  433. static void
  434. rattlerSetupPlanes(struct stifb_info *fb)
  435. {
  436. CRX24_SETUP_RAMDAC(fb);
  437. /* replacement for: SETUP_FB(fb, CRX24_OVERLAY_PLANES); */
  438. WRITE_WORD(0x83000300, fb, REG_14);
  439. SETUP_HW(fb);
  440. WRITE_BYTE(1, fb, REG_16b1);
  441. fb_memset((void*)fb->info.fix.smem_start, 0xff,
  442. fb->info.var.yres*fb->info.fix.line_length);
  443. CRX24_SET_OVLY_MASK(fb);
  444. SETUP_FB(fb);
  445. }
  446. #define HYPER_CMAP_TYPE 0
  447. #define NGLE_CMAP_INDEXED0_TYPE 0
  448. #define NGLE_CMAP_OVERLAY_TYPE 3
  449. /* typedef of LUT (Colormap) BLT Control Register */
  450. typedef union /* Note assumption that fields are packed left-to-right */
  451. { u32 all;
  452. struct
  453. {
  454. unsigned enable : 1;
  455. unsigned waitBlank : 1;
  456. unsigned reserved1 : 4;
  457. unsigned lutOffset : 10; /* Within destination LUT */
  458. unsigned lutType : 2; /* Cursor, image, overlay */
  459. unsigned reserved2 : 4;
  460. unsigned length : 10;
  461. } fields;
  462. } NgleLutBltCtl;
  463. #if 0
  464. static NgleLutBltCtl
  465. setNgleLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
  466. {
  467. NgleLutBltCtl lutBltCtl;
  468. /* set enable, zero reserved fields */
  469. lutBltCtl.all = 0x80000000;
  470. lutBltCtl.fields.length = length;
  471. switch (fb->id)
  472. {
  473. case S9000_ID_A1439A: /* CRX24 */
  474. if (fb->var.bits_per_pixel == 8) {
  475. lutBltCtl.fields.lutType = NGLE_CMAP_OVERLAY_TYPE;
  476. lutBltCtl.fields.lutOffset = 0;
  477. } else {
  478. lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
  479. lutBltCtl.fields.lutOffset = 0 * 256;
  480. }
  481. break;
  482. case S9000_ID_ARTIST:
  483. lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
  484. lutBltCtl.fields.lutOffset = 0 * 256;
  485. break;
  486. default:
  487. lutBltCtl.fields.lutType = NGLE_CMAP_INDEXED0_TYPE;
  488. lutBltCtl.fields.lutOffset = 0;
  489. break;
  490. }
  491. /* Offset points to start of LUT. Adjust for within LUT */
  492. lutBltCtl.fields.lutOffset += offsetWithinLut;
  493. return lutBltCtl;
  494. }
  495. #endif
  496. static NgleLutBltCtl
  497. setHyperLutBltCtl(struct stifb_info *fb, int offsetWithinLut, int length)
  498. {
  499. NgleLutBltCtl lutBltCtl;
  500. /* set enable, zero reserved fields */
  501. lutBltCtl.all = 0x80000000;
  502. lutBltCtl.fields.length = length;
  503. lutBltCtl.fields.lutType = HYPER_CMAP_TYPE;
  504. /* Expect lutIndex to be 0 or 1 for image cmaps, 2 or 3 for overlay cmaps */
  505. if (fb->info.var.bits_per_pixel == 8)
  506. lutBltCtl.fields.lutOffset = 2 * 256;
  507. else
  508. lutBltCtl.fields.lutOffset = 0 * 256;
  509. /* Offset points to start of LUT. Adjust for within LUT */
  510. lutBltCtl.fields.lutOffset += offsetWithinLut;
  511. return lutBltCtl;
  512. }
  513. static void hyperUndoITE(struct stifb_info *fb)
  514. {
  515. int nFreeFifoSlots = 0;
  516. u32 fbAddr;
  517. NGLE_LOCK(fb);
  518. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 1);
  519. WRITE_WORD(0xffffffff, fb, REG_32);
  520. /* Write overlay transparency mask so only entry 255 is transparent */
  521. /* Hardware setup for full-depth write to "magic" location */
  522. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
  523. NGLE_QUICK_SET_DST_BM_ACCESS(fb,
  524. BA(IndexedDcd, Otc04, Ots08, AddrLong,
  525. BAJustPoint(0), BINovly, BAIndexBase(0)));
  526. NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
  527. IBOvals(RopSrc, MaskAddrOffset(0),
  528. BitmapExtent08, StaticReg(0),
  529. DataDynamic, MaskOtc, BGx(0), FGx(0)));
  530. /* Now prepare to write to the "magic" location */
  531. fbAddr = NGLE_LONG_FB_ADDRESS(0, 1532, 0);
  532. NGLE_BINC_SET_DSTADDR(fb, fbAddr);
  533. NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, 0xffffff);
  534. NGLE_BINC_SET_DSTMASK(fb, 0xffffffff);
  535. /* Finally, write a zero to clear the mask */
  536. NGLE_BINC_WRITE32(fb, 0);
  537. NGLE_UNLOCK(fb);
  538. }
  539. static void
  540. ngleDepth8_ClearImagePlanes(struct stifb_info *fb)
  541. {
  542. /* FIXME! */
  543. }
  544. static void
  545. ngleDepth24_ClearImagePlanes(struct stifb_info *fb)
  546. {
  547. /* FIXME! */
  548. }
  549. static void
  550. ngleResetAttrPlanes(struct stifb_info *fb, unsigned int ctlPlaneReg)
  551. {
  552. int nFreeFifoSlots = 0;
  553. u32 packed_dst;
  554. u32 packed_len;
  555. NGLE_LOCK(fb);
  556. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 4);
  557. NGLE_QUICK_SET_DST_BM_ACCESS(fb,
  558. BA(IndexedDcd, Otc32, OtsIndirect,
  559. AddrLong, BAJustPoint(0),
  560. BINattr, BAIndexBase(0)));
  561. NGLE_QUICK_SET_CTL_PLN_REG(fb, ctlPlaneReg);
  562. NGLE_SET_TRANSFERDATA(fb, 0xffffffff);
  563. NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
  564. IBOvals(RopSrc, MaskAddrOffset(0),
  565. BitmapExtent08, StaticReg(1),
  566. DataDynamic, MaskOtc,
  567. BGx(0), FGx(0)));
  568. packed_dst = 0;
  569. packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
  570. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
  571. NGLE_SET_DSTXY(fb, packed_dst);
  572. SET_LENXY_START_RECFILL(fb, packed_len);
  573. /*
  574. * In order to work around an ELK hardware problem (Buffy doesn't
  575. * always flush it's buffers when writing to the attribute
  576. * planes), at least 4 pixels must be written to the attribute
  577. * planes starting at (X == 1280) and (Y != to the last Y written
  578. * by BIF):
  579. */
  580. if (fb->id == S9000_ID_A1659A) { /* ELK_DEVICE_ID */
  581. /* It's safe to use scanline zero: */
  582. packed_dst = (1280 << 16);
  583. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 2);
  584. NGLE_SET_DSTXY(fb, packed_dst);
  585. packed_len = (4 << 16) | 1;
  586. SET_LENXY_START_RECFILL(fb, packed_len);
  587. } /* ELK Hardware Kludge */
  588. /**** Finally, set the Control Plane Register back to zero: ****/
  589. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 1);
  590. NGLE_QUICK_SET_CTL_PLN_REG(fb, 0);
  591. NGLE_UNLOCK(fb);
  592. }
  593. static void
  594. ngleClearOverlayPlanes(struct stifb_info *fb, int mask, int data)
  595. {
  596. int nFreeFifoSlots = 0;
  597. u32 packed_dst;
  598. u32 packed_len;
  599. NGLE_LOCK(fb);
  600. /* Hardware setup */
  601. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 8);
  602. NGLE_QUICK_SET_DST_BM_ACCESS(fb,
  603. BA(IndexedDcd, Otc04, Ots08, AddrLong,
  604. BAJustPoint(0), BINovly, BAIndexBase(0)));
  605. NGLE_SET_TRANSFERDATA(fb, 0xffffffff); /* Write foreground color */
  606. NGLE_REALLY_SET_IMAGE_FG_COLOR(fb, data);
  607. NGLE_REALLY_SET_IMAGE_PLANEMASK(fb, mask);
  608. packed_dst = 0;
  609. packed_len = (fb->info.var.xres << 16) | fb->info.var.yres;
  610. NGLE_SET_DSTXY(fb, packed_dst);
  611. /* Write zeroes to overlay planes */
  612. NGLE_QUICK_SET_IMAGE_BITMAP_OP(fb,
  613. IBOvals(RopSrc, MaskAddrOffset(0),
  614. BitmapExtent08, StaticReg(0),
  615. DataDynamic, MaskOtc, BGx(0), FGx(0)));
  616. SET_LENXY_START_RECFILL(fb, packed_len);
  617. NGLE_UNLOCK(fb);
  618. }
  619. static void
  620. hyperResetPlanes(struct stifb_info *fb, int enable)
  621. {
  622. unsigned int controlPlaneReg;
  623. NGLE_LOCK(fb);
  624. if (IS_24_DEVICE(fb))
  625. if (fb->info.var.bits_per_pixel == 32)
  626. controlPlaneReg = 0x04000F00;
  627. else
  628. controlPlaneReg = 0x00000F00; /* 0x00000800 should be enought, but lets clear all 4 bits */
  629. else
  630. controlPlaneReg = 0x00000F00; /* 0x00000100 should be enought, but lets clear all 4 bits */
  631. switch (enable) {
  632. case ENABLE:
  633. /* clear screen */
  634. if (IS_24_DEVICE(fb))
  635. ngleDepth24_ClearImagePlanes(fb);
  636. else
  637. ngleDepth8_ClearImagePlanes(fb);
  638. /* Paint attribute planes for default case.
  639. * On Hyperdrive, this means all windows using overlay cmap 0. */
  640. ngleResetAttrPlanes(fb, controlPlaneReg);
  641. /* clear overlay planes */
  642. ngleClearOverlayPlanes(fb, 0xff, 255);
  643. /**************************************************
  644. ** Also need to counteract ITE settings
  645. **************************************************/
  646. hyperUndoITE(fb);
  647. break;
  648. case DISABLE:
  649. /* clear screen */
  650. if (IS_24_DEVICE(fb))
  651. ngleDepth24_ClearImagePlanes(fb);
  652. else
  653. ngleDepth8_ClearImagePlanes(fb);
  654. ngleResetAttrPlanes(fb, controlPlaneReg);
  655. ngleClearOverlayPlanes(fb, 0xff, 0);
  656. break;
  657. case -1: /* RESET */
  658. hyperUndoITE(fb);
  659. ngleResetAttrPlanes(fb, controlPlaneReg);
  660. break;
  661. }
  662. NGLE_UNLOCK(fb);
  663. }
  664. /* Return pointer to in-memory structure holding ELK device-dependent ROM values. */
  665. static void
  666. ngleGetDeviceRomData(struct stifb_info *fb)
  667. {
  668. #if 0
  669. XXX: FIXME: !!!
  670. int *pBytePerLongDevDepData;/* data byte == LSB */
  671. int *pRomTable;
  672. NgleDevRomData *pPackedDevRomData;
  673. int sizePackedDevRomData = sizeof(*pPackedDevRomData);
  674. char *pCard8;
  675. int i;
  676. char *mapOrigin = NULL;
  677. int romTableIdx;
  678. pPackedDevRomData = fb->ngle_rom;
  679. SETUP_HW(fb);
  680. if (fb->id == S9000_ID_ARTIST) {
  681. pPackedDevRomData->cursor_pipeline_delay = 4;
  682. pPackedDevRomData->video_interleaves = 4;
  683. } else {
  684. /* Get pointer to unpacked byte/long data in ROM */
  685. pBytePerLongDevDepData = fb->sti->regions[NGLEDEVDEPROM_CRT_REGION];
  686. /* Tomcat supports several resolutions: 1280x1024, 1024x768, 640x480 */
  687. if (fb->id == S9000_ID_TOMCAT)
  688. {
  689. /* jump to the correct ROM table */
  690. GET_ROMTABLE_INDEX(romTableIdx);
  691. while (romTableIdx > 0)
  692. {
  693. pCard8 = (Card8 *) pPackedDevRomData;
  694. pRomTable = pBytePerLongDevDepData;
  695. /* Pack every fourth byte from ROM into structure */
  696. for (i = 0; i < sizePackedDevRomData; i++)
  697. {
  698. *pCard8++ = (Card8) (*pRomTable++);
  699. }
  700. pBytePerLongDevDepData = (Card32 *)
  701. ((Card8 *) pBytePerLongDevDepData +
  702. pPackedDevRomData->sizeof_ngle_data);
  703. romTableIdx--;
  704. }
  705. }
  706. pCard8 = (Card8 *) pPackedDevRomData;
  707. /* Pack every fourth byte from ROM into structure */
  708. for (i = 0; i < sizePackedDevRomData; i++)
  709. {
  710. *pCard8++ = (Card8) (*pBytePerLongDevDepData++);
  711. }
  712. }
  713. SETUP_FB(fb);
  714. #endif
  715. }
  716. #define HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES 4
  717. #define HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE 8
  718. #define HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE 10
  719. #define HYPERBOWL_MODE2_8_24 15
  720. /* HCRX specific boot-time initialization */
  721. static void __init
  722. SETUP_HCRX(struct stifb_info *fb)
  723. {
  724. int hyperbowl;
  725. int nFreeFifoSlots = 0;
  726. if (fb->id != S9000_ID_HCRX)
  727. return;
  728. /* Initialize Hyperbowl registers */
  729. GET_FIFO_SLOTS(fb, nFreeFifoSlots, 7);
  730. if (IS_24_DEVICE(fb)) {
  731. hyperbowl = (fb->info.var.bits_per_pixel == 32) ?
  732. HYPERBOWL_MODE01_8_24_LUT0_TRANSPARENT_LUT1_OPAQUE :
  733. HYPERBOWL_MODE01_8_24_LUT0_OPAQUE_LUT1_OPAQUE;
  734. /* First write to Hyperbowl must happen twice (bug) */
  735. WRITE_WORD(hyperbowl, fb, REG_40);
  736. WRITE_WORD(hyperbowl, fb, REG_40);
  737. WRITE_WORD(HYPERBOWL_MODE2_8_24, fb, REG_39);
  738. WRITE_WORD(0x014c0148, fb, REG_42); /* Set lut 0 to be the direct color */
  739. WRITE_WORD(0x404c4048, fb, REG_43);
  740. WRITE_WORD(0x034c0348, fb, REG_44);
  741. WRITE_WORD(0x444c4448, fb, REG_45);
  742. } else {
  743. hyperbowl = HYPERBOWL_MODE_FOR_8_OVER_88_LUT0_NO_TRANSPARENCIES;
  744. /* First write to Hyperbowl must happen twice (bug) */
  745. WRITE_WORD(hyperbowl, fb, REG_40);
  746. WRITE_WORD(hyperbowl, fb, REG_40);
  747. WRITE_WORD(0x00000000, fb, REG_42);
  748. WRITE_WORD(0x00000000, fb, REG_43);
  749. WRITE_WORD(0x00000000, fb, REG_44);
  750. WRITE_WORD(0x444c4048, fb, REG_45);
  751. }
  752. }
  753. /* ------------------- driver specific functions --------------------------- */
  754. static int
  755. stifb_setcolreg(u_int regno, u_int red, u_int green,
  756. u_int blue, u_int transp, struct fb_info *info)
  757. {
  758. struct stifb_info *fb = (struct stifb_info *) info;
  759. u32 color;
  760. if (regno >= NR_PALETTE)
  761. return 1;
  762. red >>= 8;
  763. green >>= 8;
  764. blue >>= 8;
  765. DEBUG_OFF();
  766. START_IMAGE_COLORMAP_ACCESS(fb);
  767. if (unlikely(fb->info.var.grayscale)) {
  768. /* gray = 0.30*R + 0.59*G + 0.11*B */
  769. color = ((red * 77) +
  770. (green * 151) +
  771. (blue * 28)) >> 8;
  772. } else {
  773. color = ((red << 16) |
  774. (green << 8) |
  775. (blue));
  776. }
  777. if (fb->info.fix.visual == FB_VISUAL_DIRECTCOLOR) {
  778. struct fb_var_screeninfo *var = &fb->info.var;
  779. if (regno < 16)
  780. ((u32 *)fb->info.pseudo_palette)[regno] =
  781. regno << var->red.offset |
  782. regno << var->green.offset |
  783. regno << var->blue.offset;
  784. }
  785. WRITE_IMAGE_COLOR(fb, regno, color);
  786. if (fb->id == S9000_ID_HCRX) {
  787. NgleLutBltCtl lutBltCtl;
  788. lutBltCtl = setHyperLutBltCtl(fb,
  789. 0, /* Offset w/i LUT */
  790. 256); /* Load entire LUT */
  791. NGLE_BINC_SET_SRCADDR(fb,
  792. NGLE_LONG_FB_ADDRESS(0, 0x100, 0));
  793. /* 0x100 is same as used in WRITE_IMAGE_COLOR() */
  794. START_COLORMAPLOAD(fb, lutBltCtl.all);
  795. SETUP_FB(fb);
  796. } else {
  797. /* cleanup colormap hardware */
  798. FINISH_IMAGE_COLORMAP_ACCESS(fb);
  799. }
  800. DEBUG_ON();
  801. return 0;
  802. }
  803. static int
  804. stifb_blank(int blank_mode, struct fb_info *info)
  805. {
  806. struct stifb_info *fb = (struct stifb_info *) info;
  807. int enable = (blank_mode == 0) ? ENABLE : DISABLE;
  808. switch (fb->id) {
  809. case S9000_ID_A1439A:
  810. CRX24_ENABLE_DISABLE_DISPLAY(fb, enable);
  811. break;
  812. case CRT_ID_VISUALIZE_EG:
  813. case S9000_ID_ARTIST:
  814. ARTIST_ENABLE_DISABLE_DISPLAY(fb, enable);
  815. break;
  816. case S9000_ID_HCRX:
  817. HYPER_ENABLE_DISABLE_DISPLAY(fb, enable);
  818. break;
  819. case S9000_ID_A1659A: /* fall through */
  820. case S9000_ID_TIMBER:
  821. case CRX24_OVERLAY_PLANES:
  822. default:
  823. ENABLE_DISABLE_DISPLAY(fb, enable);
  824. break;
  825. }
  826. SETUP_FB(fb);
  827. return 0;
  828. }
  829. static void __init
  830. stifb_init_display(struct stifb_info *fb)
  831. {
  832. int id = fb->id;
  833. SETUP_FB(fb);
  834. /* HCRX specific initialization */
  835. SETUP_HCRX(fb);
  836. /*
  837. if (id == S9000_ID_HCRX)
  838. hyperInitSprite(fb);
  839. else
  840. ngleInitSprite(fb);
  841. */
  842. /* Initialize the image planes. */
  843. switch (id) {
  844. case S9000_ID_HCRX:
  845. hyperResetPlanes(fb, ENABLE);
  846. break;
  847. case S9000_ID_A1439A:
  848. rattlerSetupPlanes(fb);
  849. break;
  850. case S9000_ID_A1659A:
  851. case S9000_ID_ARTIST:
  852. case CRT_ID_VISUALIZE_EG:
  853. elkSetupPlanes(fb);
  854. break;
  855. }
  856. /* Clear attribute planes on non HCRX devices. */
  857. switch (id) {
  858. case S9000_ID_A1659A:
  859. case S9000_ID_A1439A:
  860. if (fb->info.var.bits_per_pixel == 32)
  861. ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
  862. else {
  863. ngleSetupAttrPlanes(fb, BUFF1_CMAP0);
  864. }
  865. if (id == S9000_ID_A1439A)
  866. ngleClearOverlayPlanes(fb, 0xff, 0);
  867. break;
  868. case S9000_ID_ARTIST:
  869. case CRT_ID_VISUALIZE_EG:
  870. if (fb->info.var.bits_per_pixel == 32)
  871. ngleSetupAttrPlanes(fb, BUFF1_CMAP3);
  872. else {
  873. ngleSetupAttrPlanes(fb, ARTIST_CMAP0);
  874. }
  875. break;
  876. }
  877. stifb_blank(0, (struct fb_info *)fb); /* 0=enable screen */
  878. SETUP_FB(fb);
  879. }
  880. /* ------------ Interfaces to hardware functions ------------ */
  881. static struct fb_ops stifb_ops = {
  882. .owner = THIS_MODULE,
  883. .fb_setcolreg = stifb_setcolreg,
  884. .fb_blank = stifb_blank,
  885. .fb_fillrect = cfb_fillrect,
  886. .fb_copyarea = cfb_copyarea,
  887. .fb_imageblit = cfb_imageblit,
  888. };
  889. /*
  890. * Initialization
  891. */
  892. int __init
  893. stifb_init_fb(struct sti_struct *sti, int bpp_pref)
  894. {
  895. struct fb_fix_screeninfo *fix;
  896. struct fb_var_screeninfo *var;
  897. struct stifb_info *fb;
  898. struct fb_info *info;
  899. unsigned long sti_rom_address;
  900. char *dev_name;
  901. int bpp, xres, yres;
  902. fb = kzalloc(sizeof(*fb), GFP_ATOMIC);
  903. if (!fb) {
  904. printk(KERN_ERR "stifb: Could not allocate stifb structure\n");
  905. return -ENODEV;
  906. }
  907. info = &fb->info;
  908. /* set struct to a known state */
  909. fix = &info->fix;
  910. var = &info->var;
  911. fb->sti = sti;
  912. /* store upper 32bits of the graphics id */
  913. fb->id = fb->sti->graphics_id[0];
  914. /* only supported cards are allowed */
  915. switch (fb->id) {
  916. case CRT_ID_VISUALIZE_EG:
  917. /* look for a double buffering device like e.g. the
  918. "INTERNAL_EG_DX1024" in the RDI precisionbook laptop
  919. which won't work. The same device in non-double
  920. buffering mode returns "INTERNAL_EG_X1024". */
  921. if (strstr(sti->outptr.dev_name, "EG_DX")) {
  922. printk(KERN_WARNING
  923. "stifb: ignoring '%s'. Disable double buffering in IPL menu.\n",
  924. sti->outptr.dev_name);
  925. goto out_err0;
  926. }
  927. /* fall though */
  928. case S9000_ID_ARTIST:
  929. case S9000_ID_HCRX:
  930. case S9000_ID_TIMBER:
  931. case S9000_ID_A1659A:
  932. case S9000_ID_A1439A:
  933. break;
  934. default:
  935. printk(KERN_WARNING "stifb: '%s' (id: 0x%08x) not supported.\n",
  936. sti->outptr.dev_name, fb->id);
  937. goto out_err0;
  938. }
  939. /* default to 8 bpp on most graphic chips */
  940. bpp = 8;
  941. xres = sti_onscreen_x(fb->sti);
  942. yres = sti_onscreen_y(fb->sti);
  943. ngleGetDeviceRomData(fb);
  944. /* get (virtual) io region base addr */
  945. fix->mmio_start = REGION_BASE(fb,2);
  946. fix->mmio_len = 0x400000;
  947. /* Reject any device not in the NGLE family */
  948. switch (fb->id) {
  949. case S9000_ID_A1659A: /* CRX/A1659A */
  950. break;
  951. case S9000_ID_ELM: /* GRX, grayscale but else same as A1659A */
  952. var->grayscale = 1;
  953. fb->id = S9000_ID_A1659A;
  954. break;
  955. case S9000_ID_TIMBER: /* HP9000/710 Any (may be a grayscale device) */
  956. dev_name = fb->sti->outptr.dev_name;
  957. if (strstr(dev_name, "GRAYSCALE") ||
  958. strstr(dev_name, "Grayscale") ||
  959. strstr(dev_name, "grayscale"))
  960. var->grayscale = 1;
  961. break;
  962. case S9000_ID_TOMCAT: /* Dual CRX, behaves else like a CRX */
  963. /* FIXME: TomCat supports two heads:
  964. * fb.iobase = REGION_BASE(fb_info,3);
  965. * fb.screen_base = ioremap_nocache(REGION_BASE(fb_info,2),xxx);
  966. * for now we only support the left one ! */
  967. xres = fb->ngle_rom.x_size_visible;
  968. yres = fb->ngle_rom.y_size_visible;
  969. fb->id = S9000_ID_A1659A;
  970. break;
  971. case S9000_ID_A1439A: /* CRX24/A1439A */
  972. bpp = 32;
  973. break;
  974. case S9000_ID_HCRX: /* Hyperdrive/HCRX */
  975. memset(&fb->ngle_rom, 0, sizeof(fb->ngle_rom));
  976. if ((fb->sti->regions_phys[0] & 0xfc000000) ==
  977. (fb->sti->regions_phys[2] & 0xfc000000))
  978. sti_rom_address = F_EXTEND(fb->sti->regions_phys[0]);
  979. else
  980. sti_rom_address = F_EXTEND(fb->sti->regions_phys[1]);
  981. fb->deviceSpecificConfig = gsc_readl(sti_rom_address);
  982. if (IS_24_DEVICE(fb)) {
  983. if (bpp_pref == 8 || bpp_pref == 32)
  984. bpp = bpp_pref;
  985. else
  986. bpp = 32;
  987. } else
  988. bpp = 8;
  989. READ_WORD(fb, REG_15);
  990. SETUP_HW(fb);
  991. break;
  992. case CRT_ID_VISUALIZE_EG:
  993. case S9000_ID_ARTIST: /* Artist */
  994. break;
  995. default:
  996. #ifdef FALLBACK_TO_1BPP
  997. printk(KERN_WARNING
  998. "stifb: Unsupported graphics card (id=0x%08x) "
  999. "- now trying 1bpp mode instead\n",
  1000. fb->id);
  1001. bpp = 1; /* default to 1 bpp */
  1002. break;
  1003. #else
  1004. printk(KERN_WARNING
  1005. "stifb: Unsupported graphics card (id=0x%08x) "
  1006. "- skipping.\n",
  1007. fb->id);
  1008. goto out_err0;
  1009. #endif
  1010. }
  1011. /* get framebuffer physical and virtual base addr & len (64bit ready) */
  1012. fix->smem_start = F_EXTEND(fb->sti->regions_phys[1]);
  1013. fix->smem_len = fb->sti->regions[1].region_desc.length * 4096;
  1014. fix->line_length = (fb->sti->glob_cfg->total_x * bpp) / 8;
  1015. if (!fix->line_length)
  1016. fix->line_length = 2048; /* default */
  1017. /* limit fbsize to max visible screen size */
  1018. if (fix->smem_len > yres*fix->line_length)
  1019. fix->smem_len = yres*fix->line_length;
  1020. fix->accel = FB_ACCEL_NONE;
  1021. switch (bpp) {
  1022. case 1:
  1023. fix->type = FB_TYPE_PLANES; /* well, sort of */
  1024. fix->visual = FB_VISUAL_MONO10;
  1025. var->red.length = var->green.length = var->blue.length = 1;
  1026. break;
  1027. case 8:
  1028. fix->type = FB_TYPE_PACKED_PIXELS;
  1029. fix->visual = FB_VISUAL_PSEUDOCOLOR;
  1030. var->red.length = var->green.length = var->blue.length = 8;
  1031. break;
  1032. case 32:
  1033. fix->type = FB_TYPE_PACKED_PIXELS;
  1034. fix->visual = FB_VISUAL_DIRECTCOLOR;
  1035. var->red.length = var->green.length = var->blue.length = var->transp.length = 8;
  1036. var->blue.offset = 0;
  1037. var->green.offset = 8;
  1038. var->red.offset = 16;
  1039. var->transp.offset = 24;
  1040. break;
  1041. default:
  1042. break;
  1043. }
  1044. var->xres = var->xres_virtual = xres;
  1045. var->yres = var->yres_virtual = yres;
  1046. var->bits_per_pixel = bpp;
  1047. strcpy(fix->id, "stifb");
  1048. info->fbops = &stifb_ops;
  1049. info->screen_base = ioremap_nocache(REGION_BASE(fb,1), fix->smem_len);
  1050. info->screen_size = fix->smem_len;
  1051. info->flags = FBINFO_DEFAULT;
  1052. info->pseudo_palette = &fb->pseudo_palette;
  1053. /* This has to been done !!! */
  1054. fb_alloc_cmap(&info->cmap, NR_PALETTE, 0);
  1055. stifb_init_display(fb);
  1056. if (!request_mem_region(fix->smem_start, fix->smem_len, "stifb fb")) {
  1057. printk(KERN_ERR "stifb: cannot reserve fb region 0x%04lx-0x%04lx\n",
  1058. fix->smem_start, fix->smem_start+fix->smem_len);
  1059. goto out_err1;
  1060. }
  1061. if (!request_mem_region(fix->mmio_start, fix->mmio_len, "stifb mmio")) {
  1062. printk(KERN_ERR "stifb: cannot reserve sti mmio region 0x%04lx-0x%04lx\n",
  1063. fix->mmio_start, fix->mmio_start+fix->mmio_len);
  1064. goto out_err2;
  1065. }
  1066. if (register_framebuffer(&fb->info) < 0)
  1067. goto out_err3;
  1068. sti->info = info; /* save for unregister_framebuffer() */
  1069. printk(KERN_INFO
  1070. "fb%d: %s %dx%d-%d frame buffer device, %s, id: %04x, mmio: 0x%04lx\n",
  1071. fb->info.node,
  1072. fix->id,
  1073. var->xres,
  1074. var->yres,
  1075. var->bits_per_pixel,
  1076. sti->outptr.dev_name,
  1077. fb->id,
  1078. fix->mmio_start);
  1079. return 0;
  1080. out_err3:
  1081. release_mem_region(fix->mmio_start, fix->mmio_len);
  1082. out_err2:
  1083. release_mem_region(fix->smem_start, fix->smem_len);
  1084. out_err1:
  1085. iounmap(info->screen_base);
  1086. fb_dealloc_cmap(&info->cmap);
  1087. out_err0:
  1088. kfree(fb);
  1089. return -ENXIO;
  1090. }
  1091. static int stifb_disabled __initdata;
  1092. int __init
  1093. stifb_setup(char *options);
  1094. int __init
  1095. stifb_init(void)
  1096. {
  1097. struct sti_struct *sti;
  1098. struct sti_struct *def_sti;
  1099. int i;
  1100. #ifndef MODULE
  1101. char *option = NULL;
  1102. if (fb_get_options("stifb", &option))
  1103. return -ENODEV;
  1104. stifb_setup(option);
  1105. #endif
  1106. if (stifb_disabled) {
  1107. printk(KERN_INFO "stifb: disabled by \"stifb=off\" kernel parameter\n");
  1108. return -ENXIO;
  1109. }
  1110. def_sti = sti_get_rom(0);
  1111. if (def_sti) {
  1112. for (i = 1; i <= MAX_STI_ROMS; i++) {
  1113. sti = sti_get_rom(i);
  1114. if (!sti)
  1115. break;
  1116. if (sti == def_sti) {
  1117. stifb_init_fb(sti, stifb_bpp_pref[i - 1]);
  1118. break;
  1119. }
  1120. }
  1121. }
  1122. for (i = 1; i <= MAX_STI_ROMS; i++) {
  1123. sti = sti_get_rom(i);
  1124. if (!sti)
  1125. break;
  1126. if (sti == def_sti)
  1127. continue;
  1128. stifb_init_fb(sti, stifb_bpp_pref[i - 1]);
  1129. }
  1130. return 0;
  1131. }
  1132. /*
  1133. * Cleanup
  1134. */
  1135. static void __exit
  1136. stifb_cleanup(void)
  1137. {
  1138. struct sti_struct *sti;
  1139. int i;
  1140. for (i = 1; i <= MAX_STI_ROMS; i++) {
  1141. sti = sti_get_rom(i);
  1142. if (!sti)
  1143. break;
  1144. if (sti->info) {
  1145. struct fb_info *info = sti->info;
  1146. unregister_framebuffer(sti->info);
  1147. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  1148. release_mem_region(info->fix.smem_start, info->fix.smem_len);
  1149. if (info->screen_base)
  1150. iounmap(info->screen_base);
  1151. fb_dealloc_cmap(&info->cmap);
  1152. kfree(info);
  1153. }
  1154. sti->info = NULL;
  1155. }
  1156. }
  1157. int __init
  1158. stifb_setup(char *options)
  1159. {
  1160. int i;
  1161. if (!options || !*options)
  1162. return 1;
  1163. if (strncmp(options, "off", 3) == 0) {
  1164. stifb_disabled = 1;
  1165. options += 3;
  1166. }
  1167. if (strncmp(options, "bpp", 3) == 0) {
  1168. options += 3;
  1169. for (i = 0; i < MAX_STI_ROMS; i++) {
  1170. if (*options++ != ':')
  1171. break;
  1172. stifb_bpp_pref[i] = simple_strtoul(options, &options, 10);
  1173. }
  1174. }
  1175. return 1;
  1176. }
  1177. __setup("stifb=", stifb_setup);
  1178. module_init(stifb_init);
  1179. module_exit(stifb_cleanup);
  1180. MODULE_AUTHOR("Helge Deller <deller@gmx.de>, Thomas Bogendoerfer <tsbogend@alpha.franken.de>");
  1181. MODULE_DESCRIPTION("Framebuffer driver for HP's NGLE series graphics cards in HP PARISC machines");
  1182. MODULE_LICENSE("GPL v2");