sstfb.c 44 KB

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  1. /*
  2. * linux/drivers/video/sstfb.c -- voodoo graphics frame buffer
  3. *
  4. * Copyright (c) 2000-2002 Ghozlane Toumi <gtoumi@laposte.net>
  5. *
  6. * Created 15 Jan 2000 by Ghozlane Toumi
  7. *
  8. * Contributions (and many thanks) :
  9. *
  10. * 03/2001 James Simmons <jsimmons@infradead.org>
  11. * 04/2001 Paul Mundt <lethal@chaoticdreams.org>
  12. * 05/2001 Urs Ganse <ursg@uni.de>
  13. * (initial work on voodoo2 port, interlace)
  14. * 09/2002 Helge Deller <deller@gmx.de>
  15. * (enable driver on big-endian machines (hppa), ioctl fixes)
  16. * 12/2002 Helge Deller <deller@gmx.de>
  17. * (port driver to new frambuffer infrastructure)
  18. * 01/2003 Helge Deller <deller@gmx.de>
  19. * (initial work on fb hardware acceleration for voodoo2)
  20. * 08/2006 Alan Cox <alan@redhat.com>
  21. * Remove never finished and bogus 24/32bit support
  22. * Clean up macro abuse
  23. * Minor tidying for format.
  24. * 12/2006 Helge Deller <deller@gmx.de>
  25. * add /sys/class/graphics/fbX/vgapass sysfs-interface
  26. * add module option "mode_option" to set initial screen mode
  27. * use fbdev default videomode database
  28. * remove debug functions from ioctl
  29. */
  30. /*
  31. * The voodoo1 has the following memory mapped address space:
  32. * 0x000000 - 0x3fffff : registers (4MB)
  33. * 0x400000 - 0x7fffff : linear frame buffer (4MB)
  34. * 0x800000 - 0xffffff : texture memory (8MB)
  35. */
  36. /*
  37. * misc notes, TODOs, toASKs, and deep thoughts
  38. -TODO: at one time or another test that the mode is acceptable by the monitor
  39. -ASK: Can I choose different ordering for the color bitfields (rgba argb ...)
  40. which one should i use ? is there any preferred one ? It seems ARGB is
  41. the one ...
  42. -TODO: in set_var check the validity of timings (hsync vsync)...
  43. -TODO: check and recheck the use of sst_wait_idle : we don't flush the fifo via
  44. a nop command. so it's ok as long as the commands we pass don't go
  45. through the fifo. warning: issuing a nop command seems to need pci_fifo
  46. -FIXME: in case of failure in the init sequence, be sure we return to a safe
  47. state.
  48. - FIXME: Use accelerator for 2D scroll
  49. -FIXME: 4MB boards have banked memory (FbiInit2 bits 1 & 20)
  50. */
  51. /*
  52. * debug info
  53. * SST_DEBUG : enable debugging
  54. * SST_DEBUG_REG : debug registers
  55. * 0 : no debug
  56. * 1 : dac calls, [un]set_bits, FbiInit
  57. * 2 : insane debug level (log every register read/write)
  58. * SST_DEBUG_FUNC : functions
  59. * 0 : no debug
  60. * 1 : function call / debug ioctl
  61. * 2 : variables
  62. * 3 : flood . you don't want to do that. trust me.
  63. * SST_DEBUG_VAR : debug display/var structs
  64. * 0 : no debug
  65. * 1 : dumps display, fb_var
  66. *
  67. * sstfb specific ioctls:
  68. * toggle vga (0x46db) : toggle vga_pass_through
  69. */
  70. #undef SST_DEBUG
  71. /*
  72. * Includes
  73. */
  74. #include <linux/string.h>
  75. #include <linux/kernel.h>
  76. #include <linux/module.h>
  77. #include <linux/fb.h>
  78. #include <linux/pci.h>
  79. #include <linux/delay.h>
  80. #include <linux/init.h>
  81. #include <linux/slab.h>
  82. #include <asm/io.h>
  83. #include <asm/uaccess.h>
  84. #include <video/sstfb.h>
  85. /* initialized by setup */
  86. static int vgapass; /* enable VGA passthrough cable */
  87. static int mem; /* mem size in MB, 0 = autodetect */
  88. static int clipping = 1; /* use clipping (slower, safer) */
  89. static int gfxclk; /* force FBI freq in Mhz . Dangerous */
  90. static int slowpci; /* slow PCI settings */
  91. /*
  92. Possible default video modes: 800x600@60, 640x480@75, 1024x768@76, 640x480@60
  93. */
  94. #define DEFAULT_VIDEO_MODE "640x480@60"
  95. static char *mode_option __devinitdata = DEFAULT_VIDEO_MODE;
  96. enum {
  97. ID_VOODOO1 = 0,
  98. ID_VOODOO2 = 1,
  99. };
  100. #define IS_VOODOO2(par) ((par)->type == ID_VOODOO2)
  101. static struct sst_spec voodoo_spec[] __devinitdata = {
  102. { .name = "Voodoo Graphics", .default_gfx_clock = 50000, .max_gfxclk = 60 },
  103. { .name = "Voodoo2", .default_gfx_clock = 75000, .max_gfxclk = 85 },
  104. };
  105. /*
  106. * debug functions
  107. */
  108. #if (SST_DEBUG_REG > 0)
  109. static void sst_dbg_print_read_reg(u32 reg, u32 val) {
  110. const char *regname;
  111. switch (reg) {
  112. case FBIINIT0: regname = "FbiInit0"; break;
  113. case FBIINIT1: regname = "FbiInit1"; break;
  114. case FBIINIT2: regname = "FbiInit2"; break;
  115. case FBIINIT3: regname = "FbiInit3"; break;
  116. case FBIINIT4: regname = "FbiInit4"; break;
  117. case FBIINIT5: regname = "FbiInit5"; break;
  118. case FBIINIT6: regname = "FbiInit6"; break;
  119. default: regname = NULL; break;
  120. }
  121. if (regname == NULL)
  122. r_ddprintk("sst_read(%#x): %#x\n", reg, val);
  123. else
  124. r_dprintk(" sst_read(%s): %#x\n", regname, val);
  125. }
  126. static void sst_dbg_print_write_reg(u32 reg, u32 val) {
  127. const char *regname;
  128. switch (reg) {
  129. case FBIINIT0: regname = "FbiInit0"; break;
  130. case FBIINIT1: regname = "FbiInit1"; break;
  131. case FBIINIT2: regname = "FbiInit2"; break;
  132. case FBIINIT3: regname = "FbiInit3"; break;
  133. case FBIINIT4: regname = "FbiInit4"; break;
  134. case FBIINIT5: regname = "FbiInit5"; break;
  135. case FBIINIT6: regname = "FbiInit6"; break;
  136. default: regname = NULL; break;
  137. }
  138. if (regname == NULL)
  139. r_ddprintk("sst_write(%#x, %#x)\n", reg, val);
  140. else
  141. r_dprintk(" sst_write(%s, %#x)\n", regname, val);
  142. }
  143. #else /* (SST_DEBUG_REG > 0) */
  144. # define sst_dbg_print_read_reg(reg, val) do {} while(0)
  145. # define sst_dbg_print_write_reg(reg, val) do {} while(0)
  146. #endif /* (SST_DEBUG_REG > 0) */
  147. /*
  148. * hardware access functions
  149. */
  150. /* register access */
  151. #define sst_read(reg) __sst_read(par->mmio_vbase, reg)
  152. #define sst_write(reg,val) __sst_write(par->mmio_vbase, reg, val)
  153. #define sst_set_bits(reg,val) __sst_set_bits(par->mmio_vbase, reg, val)
  154. #define sst_unset_bits(reg,val) __sst_unset_bits(par->mmio_vbase, reg, val)
  155. #define sst_dac_read(reg) __sst_dac_read(par->mmio_vbase, reg)
  156. #define sst_dac_write(reg,val) __sst_dac_write(par->mmio_vbase, reg, val)
  157. #define dac_i_read(reg) __dac_i_read(par->mmio_vbase, reg)
  158. #define dac_i_write(reg,val) __dac_i_write(par->mmio_vbase, reg, val)
  159. static inline u32 __sst_read(u8 __iomem *vbase, u32 reg)
  160. {
  161. u32 ret = readl(vbase + reg);
  162. sst_dbg_print_read_reg(reg, ret);
  163. return ret;
  164. }
  165. static inline void __sst_write(u8 __iomem *vbase, u32 reg, u32 val)
  166. {
  167. sst_dbg_print_write_reg(reg, val);
  168. writel(val, vbase + reg);
  169. }
  170. static inline void __sst_set_bits(u8 __iomem *vbase, u32 reg, u32 val)
  171. {
  172. r_dprintk("sst_set_bits(%#x, %#x)\n", reg, val);
  173. __sst_write(vbase, reg, __sst_read(vbase, reg) | val);
  174. }
  175. static inline void __sst_unset_bits(u8 __iomem *vbase, u32 reg, u32 val)
  176. {
  177. r_dprintk("sst_unset_bits(%#x, %#x)\n", reg, val);
  178. __sst_write(vbase, reg, __sst_read(vbase, reg) & ~val);
  179. }
  180. /*
  181. * wait for the fbi chip. ASK: what happens if the fbi is stuck ?
  182. *
  183. * the FBI is supposed to be ready if we receive 5 time
  184. * in a row a "idle" answer to our requests
  185. */
  186. #define sst_wait_idle() __sst_wait_idle(par->mmio_vbase)
  187. static int __sst_wait_idle(u8 __iomem *vbase)
  188. {
  189. int count = 0;
  190. /* if (doFBINOP) __sst_write(vbase, NOPCMD, 0); */
  191. while(1) {
  192. if (__sst_read(vbase, STATUS) & STATUS_FBI_BUSY) {
  193. f_dddprintk("status: busy\n");
  194. /* FIXME basicaly, this is a busy wait. maybe not that good. oh well;
  195. * this is a small loop after all.
  196. * Or maybe we should use mdelay() or udelay() here instead ? */
  197. count = 0;
  198. } else {
  199. count++;
  200. f_dddprintk("status: idle(%d)\n", count);
  201. }
  202. if (count >= 5) return 1;
  203. /* XXX do something to avoid hanging the machine if the voodoo is out */
  204. }
  205. }
  206. /* dac access */
  207. /* dac_read should be remaped to FbiInit2 (via the pci reg init_enable) */
  208. static u8 __sst_dac_read(u8 __iomem *vbase, u8 reg)
  209. {
  210. u8 ret;
  211. reg &= 0x07;
  212. __sst_write(vbase, DAC_DATA, ((u32)reg << 8) | DAC_READ_CMD );
  213. __sst_wait_idle(vbase);
  214. /* udelay(10); */
  215. ret = __sst_read(vbase, DAC_READ) & 0xff;
  216. r_dprintk("sst_dac_read(%#x): %#x\n", reg, ret);
  217. return ret;
  218. }
  219. static void __sst_dac_write(u8 __iomem *vbase, u8 reg, u8 val)
  220. {
  221. r_dprintk("sst_dac_write(%#x, %#x)\n", reg, val);
  222. reg &= 0x07;
  223. __sst_write(vbase, DAC_DATA,(((u32)reg << 8)) | (u32)val);
  224. __sst_wait_idle(vbase);
  225. }
  226. /* indexed access to ti/att dacs */
  227. static u32 __dac_i_read(u8 __iomem *vbase, u8 reg)
  228. {
  229. u32 ret;
  230. __sst_dac_write(vbase, DACREG_ADDR_I, reg);
  231. ret = __sst_dac_read(vbase, DACREG_DATA_I);
  232. r_dprintk("sst_dac_read_i(%#x): %#x\n", reg, ret);
  233. return ret;
  234. }
  235. static void __dac_i_write(u8 __iomem *vbase, u8 reg,u8 val)
  236. {
  237. r_dprintk("sst_dac_write_i(%#x, %#x)\n", reg, val);
  238. __sst_dac_write(vbase, DACREG_ADDR_I, reg);
  239. __sst_dac_write(vbase, DACREG_DATA_I, val);
  240. }
  241. /* compute the m,n,p , returns the real freq
  242. * (ics datasheet : N <-> N1 , P <-> N2)
  243. *
  244. * Fout= Fref * (M+2)/( 2^P * (N+2))
  245. * we try to get close to the asked freq
  246. * with P as high, and M as low as possible
  247. * range:
  248. * ti/att : 0 <= M <= 255; 0 <= P <= 3; 0<= N <= 63
  249. * ics : 1 <= M <= 127; 0 <= P <= 3; 1<= N <= 31
  250. * we'll use the lowest limitation, should be precise enouth
  251. */
  252. static int sst_calc_pll(const int freq, int *freq_out, struct pll_timing *t)
  253. {
  254. int m, m2, n, p, best_err, fout;
  255. int best_n = -1;
  256. int best_m = -1;
  257. best_err = freq;
  258. p = 3;
  259. /* f * 2^P = vco should be less than VCOmax ~ 250 MHz for ics*/
  260. while (((1 << p) * freq > VCO_MAX) && (p >= 0))
  261. p--;
  262. if (p == -1)
  263. return -EINVAL;
  264. for (n = 1; n < 32; n++) {
  265. /* calc 2 * m so we can round it later*/
  266. m2 = (2 * freq * (1 << p) * (n + 2) ) / DAC_FREF - 4 ;
  267. m = (m2 % 2 ) ? m2/2+1 : m2/2 ;
  268. if (m >= 128)
  269. break;
  270. fout = (DAC_FREF * (m + 2)) / ((1 << p) * (n + 2));
  271. if ((abs(fout - freq) < best_err) && (m > 0)) {
  272. best_n = n;
  273. best_m = m;
  274. best_err = abs(fout - freq);
  275. /* we get the lowest m , allowing 0.5% error in freq*/
  276. if (200*best_err < freq) break;
  277. }
  278. }
  279. if (best_n == -1) /* unlikely, but who knows ? */
  280. return -EINVAL;
  281. t->p = p;
  282. t->n = best_n;
  283. t->m = best_m;
  284. *freq_out = (DAC_FREF * (t->m + 2)) / ((1 << t->p) * (t->n + 2));
  285. f_ddprintk ("m: %d, n: %d, p: %d, F: %dKhz\n",
  286. t->m, t->n, t->p, *freq_out);
  287. return 0;
  288. }
  289. /*
  290. * clear lfb screen
  291. */
  292. static void sstfb_clear_screen(struct fb_info *info)
  293. {
  294. /* clear screen */
  295. fb_memset(info->screen_base, 0, info->fix.smem_len);
  296. }
  297. /**
  298. * sstfb_check_var - Optional function. Validates a var passed in.
  299. * @var: frame buffer variable screen structure
  300. * @info: frame buffer structure that represents a single frame buffer
  301. *
  302. * Limit to the abilities of a single chip as SLI is not supported
  303. * by this driver.
  304. */
  305. static int sstfb_check_var(struct fb_var_screeninfo *var,
  306. struct fb_info *info)
  307. {
  308. struct sstfb_par *par = info->par;
  309. int hSyncOff = var->xres + var->right_margin + var->left_margin;
  310. int vSyncOff = var->yres + var->lower_margin + var->upper_margin;
  311. int vBackPorch = var->left_margin, yDim = var->yres;
  312. int vSyncOn = var->vsync_len;
  313. int tiles_in_X, real_length;
  314. unsigned int freq;
  315. if (sst_calc_pll(PICOS2KHZ(var->pixclock), &freq, &par->pll)) {
  316. printk(KERN_ERR "sstfb: Pixclock at %ld KHZ out of range\n",
  317. PICOS2KHZ(var->pixclock));
  318. return -EINVAL;
  319. }
  320. var->pixclock = KHZ2PICOS(freq);
  321. if (var->vmode & FB_VMODE_INTERLACED)
  322. vBackPorch += (vBackPorch % 2);
  323. if (var->vmode & FB_VMODE_DOUBLE) {
  324. vBackPorch <<= 1;
  325. yDim <<=1;
  326. vSyncOn <<=1;
  327. vSyncOff <<=1;
  328. }
  329. switch (var->bits_per_pixel) {
  330. case 0 ... 16 :
  331. var->bits_per_pixel = 16;
  332. break;
  333. default :
  334. printk(KERN_ERR "sstfb: Unsupported bpp %d\n", var->bits_per_pixel);
  335. return -EINVAL;
  336. }
  337. /* validity tests */
  338. if (var->xres <= 1 || yDim <= 0 || var->hsync_len <= 1 ||
  339. hSyncOff <= 1 || var->left_margin <= 2 || vSyncOn <= 0 ||
  340. vSyncOff <= 0 || vBackPorch <= 0) {
  341. return -EINVAL;
  342. }
  343. if (IS_VOODOO2(par)) {
  344. /* Voodoo 2 limits */
  345. tiles_in_X = (var->xres + 63 ) / 64 * 2;
  346. if (var->xres > POW2(11) || yDim >= POW2(11)) {
  347. printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
  348. var->xres, var->yres);
  349. return -EINVAL;
  350. }
  351. if (var->hsync_len > POW2(9) || hSyncOff > POW2(11) ||
  352. var->left_margin - 2 >= POW2(9) || vSyncOn >= POW2(13) ||
  353. vSyncOff >= POW2(13) || vBackPorch >= POW2(9) ||
  354. tiles_in_X >= POW2(6) || tiles_in_X <= 0) {
  355. printk(KERN_ERR "sstfb: Unsupported timings\n");
  356. return -EINVAL;
  357. }
  358. } else {
  359. /* Voodoo limits */
  360. tiles_in_X = (var->xres + 63 ) / 64;
  361. if (var->vmode) {
  362. printk(KERN_ERR "sstfb: Interlace/doublescan not supported %#x\n",
  363. var->vmode);
  364. return -EINVAL;
  365. }
  366. if (var->xres > POW2(10) || var->yres >= POW2(10)) {
  367. printk(KERN_ERR "sstfb: Unsupported resolution %dx%d\n",
  368. var->xres, var->yres);
  369. return -EINVAL;
  370. }
  371. if (var->hsync_len > POW2(8) || hSyncOff - 1 > POW2(10) ||
  372. var->left_margin - 2 >= POW2(8) || vSyncOn >= POW2(12) ||
  373. vSyncOff >= POW2(12) || vBackPorch >= POW2(8) ||
  374. tiles_in_X >= POW2(4) || tiles_in_X <= 0) {
  375. printk(KERN_ERR "sstfb: Unsupported timings\n");
  376. return -EINVAL;
  377. }
  378. }
  379. /* it seems that the fbi uses tiles of 64x16 pixels to "map" the mem */
  380. /* FIXME: i don't like this... looks wrong */
  381. real_length = tiles_in_X * (IS_VOODOO2(par) ? 32 : 64 )
  382. * ((var->bits_per_pixel == 16) ? 2 : 4);
  383. if (real_length * yDim > info->fix.smem_len) {
  384. printk(KERN_ERR "sstfb: Not enough video memory\n");
  385. return -ENOMEM;
  386. }
  387. var->sync &= (FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT);
  388. var->vmode &= (FB_VMODE_INTERLACED | FB_VMODE_DOUBLE);
  389. var->xoffset = 0;
  390. var->yoffset = 0;
  391. var->height = -1;
  392. var->width = -1;
  393. /*
  394. * correct the color bit fields
  395. */
  396. /* var->{red|green|blue}.msb_right = 0; */
  397. switch (var->bits_per_pixel) {
  398. case 16: /* RGB 565 LfbMode 0 */
  399. var->red.length = 5;
  400. var->green.length = 6;
  401. var->blue.length = 5;
  402. var->transp.length = 0;
  403. var->red.offset = 11;
  404. var->green.offset = 5;
  405. var->blue.offset = 0;
  406. var->transp.offset = 0;
  407. break;
  408. default:
  409. return -EINVAL;
  410. }
  411. return 0;
  412. }
  413. /**
  414. * sstfb_set_par - Optional function. Alters the hardware state.
  415. * @info: frame buffer structure that represents a single frame buffer
  416. */
  417. static int sstfb_set_par(struct fb_info *info)
  418. {
  419. struct sstfb_par *par = info->par;
  420. u32 lfbmode, fbiinit1, fbiinit2, fbiinit3, fbiinit5, fbiinit6=0;
  421. struct pci_dev *sst_dev = par->dev;
  422. unsigned int freq;
  423. int ntiles;
  424. par->hSyncOff = info->var.xres + info->var.right_margin + info->var.left_margin;
  425. par->yDim = info->var.yres;
  426. par->vSyncOn = info->var.vsync_len;
  427. par->vSyncOff = info->var.yres + info->var.lower_margin + info->var.upper_margin;
  428. par->vBackPorch = info->var.upper_margin;
  429. /* We need par->pll */
  430. sst_calc_pll(PICOS2KHZ(info->var.pixclock), &freq, &par->pll);
  431. if (info->var.vmode & FB_VMODE_INTERLACED)
  432. par->vBackPorch += (par->vBackPorch % 2);
  433. if (info->var.vmode & FB_VMODE_DOUBLE) {
  434. par->vBackPorch <<= 1;
  435. par->yDim <<=1;
  436. par->vSyncOn <<=1;
  437. par->vSyncOff <<=1;
  438. }
  439. if (IS_VOODOO2(par)) {
  440. /* voodoo2 has 32 pixel wide tiles , BUT stange things
  441. happen with odd number of tiles */
  442. par->tiles_in_X = (info->var.xres + 63 ) / 64 * 2;
  443. } else {
  444. /* voodoo1 has 64 pixels wide tiles. */
  445. par->tiles_in_X = (info->var.xres + 63 ) / 64;
  446. }
  447. f_ddprintk("hsync_len hSyncOff vsync_len vSyncOff\n");
  448. f_ddprintk("%-7d %-8d %-7d %-8d\n",
  449. info->var.hsync_len, par->hSyncOff,
  450. par->vSyncOn, par->vSyncOff);
  451. f_ddprintk("left_margin upper_margin xres yres Freq\n");
  452. f_ddprintk("%-10d %-10d %-4d %-4d %-8ld\n",
  453. info->var.left_margin, info->var.upper_margin,
  454. info->var.xres, info->var.yres, PICOS2KHZ(info->var.pixclock));
  455. sst_write(NOPCMD, 0);
  456. sst_wait_idle();
  457. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
  458. sst_set_bits(FBIINIT1, VIDEO_RESET);
  459. sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  460. sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
  461. sst_wait_idle();
  462. /*sst_unset_bits (FBIINIT0, FBI_RESET); / reenable FBI ? */
  463. sst_write(BACKPORCH, par->vBackPorch << 16 | (info->var.left_margin - 2));
  464. sst_write(VIDEODIMENSIONS, par->yDim << 16 | (info->var.xres - 1));
  465. sst_write(HSYNC, (par->hSyncOff - 1) << 16 | (info->var.hsync_len - 1));
  466. sst_write(VSYNC, par->vSyncOff << 16 | par->vSyncOn);
  467. fbiinit2 = sst_read(FBIINIT2);
  468. fbiinit3 = sst_read(FBIINIT3);
  469. /* everything is reset. we enable fbiinit2/3 remap : dac acces ok */
  470. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
  471. PCI_EN_INIT_WR | PCI_REMAP_DAC );
  472. par->dac_sw.set_vidmod(info, info->var.bits_per_pixel);
  473. /* set video clock */
  474. par->dac_sw.set_pll(info, &par->pll, VID_CLOCK);
  475. /* disable fbiinit2/3 remap */
  476. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
  477. PCI_EN_INIT_WR);
  478. /* restore fbiinit2/3 */
  479. sst_write(FBIINIT2,fbiinit2);
  480. sst_write(FBIINIT3,fbiinit3);
  481. fbiinit1 = (sst_read(FBIINIT1) & VIDEO_MASK)
  482. | EN_DATA_OE
  483. | EN_BLANK_OE
  484. | EN_HVSYNC_OE
  485. | EN_DCLK_OE
  486. /* | (15 << TILES_IN_X_SHIFT) */
  487. | SEL_INPUT_VCLK_2X
  488. /* | (2 << VCLK_2X_SEL_DEL_SHIFT)
  489. | (2 << VCLK_DEL_SHIFT) */;
  490. /* try with vclk_in_delay =0 (bits 29:30) , vclk_out_delay =0 (bits(27:28)
  491. in (near) future set them accordingly to revision + resolution (cf glide)
  492. first understand what it stands for :)
  493. FIXME: there are some artefacts... check for the vclk_in_delay
  494. lets try with 6ns delay in both vclk_out & in...
  495. doh... they're still there :\
  496. */
  497. ntiles = par->tiles_in_X;
  498. if (IS_VOODOO2(par)) {
  499. fbiinit1 |= ((ntiles & 0x20) >> 5) << TILES_IN_X_MSB_SHIFT
  500. | ((ntiles & 0x1e) >> 1) << TILES_IN_X_SHIFT;
  501. /* as the only value of importance for us in fbiinit6 is tiles in X (lsb),
  502. and as reading fbinit 6 will return crap (see FBIINIT6_DEFAULT) we just
  503. write our value. BTW due to the dac unable to read odd number of tiles, this
  504. field is always null ... */
  505. fbiinit6 = (ntiles & 0x1) << TILES_IN_X_LSB_SHIFT;
  506. }
  507. else
  508. fbiinit1 |= ntiles << TILES_IN_X_SHIFT;
  509. switch (info->var.bits_per_pixel) {
  510. case 16:
  511. fbiinit1 |= SEL_SOURCE_VCLK_2X_SEL;
  512. break;
  513. default:
  514. return -EINVAL;
  515. }
  516. sst_write(FBIINIT1, fbiinit1);
  517. if (IS_VOODOO2(par)) {
  518. sst_write(FBIINIT6, fbiinit6);
  519. fbiinit5=sst_read(FBIINIT5) & FBIINIT5_MASK ;
  520. if (info->var.vmode & FB_VMODE_INTERLACED)
  521. fbiinit5 |= INTERLACE;
  522. if (info->var.vmode & FB_VMODE_DOUBLE)
  523. fbiinit5 |= VDOUBLESCAN;
  524. if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
  525. fbiinit5 |= HSYNC_HIGH;
  526. if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
  527. fbiinit5 |= VSYNC_HIGH;
  528. sst_write(FBIINIT5, fbiinit5);
  529. }
  530. sst_wait_idle();
  531. sst_unset_bits(FBIINIT1, VIDEO_RESET);
  532. sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  533. sst_set_bits(FBIINIT2, EN_DRAM_REFRESH);
  534. /* disables fbiinit writes */
  535. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
  536. /* set lfbmode : set mode + front buffer for reads/writes
  537. + disable pipeline */
  538. switch (info->var.bits_per_pixel) {
  539. case 16:
  540. lfbmode = LFB_565;
  541. break;
  542. default:
  543. return -EINVAL;
  544. }
  545. #if defined(__BIG_ENDIAN)
  546. /* Enable byte-swizzle functionality in hardware.
  547. * With this enabled, all our read- and write-accesses to
  548. * the voodoo framebuffer can be done in native format, and
  549. * the hardware will automatically convert it to little-endian.
  550. * - tested on HP-PARISC, Helge Deller <deller@gmx.de> */
  551. lfbmode |= ( LFB_WORD_SWIZZLE_WR | LFB_BYTE_SWIZZLE_WR |
  552. LFB_WORD_SWIZZLE_RD | LFB_BYTE_SWIZZLE_RD );
  553. #endif
  554. if (clipping) {
  555. sst_write(LFBMODE, lfbmode | EN_PXL_PIPELINE);
  556. /*
  557. * Set "clipping" dimensions. If clipping is disabled and
  558. * writes to offscreen areas of the framebuffer are performed,
  559. * the "behaviour is undefined" (_very_ undefined) - Urs
  560. */
  561. /* btw, it requires enabling pixel pipeline in LFBMODE .
  562. off screen read/writes will just wrap and read/print pixels
  563. on screen. Ugly but not that dangerous */
  564. f_ddprintk("setting clipping dimensions 0..%d, 0..%d\n",
  565. info->var.xres - 1, par->yDim - 1);
  566. sst_write(CLIP_LEFT_RIGHT, info->var.xres);
  567. sst_write(CLIP_LOWY_HIGHY, par->yDim);
  568. sst_set_bits(FBZMODE, EN_CLIPPING | EN_RGB_WRITE);
  569. } else {
  570. /* no clipping : direct access, no pipeline */
  571. sst_write(LFBMODE, lfbmode);
  572. }
  573. return 0;
  574. }
  575. /**
  576. * sstfb_setcolreg - Optional function. Sets a color register.
  577. * @regno: hardware colormap register
  578. * @red: frame buffer colormap structure
  579. * @green: The green value which can be up to 16 bits wide
  580. * @blue: The blue value which can be up to 16 bits wide.
  581. * @transp: If supported the alpha value which can be up to 16 bits wide.
  582. * @info: frame buffer info structure
  583. */
  584. static int sstfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  585. u_int transp, struct fb_info *info)
  586. {
  587. struct sstfb_par *par = info->par;
  588. u32 col;
  589. f_dddprintk("sstfb_setcolreg\n");
  590. f_dddprintk("%-2d rgbt: %#x, %#x, %#x, %#x\n",
  591. regno, red, green, blue, transp);
  592. if (regno > 15)
  593. return 0;
  594. red >>= (16 - info->var.red.length);
  595. green >>= (16 - info->var.green.length);
  596. blue >>= (16 - info->var.blue.length);
  597. transp >>= (16 - info->var.transp.length);
  598. col = (red << info->var.red.offset)
  599. | (green << info->var.green.offset)
  600. | (blue << info->var.blue.offset)
  601. | (transp << info->var.transp.offset);
  602. par->palette[regno] = col;
  603. return 0;
  604. }
  605. static void sstfb_setvgapass( struct fb_info *info, int enable )
  606. {
  607. struct sstfb_par *par = info->par;
  608. struct pci_dev *sst_dev = par->dev;
  609. u32 fbiinit0, tmp;
  610. enable = enable ? 1:0;
  611. if (par->vgapass == enable)
  612. return;
  613. par->vgapass = enable;
  614. pci_read_config_dword(sst_dev, PCI_INIT_ENABLE, &tmp);
  615. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE,
  616. tmp | PCI_EN_INIT_WR );
  617. fbiinit0 = sst_read (FBIINIT0);
  618. if (par->vgapass) {
  619. sst_write(FBIINIT0, fbiinit0 & ~DIS_VGA_PASSTHROUGH);
  620. printk(KERN_INFO "fb%d: Enabling VGA pass-through\n", info->node );
  621. } else {
  622. sst_write(FBIINIT0, fbiinit0 | DIS_VGA_PASSTHROUGH);
  623. printk(KERN_INFO "fb%d: Disabling VGA pass-through\n", info->node );
  624. }
  625. pci_write_config_dword(sst_dev, PCI_INIT_ENABLE, tmp);
  626. }
  627. static ssize_t store_vgapass(struct device *device, struct device_attribute *attr,
  628. const char *buf, size_t count)
  629. {
  630. struct fb_info *info = dev_get_drvdata(device);
  631. char ** last = NULL;
  632. int val;
  633. val = simple_strtoul(buf, last, 0);
  634. sstfb_setvgapass(info, val);
  635. return count;
  636. }
  637. static ssize_t show_vgapass(struct device *device, struct device_attribute *attr,
  638. char *buf)
  639. {
  640. struct fb_info *info = dev_get_drvdata(device);
  641. struct sstfb_par *par = info->par;
  642. return snprintf(buf, PAGE_SIZE, "%d\n", par->vgapass);
  643. }
  644. static struct device_attribute device_attrs[] = {
  645. __ATTR(vgapass, S_IRUGO|S_IWUSR, show_vgapass, store_vgapass)
  646. };
  647. static int sstfb_ioctl(struct fb_info *info, unsigned int cmd,
  648. unsigned long arg)
  649. {
  650. struct sstfb_par *par;
  651. u32 val;
  652. switch (cmd) {
  653. /* set/get VGA pass_through mode */
  654. case SSTFB_SET_VGAPASS:
  655. if (copy_from_user(&val, (void __user *)arg, sizeof(val)))
  656. return -EFAULT;
  657. sstfb_setvgapass(info, val);
  658. return 0;
  659. case SSTFB_GET_VGAPASS:
  660. par = info->par;
  661. val = par->vgapass;
  662. if (copy_to_user((void __user *)arg, &val, sizeof(val)))
  663. return -EFAULT;
  664. return 0;
  665. }
  666. return -EINVAL;
  667. }
  668. /*
  669. * Screen-to-Screen BitBlt 2D command (for the bmove fb op.) - Voodoo2 only
  670. */
  671. #if 0
  672. static void sstfb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
  673. {
  674. struct sstfb_par *par = info->par;
  675. u32 stride = info->fix.line_length;
  676. if (!IS_VOODOO2(par))
  677. return;
  678. sst_write(BLTSRCBASEADDR, 0);
  679. sst_write(BLTDSTBASEADDR, 0);
  680. sst_write(BLTROP, BLTROP_COPY);
  681. sst_write(BLTXYSTRIDES, stride | (stride << 16));
  682. sst_write(BLTSRCXY, area->sx | (area->sy << 16));
  683. sst_write(BLTDSTXY, area->dx | (area->dy << 16));
  684. sst_write(BLTSIZE, area->width | (area->height << 16));
  685. sst_write(BLTCOMMAND, BLT_SCR2SCR_BITBLT | LAUNCH_BITBLT |
  686. (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) );
  687. sst_wait_idle();
  688. }
  689. #endif
  690. /*
  691. * FillRect 2D command (solidfill or invert (via ROP_XOR)) - Voodoo2 only
  692. */
  693. #if 0
  694. static void sstfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  695. {
  696. struct sstfb_par *par = info->par;
  697. u32 stride = info->fix.line_length;
  698. if (!IS_VOODOO2(par))
  699. return;
  700. sst_write(BLTCLIPX, info->var.xres);
  701. sst_write(BLTCLIPY, info->var.yres);
  702. sst_write(BLTDSTBASEADDR, 0);
  703. sst_write(BLTCOLOR, rect->color);
  704. sst_write(BLTROP, rect->rop == ROP_COPY ? BLTROP_COPY : BLTROP_XOR);
  705. sst_write(BLTXYSTRIDES, stride | (stride << 16));
  706. sst_write(BLTDSTXY, rect->dx | (rect->dy << 16));
  707. sst_write(BLTSIZE, rect->width | (rect->height << 16));
  708. sst_write(BLTCOMMAND, BLT_RECFILL_BITBLT | LAUNCH_BITBLT
  709. | (BLT_16BPP_FMT << 3) /* | BIT(14) */ | BIT(15) | BIT(16) );
  710. sst_wait_idle();
  711. }
  712. #endif
  713. /*
  714. * get lfb size
  715. */
  716. static int __devinit sst_get_memsize(struct fb_info *info, __u32 *memsize)
  717. {
  718. u8 __iomem *fbbase_virt = info->screen_base;
  719. /* force memsize */
  720. if (mem >= 1 && mem <= 4) {
  721. *memsize = (mem * 0x100000);
  722. printk(KERN_INFO "supplied memsize: %#x\n", *memsize);
  723. return 1;
  724. }
  725. writel(0xdeadbeef, fbbase_virt);
  726. writel(0xdeadbeef, fbbase_virt+0x100000);
  727. writel(0xdeadbeef, fbbase_virt+0x200000);
  728. f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
  729. readl(fbbase_virt), readl(fbbase_virt + 0x100000),
  730. readl(fbbase_virt + 0x200000));
  731. writel(0xabcdef01, fbbase_virt);
  732. f_ddprintk("0MB: %#x, 1MB: %#x, 2MB: %#x\n",
  733. readl(fbbase_virt), readl(fbbase_virt + 0x100000),
  734. readl(fbbase_virt + 0x200000));
  735. /* checks for 4mb lfb, then 2, then defaults to 1 */
  736. if (readl(fbbase_virt + 0x200000) == 0xdeadbeef)
  737. *memsize = 0x400000;
  738. else if (readl(fbbase_virt + 0x100000) == 0xdeadbeef)
  739. *memsize = 0x200000;
  740. else
  741. *memsize = 0x100000;
  742. f_ddprintk("detected memsize: %dMB\n", *memsize >> 20);
  743. return 1;
  744. }
  745. /*
  746. * DAC detection routines
  747. */
  748. /* fbi should be idle, and fifo emty and mem disabled */
  749. /* supposed to detect AT&T ATT20C409 and Ti TVP3409 ramdacs */
  750. static int __devinit sst_detect_att(struct fb_info *info)
  751. {
  752. struct sstfb_par *par = info->par;
  753. int i, mir, dir;
  754. for (i = 0; i < 3; i++) {
  755. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  756. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  757. sst_dac_read(DACREG_RMR);
  758. sst_dac_read(DACREG_RMR);
  759. sst_dac_read(DACREG_RMR);
  760. /* the fifth time, CR0 is read */
  761. sst_dac_read(DACREG_RMR);
  762. /* the 6th, manufacturer id register */
  763. mir = sst_dac_read(DACREG_RMR);
  764. /*the 7th, device ID register */
  765. dir = sst_dac_read(DACREG_RMR);
  766. f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
  767. if (mir == DACREG_MIR_ATT && dir == DACREG_DIR_ATT) {
  768. return 1;
  769. }
  770. }
  771. return 0;
  772. }
  773. static int __devinit sst_detect_ti(struct fb_info *info)
  774. {
  775. struct sstfb_par *par = info->par;
  776. int i, mir, dir;
  777. for (i = 0; i<3; i++) {
  778. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  779. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  780. sst_dac_read(DACREG_RMR);
  781. sst_dac_read(DACREG_RMR);
  782. sst_dac_read(DACREG_RMR);
  783. /* the fifth time, CR0 is read */
  784. sst_dac_read(DACREG_RMR);
  785. /* the 6th, manufacturer id register */
  786. mir = sst_dac_read(DACREG_RMR);
  787. /*the 7th, device ID register */
  788. dir = sst_dac_read(DACREG_RMR);
  789. f_ddprintk("mir: %#x, dir: %#x\n", mir, dir);
  790. if ((mir == DACREG_MIR_TI ) && (dir == DACREG_DIR_TI)) {
  791. return 1;
  792. }
  793. }
  794. return 0;
  795. }
  796. /*
  797. * try to detect ICS5342 ramdac
  798. * we get the 1st byte (M value) of preset f1,f7 and fB
  799. * why those 3 ? mmmh... for now, i'll do it the glide way...
  800. * and ask questions later. anyway, it seems that all the freq registers are
  801. * realy at their default state (cf specs) so i ask again, why those 3 regs ?
  802. * mmmmh.. it seems that's much more ugly than i thought. we use f0 and fA for
  803. * pll programming, so in fact, we *hope* that the f1, f7 & fB won't be
  804. * touched...
  805. * is it realy safe ? how can i reset this ramdac ? geee...
  806. */
  807. static int __devinit sst_detect_ics(struct fb_info *info)
  808. {
  809. struct sstfb_par *par = info->par;
  810. int m_clk0_1, m_clk0_7, m_clk1_b;
  811. int n_clk0_1, n_clk0_7, n_clk1_b;
  812. int i;
  813. for (i = 0; i<5; i++ ) {
  814. sst_dac_write(DACREG_ICS_PLLRMA, 0x1); /* f1 */
  815. m_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
  816. n_clk0_1 = sst_dac_read(DACREG_ICS_PLLDATA);
  817. sst_dac_write(DACREG_ICS_PLLRMA, 0x7); /* f7 */
  818. m_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
  819. n_clk0_7 = sst_dac_read(DACREG_ICS_PLLDATA);
  820. sst_dac_write(DACREG_ICS_PLLRMA, 0xb); /* fB */
  821. m_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
  822. n_clk1_b= sst_dac_read(DACREG_ICS_PLLDATA);
  823. f_ddprintk("m_clk0_1: %#x, m_clk0_7: %#x, m_clk1_b: %#x\n",
  824. m_clk0_1, m_clk0_7, m_clk1_b);
  825. f_ddprintk("n_clk0_1: %#x, n_clk0_7: %#x, n_clk1_b: %#x\n",
  826. n_clk0_1, n_clk0_7, n_clk1_b);
  827. if (( m_clk0_1 == DACREG_ICS_PLL_CLK0_1_INI)
  828. && (m_clk0_7 == DACREG_ICS_PLL_CLK0_7_INI)
  829. && (m_clk1_b == DACREG_ICS_PLL_CLK1_B_INI)) {
  830. return 1;
  831. }
  832. }
  833. return 0;
  834. }
  835. /*
  836. * gfx, video, pci fifo should be reset, dram refresh disabled
  837. * see detect_dac
  838. */
  839. static int sst_set_pll_att_ti(struct fb_info *info,
  840. const struct pll_timing *t, const int clock)
  841. {
  842. struct sstfb_par *par = info->par;
  843. u8 cr0, cc;
  844. /* enable indexed mode */
  845. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  846. sst_dac_read(DACREG_RMR); /* 1 time: RMR */
  847. sst_dac_read(DACREG_RMR); /* 2 RMR */
  848. sst_dac_read(DACREG_RMR); /* 3 // */
  849. sst_dac_read(DACREG_RMR); /* 4 // */
  850. cr0 = sst_dac_read(DACREG_RMR); /* 5 CR0 */
  851. sst_dac_write(DACREG_WMA, 0);
  852. sst_dac_read(DACREG_RMR);
  853. sst_dac_read(DACREG_RMR);
  854. sst_dac_read(DACREG_RMR);
  855. sst_dac_read(DACREG_RMR);
  856. sst_dac_write(DACREG_RMR, (cr0 & 0xf0)
  857. | DACREG_CR0_EN_INDEXED
  858. | DACREG_CR0_8BIT
  859. | DACREG_CR0_PWDOWN );
  860. /* so, now we are in indexed mode . dunno if its common, but
  861. i find this way of doing things a little bit weird :p */
  862. udelay(300);
  863. cc = dac_i_read(DACREG_CC_I);
  864. switch (clock) {
  865. case VID_CLOCK:
  866. dac_i_write(DACREG_AC0_I, t->m);
  867. dac_i_write(DACREG_AC1_I, t->p << 6 | t->n);
  868. dac_i_write(DACREG_CC_I,
  869. (cc & 0x0f) | DACREG_CC_CLKA | DACREG_CC_CLKA_C);
  870. break;
  871. case GFX_CLOCK:
  872. dac_i_write(DACREG_BD0_I, t->m);
  873. dac_i_write(DACREG_BD1_I, t->p << 6 | t->n);
  874. dac_i_write(DACREG_CC_I,
  875. (cc & 0xf0) | DACREG_CC_CLKB | DACREG_CC_CLKB_D);
  876. break;
  877. default:
  878. dprintk("%s: wrong clock code '%d'\n",
  879. __FUNCTION__, clock);
  880. return 0;
  881. }
  882. udelay(300);
  883. /* power up the dac & return to "normal" non-indexed mode */
  884. dac_i_write(DACREG_CR0_I,
  885. cr0 & ~DACREG_CR0_PWDOWN & ~DACREG_CR0_EN_INDEXED);
  886. return 1;
  887. }
  888. static int sst_set_pll_ics(struct fb_info *info,
  889. const struct pll_timing *t, const int clock)
  890. {
  891. struct sstfb_par *par = info->par;
  892. u8 pll_ctrl;
  893. sst_dac_write(DACREG_ICS_PLLRMA, DACREG_ICS_PLL_CTRL);
  894. pll_ctrl = sst_dac_read(DACREG_ICS_PLLDATA);
  895. switch(clock) {
  896. case VID_CLOCK:
  897. sst_dac_write(DACREG_ICS_PLLWMA, 0x0); /* CLK0, f0 */
  898. sst_dac_write(DACREG_ICS_PLLDATA, t->m);
  899. sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
  900. /* selects freq f0 for clock 0 */
  901. sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
  902. sst_dac_write(DACREG_ICS_PLLDATA,
  903. (pll_ctrl & 0xd8)
  904. | DACREG_ICS_CLK0
  905. | DACREG_ICS_CLK0_0);
  906. break;
  907. case GFX_CLOCK :
  908. sst_dac_write(DACREG_ICS_PLLWMA, 0xa); /* CLK1, fA */
  909. sst_dac_write(DACREG_ICS_PLLDATA, t->m);
  910. sst_dac_write(DACREG_ICS_PLLDATA, t->p << 5 | t->n);
  911. /* selects freq fA for clock 1 */
  912. sst_dac_write(DACREG_ICS_PLLWMA, DACREG_ICS_PLL_CTRL);
  913. sst_dac_write(DACREG_ICS_PLLDATA,
  914. (pll_ctrl & 0xef) | DACREG_ICS_CLK1_A);
  915. break;
  916. default:
  917. dprintk("%s: wrong clock code '%d'\n",
  918. __FUNCTION__, clock);
  919. return 0;
  920. }
  921. udelay(300);
  922. return 1;
  923. }
  924. static void sst_set_vidmod_att_ti(struct fb_info *info, const int bpp)
  925. {
  926. struct sstfb_par *par = info->par;
  927. u8 cr0;
  928. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  929. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  930. sst_dac_read(DACREG_RMR);
  931. sst_dac_read(DACREG_RMR);
  932. sst_dac_read(DACREG_RMR);
  933. /* the fifth time, CR0 is read */
  934. cr0 = sst_dac_read(DACREG_RMR);
  935. sst_dac_write(DACREG_WMA, 0); /* backdoor */
  936. sst_dac_read(DACREG_RMR); /* read 4 times RMR */
  937. sst_dac_read(DACREG_RMR);
  938. sst_dac_read(DACREG_RMR);
  939. sst_dac_read(DACREG_RMR);
  940. /* cr0 */
  941. switch(bpp) {
  942. case 16:
  943. sst_dac_write(DACREG_RMR, (cr0 & 0x0f) | DACREG_CR0_16BPP);
  944. break;
  945. default:
  946. dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
  947. break;
  948. }
  949. }
  950. static void sst_set_vidmod_ics(struct fb_info *info, const int bpp)
  951. {
  952. struct sstfb_par *par = info->par;
  953. switch(bpp) {
  954. case 16:
  955. sst_dac_write(DACREG_ICS_CMD, DACREG_ICS_CMD_16BPP);
  956. break;
  957. default:
  958. dprintk("%s: bad depth '%u'\n", __FUNCTION__, bpp);
  959. break;
  960. }
  961. }
  962. /*
  963. * detect dac type
  964. * prerequisite : write to FbiInitx enabled, video and fbi and pci fifo reset,
  965. * dram refresh disabled, FbiInit remaped.
  966. * TODO: mmh.. maybe i shoud put the "prerequisite" in the func ...
  967. */
  968. static struct dac_switch dacs[] __devinitdata = {
  969. { .name = "TI TVP3409",
  970. .detect = sst_detect_ti,
  971. .set_pll = sst_set_pll_att_ti,
  972. .set_vidmod = sst_set_vidmod_att_ti },
  973. { .name = "AT&T ATT20C409",
  974. .detect = sst_detect_att,
  975. .set_pll = sst_set_pll_att_ti,
  976. .set_vidmod = sst_set_vidmod_att_ti },
  977. { .name = "ICS ICS5342",
  978. .detect = sst_detect_ics,
  979. .set_pll = sst_set_pll_ics,
  980. .set_vidmod = sst_set_vidmod_ics },
  981. };
  982. static int __devinit sst_detect_dactype(struct fb_info *info, struct sstfb_par *par)
  983. {
  984. int i, ret = 0;
  985. for (i = 0; i < ARRAY_SIZE(dacs); i++) {
  986. ret = dacs[i].detect(info);
  987. if (ret)
  988. break;
  989. }
  990. if (!ret)
  991. return 0;
  992. f_dprintk("%s found %s\n", __FUNCTION__, dacs[i].name);
  993. par->dac_sw = dacs[i];
  994. return 1;
  995. }
  996. /*
  997. * Internal Routines
  998. */
  999. static int __devinit sst_init(struct fb_info *info, struct sstfb_par *par)
  1000. {
  1001. u32 fbiinit0, fbiinit1, fbiinit4;
  1002. struct pci_dev *dev = par->dev;
  1003. struct pll_timing gfx_timings;
  1004. struct sst_spec *spec;
  1005. int Fout;
  1006. int gfx_clock;
  1007. spec = &voodoo_spec[par->type];
  1008. f_ddprintk(" fbiinit0 fbiinit1 fbiinit2 fbiinit3 fbiinit4 "
  1009. " fbiinit6\n");
  1010. f_ddprintk("%0#10x %0#10x %0#10x %0#10x %0#10x %0#10x\n",
  1011. sst_read(FBIINIT0), sst_read(FBIINIT1), sst_read(FBIINIT2),
  1012. sst_read(FBIINIT3), sst_read(FBIINIT4), sst_read(FBIINIT6));
  1013. /* disable video clock */
  1014. pci_write_config_dword(dev, PCI_VCLK_DISABLE, 0);
  1015. /* enable writing to init registers, disable pci fifo */
  1016. pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
  1017. /* reset video */
  1018. sst_set_bits(FBIINIT1, VIDEO_RESET);
  1019. sst_wait_idle();
  1020. /* reset gfx + pci fifo */
  1021. sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  1022. sst_wait_idle();
  1023. /* unreset fifo */
  1024. /*sst_unset_bits(FBIINIT0, FIFO_RESET);
  1025. sst_wait_idle();*/
  1026. /* unreset FBI */
  1027. /*sst_unset_bits(FBIINIT0, FBI_RESET);
  1028. sst_wait_idle();*/
  1029. /* disable dram refresh */
  1030. sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
  1031. sst_wait_idle();
  1032. /* remap fbinit2/3 to dac */
  1033. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1034. PCI_EN_INIT_WR | PCI_REMAP_DAC );
  1035. /* detect dac type */
  1036. if (!sst_detect_dactype(info, par)) {
  1037. printk(KERN_ERR "sstfb: unknown dac type.\n");
  1038. //FIXME watch it: we are not in a safe state, bad bad bad.
  1039. return 0;
  1040. }
  1041. /* set graphic clock */
  1042. gfx_clock = spec->default_gfx_clock;
  1043. if ((gfxclk >10 ) && (gfxclk < spec->max_gfxclk)) {
  1044. printk(KERN_INFO "sstfb: Using supplied graphic freq : %dMHz\n", gfxclk);
  1045. gfx_clock = gfxclk *1000;
  1046. } else if (gfxclk) {
  1047. printk(KERN_WARNING "sstfb: %dMhz is way out of spec! Using default\n", gfxclk);
  1048. }
  1049. sst_calc_pll(gfx_clock, &Fout, &gfx_timings);
  1050. par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
  1051. /* disable fbiinit remap */
  1052. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1053. PCI_EN_INIT_WR| PCI_EN_FIFO_WR );
  1054. /* defaults init registers */
  1055. /* FbiInit0: unreset gfx, unreset fifo */
  1056. fbiinit0 = FBIINIT0_DEFAULT;
  1057. fbiinit1 = FBIINIT1_DEFAULT;
  1058. fbiinit4 = FBIINIT4_DEFAULT;
  1059. par->vgapass = vgapass;
  1060. if (par->vgapass)
  1061. fbiinit0 &= ~DIS_VGA_PASSTHROUGH;
  1062. else
  1063. fbiinit0 |= DIS_VGA_PASSTHROUGH;
  1064. if (slowpci) {
  1065. fbiinit1 |= SLOW_PCI_WRITES;
  1066. fbiinit4 |= SLOW_PCI_READS;
  1067. } else {
  1068. fbiinit1 &= ~SLOW_PCI_WRITES;
  1069. fbiinit4 &= ~SLOW_PCI_READS;
  1070. }
  1071. sst_write(FBIINIT0, fbiinit0);
  1072. sst_wait_idle();
  1073. sst_write(FBIINIT1, fbiinit1);
  1074. sst_wait_idle();
  1075. sst_write(FBIINIT2, FBIINIT2_DEFAULT);
  1076. sst_wait_idle();
  1077. sst_write(FBIINIT3, FBIINIT3_DEFAULT);
  1078. sst_wait_idle();
  1079. sst_write(FBIINIT4, fbiinit4);
  1080. sst_wait_idle();
  1081. if (IS_VOODOO2(par)) {
  1082. sst_write(FBIINIT6, FBIINIT6_DEFAULT);
  1083. sst_wait_idle();
  1084. }
  1085. pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_FIFO_WR);
  1086. pci_write_config_dword(dev, PCI_VCLK_ENABLE, 0);
  1087. return 1;
  1088. }
  1089. static void __devexit sst_shutdown(struct fb_info *info)
  1090. {
  1091. struct sstfb_par *par = info->par;
  1092. struct pci_dev *dev = par->dev;
  1093. struct pll_timing gfx_timings;
  1094. int Fout;
  1095. /* reset video, gfx, fifo, disable dram + remap fbiinit2/3 */
  1096. pci_write_config_dword(dev, PCI_INIT_ENABLE, PCI_EN_INIT_WR);
  1097. sst_set_bits(FBIINIT1, VIDEO_RESET | EN_BLANKING);
  1098. sst_unset_bits(FBIINIT2, EN_DRAM_REFRESH);
  1099. sst_set_bits(FBIINIT0, FBI_RESET | FIFO_RESET);
  1100. sst_wait_idle();
  1101. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1102. PCI_EN_INIT_WR | PCI_REMAP_DAC);
  1103. /* set 20Mhz gfx clock */
  1104. sst_calc_pll(20000, &Fout, &gfx_timings);
  1105. par->dac_sw.set_pll(info, &gfx_timings, GFX_CLOCK);
  1106. /* TODO maybe shutdown the dac, vrefresh and so on... */
  1107. pci_write_config_dword(dev, PCI_INIT_ENABLE,
  1108. PCI_EN_INIT_WR);
  1109. sst_unset_bits(FBIINIT0, FBI_RESET | FIFO_RESET | DIS_VGA_PASSTHROUGH);
  1110. pci_write_config_dword(dev, PCI_VCLK_DISABLE,0);
  1111. /* maybe keep fbiinit* and PCI_INIT_enable in the fb_info struct
  1112. * from start ? */
  1113. pci_write_config_dword(dev, PCI_INIT_ENABLE, 0);
  1114. }
  1115. /*
  1116. * Interface to the world
  1117. */
  1118. static int __devinit sstfb_setup(char *options)
  1119. {
  1120. char *this_opt;
  1121. if (!options || !*options)
  1122. return 0;
  1123. while ((this_opt = strsep(&options, ",")) != NULL) {
  1124. if (!*this_opt) continue;
  1125. f_ddprintk("option %s\n", this_opt);
  1126. if (!strcmp(this_opt, "vganopass"))
  1127. vgapass = 0;
  1128. else if (!strcmp(this_opt, "vgapass"))
  1129. vgapass = 1;
  1130. else if (!strcmp(this_opt, "clipping"))
  1131. clipping = 1;
  1132. else if (!strcmp(this_opt, "noclipping"))
  1133. clipping = 0;
  1134. else if (!strcmp(this_opt, "fastpci"))
  1135. slowpci = 0;
  1136. else if (!strcmp(this_opt, "slowpci"))
  1137. slowpci = 1;
  1138. else if (!strncmp(this_opt, "mem:",4))
  1139. mem = simple_strtoul (this_opt+4, NULL, 0);
  1140. else if (!strncmp(this_opt, "gfxclk:",7))
  1141. gfxclk = simple_strtoul (this_opt+7, NULL, 0);
  1142. else
  1143. mode_option = this_opt;
  1144. }
  1145. return 0;
  1146. }
  1147. static struct fb_ops sstfb_ops = {
  1148. .owner = THIS_MODULE,
  1149. .fb_check_var = sstfb_check_var,
  1150. .fb_set_par = sstfb_set_par,
  1151. .fb_setcolreg = sstfb_setcolreg,
  1152. .fb_fillrect = cfb_fillrect, /* sstfb_fillrect */
  1153. .fb_copyarea = cfb_copyarea, /* sstfb_copyarea */
  1154. .fb_imageblit = cfb_imageblit,
  1155. .fb_ioctl = sstfb_ioctl,
  1156. };
  1157. static int __devinit sstfb_probe(struct pci_dev *pdev,
  1158. const struct pci_device_id *id)
  1159. {
  1160. struct fb_info *info;
  1161. struct fb_fix_screeninfo *fix;
  1162. struct sstfb_par *par;
  1163. struct sst_spec *spec;
  1164. int err;
  1165. /* Enable device in PCI config. */
  1166. if ((err=pci_enable_device(pdev))) {
  1167. printk(KERN_ERR "cannot enable device\n");
  1168. return err;
  1169. }
  1170. /* Allocate the fb and par structures. */
  1171. info = framebuffer_alloc(sizeof(struct sstfb_par), &pdev->dev);
  1172. if (!info)
  1173. return -ENOMEM;
  1174. pci_set_drvdata(pdev, info);
  1175. par = info->par;
  1176. fix = &info->fix;
  1177. par->type = id->driver_data;
  1178. spec = &voodoo_spec[par->type];
  1179. f_ddprintk("found device : %s\n", spec->name);
  1180. par->dev = pdev;
  1181. pci_read_config_byte(pdev, PCI_REVISION_ID, &par->revision);
  1182. fix->mmio_start = pci_resource_start(pdev,0);
  1183. fix->mmio_len = 0x400000;
  1184. fix->smem_start = fix->mmio_start + 0x400000;
  1185. if (!request_mem_region(fix->mmio_start, fix->mmio_len, "sstfb MMIO")) {
  1186. printk(KERN_ERR "sstfb: cannot reserve mmio memory\n");
  1187. goto fail_mmio_mem;
  1188. }
  1189. if (!request_mem_region(fix->smem_start, 0x400000,"sstfb FB")) {
  1190. printk(KERN_ERR "sstfb: cannot reserve fb memory\n");
  1191. goto fail_fb_mem;
  1192. }
  1193. par->mmio_vbase = ioremap_nocache(fix->mmio_start,
  1194. fix->mmio_len);
  1195. if (!par->mmio_vbase) {
  1196. printk(KERN_ERR "sstfb: cannot remap register area %#lx\n",
  1197. fix->mmio_start);
  1198. goto fail_mmio_remap;
  1199. }
  1200. info->screen_base = ioremap_nocache(fix->smem_start, 0x400000);
  1201. if (!info->screen_base) {
  1202. printk(KERN_ERR "sstfb: cannot remap framebuffer %#lx\n",
  1203. fix->smem_start);
  1204. goto fail_fb_remap;
  1205. }
  1206. if (!sst_init(info, par)) {
  1207. printk(KERN_ERR "sstfb: Init failed\n");
  1208. goto fail;
  1209. }
  1210. sst_get_memsize(info, &fix->smem_len);
  1211. strlcpy(fix->id, spec->name, sizeof(fix->id));
  1212. printk(KERN_INFO "%s (revision %d) with %s dac\n",
  1213. fix->id, par->revision, par->dac_sw.name);
  1214. printk(KERN_INFO "framebuffer at %#lx, mapped to 0x%p, size %dMB\n",
  1215. fix->smem_start, info->screen_base,
  1216. fix->smem_len >> 20);
  1217. f_ddprintk("regbase_virt: %#lx\n", par->mmio_vbase);
  1218. f_ddprintk("membase_phys: %#lx\n", fix->smem_start);
  1219. f_ddprintk("fbbase_virt: %p\n", info->screen_base);
  1220. info->flags = FBINFO_DEFAULT;
  1221. info->fbops = &sstfb_ops;
  1222. info->pseudo_palette = par->palette;
  1223. fix->type = FB_TYPE_PACKED_PIXELS;
  1224. fix->visual = FB_VISUAL_TRUECOLOR;
  1225. fix->accel = FB_ACCEL_NONE; /* FIXME */
  1226. /*
  1227. * According to the specs, the linelength must be of 1024 *pixels*
  1228. * and the 24bpp mode is in fact a 32 bpp mode (and both are in
  1229. * fact dithered to 16bit).
  1230. */
  1231. fix->line_length = 2048; /* default value, for 24 or 32bit: 4096 */
  1232. fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 16);
  1233. if (sstfb_check_var(&info->var, info)) {
  1234. printk(KERN_ERR "sstfb: invalid video mode.\n");
  1235. goto fail;
  1236. }
  1237. if (sstfb_set_par(info)) {
  1238. printk(KERN_ERR "sstfb: can't set default video mode.\n");
  1239. goto fail;
  1240. }
  1241. fb_alloc_cmap(&info->cmap, 256, 0);
  1242. /* register fb */
  1243. info->device = &pdev->dev;
  1244. if (register_framebuffer(info) < 0) {
  1245. printk(KERN_ERR "sstfb: can't register framebuffer.\n");
  1246. goto fail;
  1247. }
  1248. sstfb_clear_screen(info);
  1249. if (device_create_file(info->dev, &device_attrs[0]))
  1250. printk(KERN_WARNING "sstfb: can't create sysfs entry.\n");
  1251. printk(KERN_INFO "fb%d: %s frame buffer device at 0x%p\n",
  1252. info->node, fix->id, info->screen_base);
  1253. return 0;
  1254. fail:
  1255. fb_dealloc_cmap(&info->cmap);
  1256. iounmap(info->screen_base);
  1257. fail_fb_remap:
  1258. iounmap(par->mmio_vbase);
  1259. fail_mmio_remap:
  1260. release_mem_region(fix->smem_start, 0x400000);
  1261. fail_fb_mem:
  1262. release_mem_region(fix->mmio_start, info->fix.mmio_len);
  1263. fail_mmio_mem:
  1264. framebuffer_release(info);
  1265. return -ENXIO; /* no voodoo detected */
  1266. }
  1267. static void __devexit sstfb_remove(struct pci_dev *pdev)
  1268. {
  1269. struct sstfb_par *par;
  1270. struct fb_info *info;
  1271. info = pci_get_drvdata(pdev);
  1272. par = info->par;
  1273. device_remove_file(info->dev, &device_attrs[0]);
  1274. sst_shutdown(info);
  1275. iounmap(info->screen_base);
  1276. iounmap(par->mmio_vbase);
  1277. release_mem_region(info->fix.smem_start, 0x400000);
  1278. release_mem_region(info->fix.mmio_start, info->fix.mmio_len);
  1279. fb_dealloc_cmap(&info->cmap);
  1280. unregister_framebuffer(info);
  1281. framebuffer_release(info);
  1282. }
  1283. static const struct pci_device_id sstfb_id_tbl[] = {
  1284. { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO ),
  1285. .driver_data = ID_VOODOO1, },
  1286. { PCI_DEVICE(PCI_VENDOR_ID_3DFX, PCI_DEVICE_ID_3DFX_VOODOO2),
  1287. .driver_data = ID_VOODOO2, },
  1288. { 0 },
  1289. };
  1290. static struct pci_driver sstfb_driver = {
  1291. .name = "sstfb",
  1292. .id_table = sstfb_id_tbl,
  1293. .probe = sstfb_probe,
  1294. .remove = __devexit_p(sstfb_remove),
  1295. };
  1296. static int __devinit sstfb_init(void)
  1297. {
  1298. char *option = NULL;
  1299. if (fb_get_options("sstfb", &option))
  1300. return -ENODEV;
  1301. sstfb_setup(option);
  1302. return pci_register_driver(&sstfb_driver);
  1303. }
  1304. static void __devexit sstfb_exit(void)
  1305. {
  1306. pci_unregister_driver(&sstfb_driver);
  1307. }
  1308. module_init(sstfb_init);
  1309. module_exit(sstfb_exit);
  1310. MODULE_AUTHOR("(c) 2000,2002 Ghozlane Toumi <gtoumi@laposte.net>");
  1311. MODULE_DESCRIPTION("FBDev driver for 3dfx Voodoo Graphics and Voodoo2 based video boards");
  1312. MODULE_LICENSE("GPL");
  1313. module_param(mem, int, 0);
  1314. MODULE_PARM_DESC(mem, "Size of frame buffer memory in MB (1, 2, 4 MB, default=autodetect)");
  1315. module_param(vgapass, bool, 0);
  1316. MODULE_PARM_DESC(vgapass, "Enable VGA PassThrough mode (0 or 1) (default=0)");
  1317. module_param(clipping, bool, 0);
  1318. MODULE_PARM_DESC(clipping, "Enable clipping (slower, safer) (0 or 1) (default=1)");
  1319. module_param(gfxclk, int, 0);
  1320. MODULE_PARM_DESC(gfxclk, "Force graphic chip frequency in MHz. DANGEROUS. (default=auto)");
  1321. module_param(slowpci, bool, 0);
  1322. MODULE_PARM_DESC(slowpci, "Uses slow PCI settings (0 or 1) (default=0)");
  1323. module_param(mode_option, charp, 0);
  1324. MODULE_PARM_DESC(mode_option, "Initial video mode (default=" DEFAULT_VIDEO_MODE ")");