sgivwfb.c 23 KB

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  1. /*
  2. * linux/drivers/video/sgivwfb.c -- SGI DBE frame buffer device
  3. *
  4. * Copyright (C) 1999 Silicon Graphics, Inc.
  5. * Jeffrey Newquist, newquist@engr.sgi.som
  6. *
  7. * This file is subject to the terms and conditions of the GNU General Public
  8. * License. See the file COPYING in the main directory of this archive for
  9. * more details.
  10. */
  11. #include <linux/module.h>
  12. #include <linux/kernel.h>
  13. #include <linux/mm.h>
  14. #include <linux/errno.h>
  15. #include <linux/delay.h>
  16. #include <linux/fb.h>
  17. #include <linux/init.h>
  18. #include <linux/ioport.h>
  19. #include <linux/platform_device.h>
  20. #include <asm/io.h>
  21. #include <asm/mtrr.h>
  22. #include <setup_arch.h>
  23. #define INCLUDE_TIMING_TABLE_DATA
  24. #define DBE_REG_BASE par->regs
  25. #include <video/sgivw.h>
  26. struct sgivw_par {
  27. struct asregs *regs;
  28. u32 cmap_fifo;
  29. u_long timing_num;
  30. };
  31. #define FLATPANEL_SGI_1600SW 5
  32. /*
  33. * RAM we reserve for the frame buffer. This defines the maximum screen
  34. * size
  35. *
  36. * The default can be overridden if the driver is compiled as a module
  37. */
  38. static int ypan = 0;
  39. static int ywrap = 0;
  40. static int flatpanel_id = -1;
  41. static struct fb_fix_screeninfo sgivwfb_fix __initdata = {
  42. .id = "SGI Vis WS FB",
  43. .type = FB_TYPE_PACKED_PIXELS,
  44. .visual = FB_VISUAL_PSEUDOCOLOR,
  45. .mmio_start = DBE_REG_PHYS,
  46. .mmio_len = DBE_REG_SIZE,
  47. .accel = FB_ACCEL_NONE,
  48. .line_length = 640,
  49. };
  50. static struct fb_var_screeninfo sgivwfb_var __initdata = {
  51. /* 640x480, 8 bpp */
  52. .xres = 640,
  53. .yres = 480,
  54. .xres_virtual = 640,
  55. .yres_virtual = 480,
  56. .bits_per_pixel = 8,
  57. .red = { 0, 8, 0 },
  58. .green = { 0, 8, 0 },
  59. .blue = { 0, 8, 0 },
  60. .height = -1,
  61. .width = -1,
  62. .pixclock = 20000,
  63. .left_margin = 64,
  64. .right_margin = 64,
  65. .upper_margin = 32,
  66. .lower_margin = 32,
  67. .hsync_len = 64,
  68. .vsync_len = 2,
  69. .vmode = FB_VMODE_NONINTERLACED
  70. };
  71. static struct fb_var_screeninfo sgivwfb_var1600sw __initdata = {
  72. /* 1600x1024, 8 bpp */
  73. .xres = 1600,
  74. .yres = 1024,
  75. .xres_virtual = 1600,
  76. .yres_virtual = 1024,
  77. .bits_per_pixel = 8,
  78. .red = { 0, 8, 0 },
  79. .green = { 0, 8, 0 },
  80. .blue = { 0, 8, 0 },
  81. .height = -1,
  82. .width = -1,
  83. .pixclock = 9353,
  84. .left_margin = 20,
  85. .right_margin = 30,
  86. .upper_margin = 37,
  87. .lower_margin = 3,
  88. .hsync_len = 20,
  89. .vsync_len = 3,
  90. .vmode = FB_VMODE_NONINTERLACED
  91. };
  92. /*
  93. * Interface used by the world
  94. */
  95. int sgivwfb_init(void);
  96. static int sgivwfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
  97. static int sgivwfb_set_par(struct fb_info *info);
  98. static int sgivwfb_setcolreg(u_int regno, u_int red, u_int green,
  99. u_int blue, u_int transp,
  100. struct fb_info *info);
  101. static int sgivwfb_mmap(struct fb_info *info,
  102. struct vm_area_struct *vma);
  103. static struct fb_ops sgivwfb_ops = {
  104. .owner = THIS_MODULE,
  105. .fb_check_var = sgivwfb_check_var,
  106. .fb_set_par = sgivwfb_set_par,
  107. .fb_setcolreg = sgivwfb_setcolreg,
  108. .fb_fillrect = cfb_fillrect,
  109. .fb_copyarea = cfb_copyarea,
  110. .fb_imageblit = cfb_imageblit,
  111. .fb_mmap = sgivwfb_mmap,
  112. };
  113. /*
  114. * Internal routines
  115. */
  116. static unsigned long bytes_per_pixel(int bpp)
  117. {
  118. switch (bpp) {
  119. case 8:
  120. return 1;
  121. case 16:
  122. return 2;
  123. case 32:
  124. return 4;
  125. default:
  126. printk(KERN_INFO "sgivwfb: unsupported bpp %d\n", bpp);
  127. return 0;
  128. }
  129. }
  130. static unsigned long get_line_length(int xres_virtual, int bpp)
  131. {
  132. return (xres_virtual * bytes_per_pixel(bpp));
  133. }
  134. /*
  135. * Function: dbe_TurnOffDma
  136. * Parameters: (None)
  137. * Description: This should turn off the monitor and dbe. This is used
  138. * when switching between the serial console and the graphics
  139. * console.
  140. */
  141. static void dbe_TurnOffDma(struct sgivw_par *par)
  142. {
  143. unsigned int readVal;
  144. int i;
  145. // Check to see if things are already turned off:
  146. // 1) Check to see if dbe is not using the internal dotclock.
  147. // 2) Check to see if the xy counter in dbe is already off.
  148. DBE_GETREG(ctrlstat, readVal);
  149. if (GET_DBE_FIELD(CTRLSTAT, PCLKSEL, readVal) < 2)
  150. return;
  151. DBE_GETREG(vt_xy, readVal);
  152. if (GET_DBE_FIELD(VT_XY, VT_FREEZE, readVal) == 1)
  153. return;
  154. // Otherwise, turn off dbe
  155. DBE_GETREG(ovr_control, readVal);
  156. SET_DBE_FIELD(OVR_CONTROL, OVR_DMA_ENABLE, readVal, 0);
  157. DBE_SETREG(ovr_control, readVal);
  158. udelay(1000);
  159. DBE_GETREG(frm_control, readVal);
  160. SET_DBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, readVal, 0);
  161. DBE_SETREG(frm_control, readVal);
  162. udelay(1000);
  163. DBE_GETREG(did_control, readVal);
  164. SET_DBE_FIELD(DID_CONTROL, DID_DMA_ENABLE, readVal, 0);
  165. DBE_SETREG(did_control, readVal);
  166. udelay(1000);
  167. // XXX HACK:
  168. //
  169. // This was necessary for GBE--we had to wait through two
  170. // vertical retrace periods before the pixel DMA was
  171. // turned off for sure. I've left this in for now, in
  172. // case dbe needs it.
  173. for (i = 0; i < 10000; i++) {
  174. DBE_GETREG(frm_inhwctrl, readVal);
  175. if (GET_DBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, readVal) ==
  176. 0)
  177. udelay(10);
  178. else {
  179. DBE_GETREG(ovr_inhwctrl, readVal);
  180. if (GET_DBE_FIELD
  181. (OVR_INHWCTRL, OVR_DMA_ENABLE, readVal) == 0)
  182. udelay(10);
  183. else {
  184. DBE_GETREG(did_inhwctrl, readVal);
  185. if (GET_DBE_FIELD
  186. (DID_INHWCTRL, DID_DMA_ENABLE,
  187. readVal) == 0)
  188. udelay(10);
  189. else
  190. break;
  191. }
  192. }
  193. }
  194. }
  195. /*
  196. * Set the User Defined Part of the Display. Again if par use it to get
  197. * real video mode.
  198. */
  199. static int sgivwfb_check_var(struct fb_var_screeninfo *var,
  200. struct fb_info *info)
  201. {
  202. struct sgivw_par *par = (struct sgivw_par *)info->par;
  203. struct dbe_timing_info *timing;
  204. u_long line_length;
  205. u_long min_mode;
  206. int req_dot;
  207. int test_mode;
  208. /*
  209. * FB_VMODE_CONUPDATE and FB_VMODE_SMOOTH_XPAN are equal!
  210. * as FB_VMODE_SMOOTH_XPAN is only used internally
  211. */
  212. if (var->vmode & FB_VMODE_CONUPDATE) {
  213. var->vmode |= FB_VMODE_YWRAP;
  214. var->xoffset = info->var.xoffset;
  215. var->yoffset = info->var.yoffset;
  216. }
  217. /* XXX FIXME - forcing var's */
  218. var->xoffset = 0;
  219. var->yoffset = 0;
  220. /* Limit bpp to 8, 16, and 32 */
  221. if (var->bits_per_pixel <= 8)
  222. var->bits_per_pixel = 8;
  223. else if (var->bits_per_pixel <= 16)
  224. var->bits_per_pixel = 16;
  225. else if (var->bits_per_pixel <= 32)
  226. var->bits_per_pixel = 32;
  227. else
  228. return -EINVAL;
  229. var->grayscale = 0; /* No grayscale for now */
  230. /* determine valid resolution and timing */
  231. for (min_mode = 0; min_mode < DBE_VT_SIZE; min_mode++) {
  232. if (dbeVTimings[min_mode].width >= var->xres &&
  233. dbeVTimings[min_mode].height >= var->yres)
  234. break;
  235. }
  236. if (min_mode == DBE_VT_SIZE)
  237. return -EINVAL; /* Resolution to high */
  238. /* XXX FIXME - should try to pick best refresh rate */
  239. /* for now, pick closest dot-clock within 3MHz */
  240. req_dot = PICOS2KHZ(var->pixclock);
  241. printk(KERN_INFO "sgivwfb: requested pixclock=%d ps (%d KHz)\n",
  242. var->pixclock, req_dot);
  243. test_mode = min_mode;
  244. while (dbeVTimings[min_mode].width == dbeVTimings[test_mode].width) {
  245. if (dbeVTimings[test_mode].cfreq + 3000 > req_dot)
  246. break;
  247. test_mode++;
  248. }
  249. if (dbeVTimings[min_mode].width != dbeVTimings[test_mode].width)
  250. test_mode--;
  251. min_mode = test_mode;
  252. timing = &dbeVTimings[min_mode];
  253. printk(KERN_INFO "sgivwfb: granted dot-clock=%d KHz\n", timing->cfreq);
  254. /* Adjust virtual resolution, if necessary */
  255. if (var->xres > var->xres_virtual || (!ywrap && !ypan))
  256. var->xres_virtual = var->xres;
  257. if (var->yres > var->yres_virtual || (!ywrap && !ypan))
  258. var->yres_virtual = var->yres;
  259. /*
  260. * Memory limit
  261. */
  262. line_length = get_line_length(var->xres_virtual, var->bits_per_pixel);
  263. if (line_length * var->yres_virtual > sgivwfb_mem_size)
  264. return -ENOMEM; /* Virtual resolution to high */
  265. info->fix.line_length = line_length;
  266. switch (var->bits_per_pixel) {
  267. case 8:
  268. var->red.offset = 0;
  269. var->red.length = 8;
  270. var->green.offset = 0;
  271. var->green.length = 8;
  272. var->blue.offset = 0;
  273. var->blue.length = 8;
  274. var->transp.offset = 0;
  275. var->transp.length = 0;
  276. break;
  277. case 16: /* RGBA 5551 */
  278. var->red.offset = 11;
  279. var->red.length = 5;
  280. var->green.offset = 6;
  281. var->green.length = 5;
  282. var->blue.offset = 1;
  283. var->blue.length = 5;
  284. var->transp.offset = 0;
  285. var->transp.length = 0;
  286. break;
  287. case 32: /* RGB 8888 */
  288. var->red.offset = 0;
  289. var->red.length = 8;
  290. var->green.offset = 8;
  291. var->green.length = 8;
  292. var->blue.offset = 16;
  293. var->blue.length = 8;
  294. var->transp.offset = 24;
  295. var->transp.length = 8;
  296. break;
  297. }
  298. var->red.msb_right = 0;
  299. var->green.msb_right = 0;
  300. var->blue.msb_right = 0;
  301. var->transp.msb_right = 0;
  302. /* set video timing information */
  303. var->pixclock = KHZ2PICOS(timing->cfreq);
  304. var->left_margin = timing->htotal - timing->hsync_end;
  305. var->right_margin = timing->hsync_start - timing->width;
  306. var->upper_margin = timing->vtotal - timing->vsync_end;
  307. var->lower_margin = timing->vsync_start - timing->height;
  308. var->hsync_len = timing->hsync_end - timing->hsync_start;
  309. var->vsync_len = timing->vsync_end - timing->vsync_start;
  310. /* Ouch. This breaks the rules but timing_num is only important if you
  311. * change a video mode */
  312. par->timing_num = min_mode;
  313. printk(KERN_INFO "sgivwfb: new video mode xres=%d yres=%d bpp=%d\n",
  314. var->xres, var->yres, var->bits_per_pixel);
  315. printk(KERN_INFO " vxres=%d vyres=%d\n", var->xres_virtual,
  316. var->yres_virtual);
  317. return 0;
  318. }
  319. /*
  320. * Setup flatpanel related registers.
  321. */
  322. static void sgivwfb_setup_flatpanel(struct sgivw_par *par, struct dbe_timing_info *currentTiming)
  323. {
  324. int fp_wid, fp_hgt, fp_vbs, fp_vbe;
  325. u32 outputVal = 0;
  326. SET_DBE_FIELD(VT_FLAGS, HDRV_INVERT, outputVal,
  327. (currentTiming->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1);
  328. SET_DBE_FIELD(VT_FLAGS, VDRV_INVERT, outputVal,
  329. (currentTiming->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1);
  330. DBE_SETREG(vt_flags, outputVal);
  331. /* Turn on the flat panel */
  332. switch (flatpanel_id) {
  333. case FLATPANEL_SGI_1600SW:
  334. fp_wid = 1600;
  335. fp_hgt = 1024;
  336. fp_vbs = 0;
  337. fp_vbe = 1600;
  338. currentTiming->pll_m = 4;
  339. currentTiming->pll_n = 1;
  340. currentTiming->pll_p = 0;
  341. break;
  342. default:
  343. fp_wid = fp_hgt = fp_vbs = fp_vbe = 0xfff;
  344. }
  345. outputVal = 0;
  346. SET_DBE_FIELD(FP_DE, FP_DE_ON, outputVal, fp_vbs);
  347. SET_DBE_FIELD(FP_DE, FP_DE_OFF, outputVal, fp_vbe);
  348. DBE_SETREG(fp_de, outputVal);
  349. outputVal = 0;
  350. SET_DBE_FIELD(FP_HDRV, FP_HDRV_OFF, outputVal, fp_wid);
  351. DBE_SETREG(fp_hdrv, outputVal);
  352. outputVal = 0;
  353. SET_DBE_FIELD(FP_VDRV, FP_VDRV_ON, outputVal, 1);
  354. SET_DBE_FIELD(FP_VDRV, FP_VDRV_OFF, outputVal, fp_hgt + 1);
  355. DBE_SETREG(fp_vdrv, outputVal);
  356. }
  357. /*
  358. * Set the hardware according to 'par'.
  359. */
  360. static int sgivwfb_set_par(struct fb_info *info)
  361. {
  362. struct sgivw_par *par = info->par;
  363. int i, j, htmp, temp;
  364. u32 readVal, outputVal;
  365. int wholeTilesX, maxPixelsPerTileX;
  366. int frmWrite1, frmWrite2, frmWrite3b;
  367. struct dbe_timing_info *currentTiming; /* Current Video Timing */
  368. int xpmax, ypmax; // Monitor resolution
  369. int bytesPerPixel; // Bytes per pixel
  370. currentTiming = &dbeVTimings[par->timing_num];
  371. bytesPerPixel = bytes_per_pixel(info->var.bits_per_pixel);
  372. xpmax = currentTiming->width;
  373. ypmax = currentTiming->height;
  374. /* dbe_InitGraphicsBase(); */
  375. /* Turn on dotclock PLL */
  376. DBE_SETREG(ctrlstat, 0x20000000);
  377. dbe_TurnOffDma(par);
  378. /* dbe_CalculateScreenParams(); */
  379. maxPixelsPerTileX = 512 / bytesPerPixel;
  380. wholeTilesX = xpmax / maxPixelsPerTileX;
  381. if (wholeTilesX * maxPixelsPerTileX < xpmax)
  382. wholeTilesX++;
  383. printk(KERN_DEBUG "sgivwfb: pixPerTile=%d wholeTilesX=%d\n",
  384. maxPixelsPerTileX, wholeTilesX);
  385. /* dbe_InitGammaMap(); */
  386. udelay(10);
  387. for (i = 0; i < 256; i++) {
  388. DBE_ISETREG(gmap, i, (i << 24) | (i << 16) | (i << 8));
  389. }
  390. /* dbe_TurnOn(); */
  391. DBE_GETREG(vt_xy, readVal);
  392. if (GET_DBE_FIELD(VT_XY, VT_FREEZE, readVal) == 1) {
  393. DBE_SETREG(vt_xy, 0x00000000);
  394. udelay(1);
  395. } else
  396. dbe_TurnOffDma(par);
  397. /* dbe_Initdbe(); */
  398. for (i = 0; i < 256; i++) {
  399. for (j = 0; j < 100; j++) {
  400. DBE_GETREG(cm_fifo, readVal);
  401. if (readVal != 0x00000000)
  402. break;
  403. else
  404. udelay(10);
  405. }
  406. // DBE_ISETREG(cmap, i, 0x00000000);
  407. DBE_ISETREG(cmap, i, (i << 8) | (i << 16) | (i << 24));
  408. }
  409. /* dbe_InitFramebuffer(); */
  410. frmWrite1 = 0;
  411. SET_DBE_FIELD(FRM_SIZE_TILE, FRM_WIDTH_TILE, frmWrite1,
  412. wholeTilesX);
  413. SET_DBE_FIELD(FRM_SIZE_TILE, FRM_RHS, frmWrite1, 0);
  414. switch (bytesPerPixel) {
  415. case 1:
  416. SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
  417. DBE_FRM_DEPTH_8);
  418. break;
  419. case 2:
  420. SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
  421. DBE_FRM_DEPTH_16);
  422. break;
  423. case 4:
  424. SET_DBE_FIELD(FRM_SIZE_TILE, FRM_DEPTH, frmWrite1,
  425. DBE_FRM_DEPTH_32);
  426. break;
  427. }
  428. frmWrite2 = 0;
  429. SET_DBE_FIELD(FRM_SIZE_PIXEL, FB_HEIGHT_PIX, frmWrite2, ypmax);
  430. // Tell dbe about the framebuffer location and type
  431. // XXX What format is the FRM_TILE_PTR?? 64K aligned address?
  432. frmWrite3b = 0;
  433. SET_DBE_FIELD(FRM_CONTROL, FRM_TILE_PTR, frmWrite3b,
  434. sgivwfb_mem_phys >> 9);
  435. SET_DBE_FIELD(FRM_CONTROL, FRM_DMA_ENABLE, frmWrite3b, 1);
  436. SET_DBE_FIELD(FRM_CONTROL, FRM_LINEAR, frmWrite3b, 1);
  437. /* Initialize DIDs */
  438. outputVal = 0;
  439. switch (bytesPerPixel) {
  440. case 1:
  441. SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_I8);
  442. break;
  443. case 2:
  444. SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_RGBA5);
  445. break;
  446. case 4:
  447. SET_DBE_FIELD(WID, TYP, outputVal, DBE_CMODE_RGB8);
  448. break;
  449. }
  450. SET_DBE_FIELD(WID, BUF, outputVal, DBE_BMODE_BOTH);
  451. for (i = 0; i < 32; i++) {
  452. DBE_ISETREG(mode_regs, i, outputVal);
  453. }
  454. /* dbe_InitTiming(); */
  455. DBE_SETREG(vt_intr01, 0xffffffff);
  456. DBE_SETREG(vt_intr23, 0xffffffff);
  457. DBE_GETREG(dotclock, readVal);
  458. DBE_SETREG(dotclock, readVal & 0xffff);
  459. DBE_SETREG(vt_xymax, 0x00000000);
  460. outputVal = 0;
  461. SET_DBE_FIELD(VT_VSYNC, VT_VSYNC_ON, outputVal,
  462. currentTiming->vsync_start);
  463. SET_DBE_FIELD(VT_VSYNC, VT_VSYNC_OFF, outputVal,
  464. currentTiming->vsync_end);
  465. DBE_SETREG(vt_vsync, outputVal);
  466. outputVal = 0;
  467. SET_DBE_FIELD(VT_HSYNC, VT_HSYNC_ON, outputVal,
  468. currentTiming->hsync_start);
  469. SET_DBE_FIELD(VT_HSYNC, VT_HSYNC_OFF, outputVal,
  470. currentTiming->hsync_end);
  471. DBE_SETREG(vt_hsync, outputVal);
  472. outputVal = 0;
  473. SET_DBE_FIELD(VT_VBLANK, VT_VBLANK_ON, outputVal,
  474. currentTiming->vblank_start);
  475. SET_DBE_FIELD(VT_VBLANK, VT_VBLANK_OFF, outputVal,
  476. currentTiming->vblank_end);
  477. DBE_SETREG(vt_vblank, outputVal);
  478. outputVal = 0;
  479. SET_DBE_FIELD(VT_HBLANK, VT_HBLANK_ON, outputVal,
  480. currentTiming->hblank_start);
  481. SET_DBE_FIELD(VT_HBLANK, VT_HBLANK_OFF, outputVal,
  482. currentTiming->hblank_end - 3);
  483. DBE_SETREG(vt_hblank, outputVal);
  484. outputVal = 0;
  485. SET_DBE_FIELD(VT_VCMAP, VT_VCMAP_ON, outputVal,
  486. currentTiming->vblank_start);
  487. SET_DBE_FIELD(VT_VCMAP, VT_VCMAP_OFF, outputVal,
  488. currentTiming->vblank_end);
  489. DBE_SETREG(vt_vcmap, outputVal);
  490. outputVal = 0;
  491. SET_DBE_FIELD(VT_HCMAP, VT_HCMAP_ON, outputVal,
  492. currentTiming->hblank_start);
  493. SET_DBE_FIELD(VT_HCMAP, VT_HCMAP_OFF, outputVal,
  494. currentTiming->hblank_end - 3);
  495. DBE_SETREG(vt_hcmap, outputVal);
  496. if (flatpanel_id != -1)
  497. sgivwfb_setup_flatpanel(par, currentTiming);
  498. outputVal = 0;
  499. temp = currentTiming->vblank_start - currentTiming->vblank_end - 1;
  500. if (temp > 0)
  501. temp = -temp;
  502. SET_DBE_FIELD(DID_START_XY, DID_STARTY, outputVal, (u32) temp);
  503. if (currentTiming->hblank_end >= 20)
  504. SET_DBE_FIELD(DID_START_XY, DID_STARTX, outputVal,
  505. currentTiming->hblank_end - 20);
  506. else
  507. SET_DBE_FIELD(DID_START_XY, DID_STARTX, outputVal,
  508. currentTiming->htotal - (20 -
  509. currentTiming->
  510. hblank_end));
  511. DBE_SETREG(did_start_xy, outputVal);
  512. outputVal = 0;
  513. SET_DBE_FIELD(CRS_START_XY, CRS_STARTY, outputVal,
  514. (u32) (temp + 1));
  515. if (currentTiming->hblank_end >= DBE_CRS_MAGIC)
  516. SET_DBE_FIELD(CRS_START_XY, CRS_STARTX, outputVal,
  517. currentTiming->hblank_end - DBE_CRS_MAGIC);
  518. else
  519. SET_DBE_FIELD(CRS_START_XY, CRS_STARTX, outputVal,
  520. currentTiming->htotal - (DBE_CRS_MAGIC -
  521. currentTiming->
  522. hblank_end));
  523. DBE_SETREG(crs_start_xy, outputVal);
  524. outputVal = 0;
  525. SET_DBE_FIELD(VC_START_XY, VC_STARTY, outputVal, (u32) temp);
  526. SET_DBE_FIELD(VC_START_XY, VC_STARTX, outputVal,
  527. currentTiming->hblank_end - 4);
  528. DBE_SETREG(vc_start_xy, outputVal);
  529. DBE_SETREG(frm_size_tile, frmWrite1);
  530. DBE_SETREG(frm_size_pixel, frmWrite2);
  531. outputVal = 0;
  532. SET_DBE_FIELD(DOTCLK, M, outputVal, currentTiming->pll_m - 1);
  533. SET_DBE_FIELD(DOTCLK, N, outputVal, currentTiming->pll_n - 1);
  534. SET_DBE_FIELD(DOTCLK, P, outputVal, currentTiming->pll_p);
  535. SET_DBE_FIELD(DOTCLK, RUN, outputVal, 1);
  536. DBE_SETREG(dotclock, outputVal);
  537. udelay(11 * 1000);
  538. DBE_SETREG(vt_vpixen, 0xffffff);
  539. DBE_SETREG(vt_hpixen, 0xffffff);
  540. outputVal = 0;
  541. SET_DBE_FIELD(VT_XYMAX, VT_MAXX, outputVal, currentTiming->htotal);
  542. SET_DBE_FIELD(VT_XYMAX, VT_MAXY, outputVal, currentTiming->vtotal);
  543. DBE_SETREG(vt_xymax, outputVal);
  544. outputVal = frmWrite1;
  545. SET_DBE_FIELD(FRM_SIZE_TILE, FRM_FIFO_RESET, outputVal, 1);
  546. DBE_SETREG(frm_size_tile, outputVal);
  547. DBE_SETREG(frm_size_tile, frmWrite1);
  548. outputVal = 0;
  549. SET_DBE_FIELD(OVR_WIDTH_TILE, OVR_FIFO_RESET, outputVal, 1);
  550. DBE_SETREG(ovr_width_tile, outputVal);
  551. DBE_SETREG(ovr_width_tile, 0);
  552. DBE_SETREG(frm_control, frmWrite3b);
  553. DBE_SETREG(did_control, 0);
  554. // Wait for dbe to take frame settings
  555. for (i = 0; i < 100000; i++) {
  556. DBE_GETREG(frm_inhwctrl, readVal);
  557. if (GET_DBE_FIELD(FRM_INHWCTRL, FRM_DMA_ENABLE, readVal) !=
  558. 0)
  559. break;
  560. else
  561. udelay(1);
  562. }
  563. if (i == 100000)
  564. printk(KERN_INFO
  565. "sgivwfb: timeout waiting for frame DMA enable.\n");
  566. outputVal = 0;
  567. htmp = currentTiming->hblank_end - 19;
  568. if (htmp < 0)
  569. htmp += currentTiming->htotal; /* allow blank to wrap around */
  570. SET_DBE_FIELD(VT_HPIXEN, VT_HPIXEN_ON, outputVal, htmp);
  571. SET_DBE_FIELD(VT_HPIXEN, VT_HPIXEN_OFF, outputVal,
  572. ((htmp + currentTiming->width -
  573. 2) % currentTiming->htotal));
  574. DBE_SETREG(vt_hpixen, outputVal);
  575. outputVal = 0;
  576. SET_DBE_FIELD(VT_VPIXEN, VT_VPIXEN_OFF, outputVal,
  577. currentTiming->vblank_start);
  578. SET_DBE_FIELD(VT_VPIXEN, VT_VPIXEN_ON, outputVal,
  579. currentTiming->vblank_end);
  580. DBE_SETREG(vt_vpixen, outputVal);
  581. // Turn off mouse cursor
  582. par->regs->crs_ctl = 0;
  583. // XXX What's this section for??
  584. DBE_GETREG(ctrlstat, readVal);
  585. readVal &= 0x02000000;
  586. if (readVal != 0) {
  587. DBE_SETREG(ctrlstat, 0x30000000);
  588. }
  589. return 0;
  590. }
  591. /*
  592. * Set a single color register. The values supplied are already
  593. * rounded down to the hardware's capabilities (according to the
  594. * entries in the var structure). Return != 0 for invalid regno.
  595. */
  596. static int sgivwfb_setcolreg(u_int regno, u_int red, u_int green,
  597. u_int blue, u_int transp,
  598. struct fb_info *info)
  599. {
  600. struct sgivw_par *par = (struct sgivw_par *) info->par;
  601. if (regno > 255)
  602. return 1;
  603. red >>= 8;
  604. green >>= 8;
  605. blue >>= 8;
  606. /* wait for the color map FIFO to have a free entry */
  607. while (par->cmap_fifo == 0)
  608. par->cmap_fifo = par->regs->cm_fifo;
  609. par->regs->cmap[regno] = (red << 24) | (green << 16) | (blue << 8);
  610. par->cmap_fifo--; /* assume FIFO is filling up */
  611. return 0;
  612. }
  613. static int sgivwfb_mmap(struct fb_info *info,
  614. struct vm_area_struct *vma)
  615. {
  616. unsigned long size = vma->vm_end - vma->vm_start;
  617. unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
  618. if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
  619. return -EINVAL;
  620. if (offset + size > sgivwfb_mem_size)
  621. return -EINVAL;
  622. offset += sgivwfb_mem_phys;
  623. pgprot_val(vma->vm_page_prot) =
  624. pgprot_val(vma->vm_page_prot) | _PAGE_PCD;
  625. vma->vm_flags |= VM_IO;
  626. if (remap_pfn_range(vma, vma->vm_start, offset >> PAGE_SHIFT,
  627. size, vma->vm_page_prot))
  628. return -EAGAIN;
  629. printk(KERN_DEBUG "sgivwfb: mmap framebuffer P(%lx)->V(%lx)\n",
  630. offset, vma->vm_start);
  631. return 0;
  632. }
  633. int __init sgivwfb_setup(char *options)
  634. {
  635. char *this_opt;
  636. if (!options || !*options)
  637. return 0;
  638. while ((this_opt = strsep(&options, ",")) != NULL) {
  639. if (!strncmp(this_opt, "monitor:", 8)) {
  640. if (!strncmp(this_opt + 8, "crt", 3))
  641. flatpanel_id = -1;
  642. else if (!strncmp(this_opt + 8, "1600sw", 6))
  643. flatpanel_id = FLATPANEL_SGI_1600SW;
  644. }
  645. }
  646. return 0;
  647. }
  648. /*
  649. * Initialisation
  650. */
  651. static int __init sgivwfb_probe(struct platform_device *dev)
  652. {
  653. struct sgivw_par *par;
  654. struct fb_info *info;
  655. char *monitor;
  656. info = framebuffer_alloc(sizeof(struct sgivw_par) + sizeof(u32) * 256, &dev->dev);
  657. if (!info)
  658. return -ENOMEM;
  659. par = info->par;
  660. if (!request_mem_region(DBE_REG_PHYS, DBE_REG_SIZE, "sgivwfb")) {
  661. printk(KERN_ERR "sgivwfb: couldn't reserve mmio region\n");
  662. framebuffer_release(info);
  663. return -EBUSY;
  664. }
  665. par->regs = (struct asregs *) ioremap_nocache(DBE_REG_PHYS, DBE_REG_SIZE);
  666. if (!par->regs) {
  667. printk(KERN_ERR "sgivwfb: couldn't ioremap registers\n");
  668. goto fail_ioremap_regs;
  669. }
  670. mtrr_add(sgivwfb_mem_phys, sgivwfb_mem_size, MTRR_TYPE_WRCOMB, 1);
  671. sgivwfb_fix.smem_start = sgivwfb_mem_phys;
  672. sgivwfb_fix.smem_len = sgivwfb_mem_size;
  673. sgivwfb_fix.ywrapstep = ywrap;
  674. sgivwfb_fix.ypanstep = ypan;
  675. info->fix = sgivwfb_fix;
  676. switch (flatpanel_id) {
  677. case FLATPANEL_SGI_1600SW:
  678. info->var = sgivwfb_var1600sw;
  679. monitor = "SGI 1600SW flatpanel";
  680. break;
  681. default:
  682. info->var = sgivwfb_var;
  683. monitor = "CRT";
  684. }
  685. printk(KERN_INFO "sgivwfb: %s monitor selected\n", monitor);
  686. info->fbops = &sgivwfb_ops;
  687. info->pseudo_palette = (void *) (par + 1);
  688. info->flags = FBINFO_DEFAULT;
  689. info->screen_base = ioremap_nocache((unsigned long) sgivwfb_mem_phys, sgivwfb_mem_size);
  690. if (!info->screen_base) {
  691. printk(KERN_ERR "sgivwfb: couldn't ioremap screen_base\n");
  692. goto fail_ioremap_fbmem;
  693. }
  694. if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
  695. goto fail_color_map;
  696. if (register_framebuffer(info) < 0) {
  697. printk(KERN_ERR "sgivwfb: couldn't register framebuffer\n");
  698. goto fail_register_framebuffer;
  699. }
  700. platform_set_drvdata(dev, info);
  701. printk(KERN_INFO "fb%d: SGI DBE frame buffer device, using %ldK of video memory at %#lx\n",
  702. info->node, sgivwfb_mem_size >> 10, sgivwfb_mem_phys);
  703. return 0;
  704. fail_register_framebuffer:
  705. fb_dealloc_cmap(&info->cmap);
  706. fail_color_map:
  707. iounmap((char *) info->screen_base);
  708. fail_ioremap_fbmem:
  709. iounmap(par->regs);
  710. fail_ioremap_regs:
  711. release_mem_region(DBE_REG_PHYS, DBE_REG_SIZE);
  712. framebuffer_release(info);
  713. return -ENXIO;
  714. }
  715. static int sgivwfb_remove(struct platform_device *dev)
  716. {
  717. struct fb_info *info = platform_get_drvdata(dev);
  718. if (info) {
  719. struct sgivw_par *par = info->par;
  720. unregister_framebuffer(info);
  721. dbe_TurnOffDma(par);
  722. iounmap(par->regs);
  723. iounmap(info->screen_base);
  724. release_mem_region(DBE_REG_PHYS, DBE_REG_SIZE);
  725. }
  726. return 0;
  727. }
  728. static struct platform_driver sgivwfb_driver = {
  729. .probe = sgivwfb_probe,
  730. .remove = sgivwfb_remove,
  731. .driver = {
  732. .name = "sgivwfb",
  733. },
  734. };
  735. static struct platform_device *sgivwfb_device;
  736. int __init sgivwfb_init(void)
  737. {
  738. int ret;
  739. #ifndef MODULE
  740. char *option = NULL;
  741. if (fb_get_options("sgivwfb", &option))
  742. return -ENODEV;
  743. sgivwfb_setup(option);
  744. #endif
  745. ret = platform_driver_register(&sgivwfb_driver);
  746. if (!ret) {
  747. sgivwfb_device = platform_device_alloc("sgivwfb", 0);
  748. if (sgivwfb_device) {
  749. ret = platform_device_add(sgivwfb_device);
  750. } else
  751. ret = -ENOMEM;
  752. if (ret) {
  753. platform_driver_unregister(&sgivwfb_driver);
  754. platform_device_put(sgivwfb_device);
  755. }
  756. }
  757. return ret;
  758. }
  759. module_init(sgivwfb_init);
  760. #ifdef MODULE
  761. MODULE_LICENSE("GPL");
  762. static void __exit sgivwfb_exit(void)
  763. {
  764. platform_device_unregister(sgivwfb_device);
  765. platform_driver_unregister(&sgivwfb_driver);
  766. }
  767. module_exit(sgivwfb_exit);
  768. #endif /* MODULE */