s3fb.c 31 KB

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  1. /*
  2. * linux/drivers/video/s3fb.c -- Frame buffer device driver for S3 Trio/Virge
  3. *
  4. * Copyright (c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file COPYING in the main directory of this archive for
  8. * more details.
  9. *
  10. * Code is based on David Boucher's viafb (http://davesdomain.org.uk/viafb/)
  11. * which is based on the code of neofb.
  12. */
  13. #include <linux/version.h>
  14. #include <linux/module.h>
  15. #include <linux/kernel.h>
  16. #include <linux/errno.h>
  17. #include <linux/string.h>
  18. #include <linux/mm.h>
  19. #include <linux/tty.h>
  20. #include <linux/slab.h>
  21. #include <linux/delay.h>
  22. #include <linux/fb.h>
  23. #include <linux/svga.h>
  24. #include <linux/init.h>
  25. #include <linux/pci.h>
  26. #include <linux/console.h> /* Why should fb driver call console functions? because acquire_console_sem() */
  27. #include <video/vga.h>
  28. #ifdef CONFIG_MTRR
  29. #include <asm/mtrr.h>
  30. #endif
  31. struct s3fb_info {
  32. int chip, rev, mclk_freq;
  33. int mtrr_reg;
  34. struct vgastate state;
  35. struct mutex open_lock;
  36. unsigned int ref_count;
  37. u32 pseudo_palette[16];
  38. };
  39. /* ------------------------------------------------------------------------- */
  40. static const struct svga_fb_format s3fb_formats[] = {
  41. { 0, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  42. FB_TYPE_TEXT, FB_AUX_TEXT_SVGA_STEP4, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  43. { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  44. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  45. { 4, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 1,
  46. FB_TYPE_INTERLEAVED_PLANES, 1, FB_VISUAL_PSEUDOCOLOR, 8, 16},
  47. { 8, {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0}, 0,
  48. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_PSEUDOCOLOR, 4, 8},
  49. {16, {10, 5, 0}, {5, 5, 0}, {0, 5, 0}, {0, 0, 0}, 0,
  50. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
  51. {16, {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0}, 0,
  52. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 2, 4},
  53. {24, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  54. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
  55. {32, {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {0, 0, 0}, 0,
  56. FB_TYPE_PACKED_PIXELS, 0, FB_VISUAL_TRUECOLOR, 1, 2},
  57. SVGA_FORMAT_END
  58. };
  59. static const struct svga_pll s3_pll = {3, 129, 3, 33, 0, 3,
  60. 60000, 240000, 14318};
  61. static const int s3_memsizes[] = {4096, 0, 3072, 8192, 2048, 6144, 1024, 512};
  62. static const char * const s3_names[] = {"S3 Unknown", "S3 Trio32", "S3 Trio64", "S3 Trio64V+",
  63. "S3 Trio64UV+", "S3 Trio64V2/DX", "S3 Trio64V2/GX",
  64. "S3 Plato/PX", "S3 Aurora64VP", "S3 Virge",
  65. "S3 Virge/VX", "S3 Virge/DX", "S3 Virge/GX",
  66. "S3 Virge/GX2", "S3 Virge/GX2P", "S3 Virge/GX2P"};
  67. #define CHIP_UNKNOWN 0x00
  68. #define CHIP_732_TRIO32 0x01
  69. #define CHIP_764_TRIO64 0x02
  70. #define CHIP_765_TRIO64VP 0x03
  71. #define CHIP_767_TRIO64UVP 0x04
  72. #define CHIP_775_TRIO64V2_DX 0x05
  73. #define CHIP_785_TRIO64V2_GX 0x06
  74. #define CHIP_551_PLATO_PX 0x07
  75. #define CHIP_M65_AURORA64VP 0x08
  76. #define CHIP_325_VIRGE 0x09
  77. #define CHIP_988_VIRGE_VX 0x0A
  78. #define CHIP_375_VIRGE_DX 0x0B
  79. #define CHIP_385_VIRGE_GX 0x0C
  80. #define CHIP_356_VIRGE_GX2 0x0D
  81. #define CHIP_357_VIRGE_GX2P 0x0E
  82. #define CHIP_359_VIRGE_GX2P 0x0F
  83. #define CHIP_XXX_TRIO 0x80
  84. #define CHIP_XXX_TRIO64V2_DXGX 0x81
  85. #define CHIP_XXX_VIRGE_DXGX 0x82
  86. #define CHIP_UNDECIDED_FLAG 0x80
  87. #define CHIP_MASK 0xFF
  88. /* CRT timing register sets */
  89. static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
  90. static const struct vga_regset s3_h_display_regs[] = {{0x01, 0, 7}, {0x5D, 1, 1}, VGA_REGSET_END};
  91. static const struct vga_regset s3_h_blank_start_regs[] = {{0x02, 0, 7}, {0x5D, 2, 2}, VGA_REGSET_END};
  92. static const struct vga_regset s3_h_blank_end_regs[] = {{0x03, 0, 4}, {0x05, 7, 7}, VGA_REGSET_END};
  93. static const struct vga_regset s3_h_sync_start_regs[] = {{0x04, 0, 7}, {0x5D, 4, 4}, VGA_REGSET_END};
  94. static const struct vga_regset s3_h_sync_end_regs[] = {{0x05, 0, 4}, VGA_REGSET_END};
  95. static const struct vga_regset s3_v_total_regs[] = {{0x06, 0, 7}, {0x07, 0, 0}, {0x07, 5, 5}, {0x5E, 0, 0}, VGA_REGSET_END};
  96. static const struct vga_regset s3_v_display_regs[] = {{0x12, 0, 7}, {0x07, 1, 1}, {0x07, 6, 6}, {0x5E, 1, 1}, VGA_REGSET_END};
  97. static const struct vga_regset s3_v_blank_start_regs[] = {{0x15, 0, 7}, {0x07, 3, 3}, {0x09, 5, 5}, {0x5E, 2, 2}, VGA_REGSET_END};
  98. static const struct vga_regset s3_v_blank_end_regs[] = {{0x16, 0, 7}, VGA_REGSET_END};
  99. static const struct vga_regset s3_v_sync_start_regs[] = {{0x10, 0, 7}, {0x07, 2, 2}, {0x07, 7, 7}, {0x5E, 4, 4}, VGA_REGSET_END};
  100. static const struct vga_regset s3_v_sync_end_regs[] = {{0x11, 0, 3}, VGA_REGSET_END};
  101. static const struct vga_regset s3_line_compare_regs[] = {{0x18, 0, 7}, {0x07, 4, 4}, {0x09, 6, 6}, {0x5E, 6, 6}, VGA_REGSET_END};
  102. static const struct vga_regset s3_start_address_regs[] = {{0x0d, 0, 7}, {0x0c, 0, 7}, {0x31, 4, 5}, {0x51, 0, 1}, VGA_REGSET_END};
  103. static const struct vga_regset s3_offset_regs[] = {{0x13, 0, 7}, {0x51, 4, 5}, VGA_REGSET_END}; /* set 0x43 bit 2 to 0 */
  104. static const struct svga_timing_regs s3_timing_regs = {
  105. s3_h_total_regs, s3_h_display_regs, s3_h_blank_start_regs,
  106. s3_h_blank_end_regs, s3_h_sync_start_regs, s3_h_sync_end_regs,
  107. s3_v_total_regs, s3_v_display_regs, s3_v_blank_start_regs,
  108. s3_v_blank_end_regs, s3_v_sync_start_regs, s3_v_sync_end_regs,
  109. };
  110. /* ------------------------------------------------------------------------- */
  111. /* Module parameters */
  112. static char *mode = "640x480-8@60";
  113. #ifdef CONFIG_MTRR
  114. static int mtrr = 1;
  115. #endif
  116. static int fasttext = 1;
  117. MODULE_AUTHOR("(c) 2006-2007 Ondrej Zajicek <santiago@crfreenet.org>");
  118. MODULE_LICENSE("GPL");
  119. MODULE_DESCRIPTION("fbdev driver for S3 Trio/Virge");
  120. module_param(mode, charp, 0444);
  121. MODULE_PARM_DESC(mode, "Default video mode ('640x480-8@60', etc)");
  122. #ifdef CONFIG_MTRR
  123. module_param(mtrr, int, 0444);
  124. MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
  125. #endif
  126. module_param(fasttext, int, 0644);
  127. MODULE_PARM_DESC(fasttext, "Enable S3 fast text mode (1=enable, 0=disable, default=1)");
  128. /* ------------------------------------------------------------------------- */
  129. /* Set font in S3 fast text mode */
  130. static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
  131. {
  132. const u8 *font = map->data;
  133. u8* fb = (u8 *) info->screen_base;
  134. int i, c;
  135. if ((map->width != 8) || (map->height != 16) ||
  136. (map->depth != 1) || (map->length != 256)) {
  137. printk(KERN_ERR "fb%d: unsupported font parameters: width %d, height %d, depth %d, length %d\n",
  138. info->node, map->width, map->height, map->depth, map->length);
  139. return;
  140. }
  141. fb += 2;
  142. for (i = 0; i < map->height; i++) {
  143. for (c = 0; c < map->length; c++) {
  144. fb[c * 4] = font[c * map->height + i];
  145. }
  146. fb += 1024;
  147. }
  148. }
  149. static struct fb_tile_ops s3fb_tile_ops = {
  150. .fb_settile = svga_settile,
  151. .fb_tilecopy = svga_tilecopy,
  152. .fb_tilefill = svga_tilefill,
  153. .fb_tileblit = svga_tileblit,
  154. .fb_tilecursor = svga_tilecursor,
  155. };
  156. static struct fb_tile_ops s3fb_fast_tile_ops = {
  157. .fb_settile = s3fb_settile_fast,
  158. .fb_tilecopy = svga_tilecopy,
  159. .fb_tilefill = svga_tilefill,
  160. .fb_tileblit = svga_tileblit,
  161. .fb_tilecursor = svga_tilecursor,
  162. };
  163. /* ------------------------------------------------------------------------- */
  164. /* image data is MSB-first, fb structure is MSB-first too */
  165. static inline u32 expand_color(u32 c)
  166. {
  167. return ((c & 1) | ((c & 2) << 7) | ((c & 4) << 14) | ((c & 8) << 21)) * 0xFF;
  168. }
  169. /* s3fb_iplan_imageblit silently assumes that almost everything is 8-pixel aligned */
  170. static void s3fb_iplan_imageblit(struct fb_info *info, const struct fb_image *image)
  171. {
  172. u32 fg = expand_color(image->fg_color);
  173. u32 bg = expand_color(image->bg_color);
  174. const u8 *src1, *src;
  175. u8 __iomem *dst1;
  176. u32 __iomem *dst;
  177. u32 val;
  178. int x, y;
  179. src1 = image->data;
  180. dst1 = info->screen_base + (image->dy * info->fix.line_length)
  181. + ((image->dx / 8) * 4);
  182. for (y = 0; y < image->height; y++) {
  183. src = src1;
  184. dst = (u32 __iomem *) dst1;
  185. for (x = 0; x < image->width; x += 8) {
  186. val = *(src++) * 0x01010101;
  187. val = (val & fg) | (~val & bg);
  188. fb_writel(val, dst++);
  189. }
  190. src1 += image->width / 8;
  191. dst1 += info->fix.line_length;
  192. }
  193. }
  194. /* s3fb_iplan_fillrect silently assumes that almost everything is 8-pixel aligned */
  195. static void s3fb_iplan_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  196. {
  197. u32 fg = expand_color(rect->color);
  198. u8 __iomem *dst1;
  199. u32 __iomem *dst;
  200. int x, y;
  201. dst1 = info->screen_base + (rect->dy * info->fix.line_length)
  202. + ((rect->dx / 8) * 4);
  203. for (y = 0; y < rect->height; y++) {
  204. dst = (u32 __iomem *) dst1;
  205. for (x = 0; x < rect->width; x += 8) {
  206. fb_writel(fg, dst++);
  207. }
  208. dst1 += info->fix.line_length;
  209. }
  210. }
  211. /* image data is MSB-first, fb structure is high-nibble-in-low-byte-first */
  212. static inline u32 expand_pixel(u32 c)
  213. {
  214. return (((c & 1) << 24) | ((c & 2) << 27) | ((c & 4) << 14) | ((c & 8) << 17) |
  215. ((c & 16) << 4) | ((c & 32) << 7) | ((c & 64) >> 6) | ((c & 128) >> 3)) * 0xF;
  216. }
  217. /* s3fb_cfb4_imageblit silently assumes that almost everything is 8-pixel aligned */
  218. static void s3fb_cfb4_imageblit(struct fb_info *info, const struct fb_image *image)
  219. {
  220. u32 fg = image->fg_color * 0x11111111;
  221. u32 bg = image->bg_color * 0x11111111;
  222. const u8 *src1, *src;
  223. u8 __iomem *dst1;
  224. u32 __iomem *dst;
  225. u32 val;
  226. int x, y;
  227. src1 = image->data;
  228. dst1 = info->screen_base + (image->dy * info->fix.line_length)
  229. + ((image->dx / 8) * 4);
  230. for (y = 0; y < image->height; y++) {
  231. src = src1;
  232. dst = (u32 __iomem *) dst1;
  233. for (x = 0; x < image->width; x += 8) {
  234. val = expand_pixel(*(src++));
  235. val = (val & fg) | (~val & bg);
  236. fb_writel(val, dst++);
  237. }
  238. src1 += image->width / 8;
  239. dst1 += info->fix.line_length;
  240. }
  241. }
  242. static void s3fb_imageblit(struct fb_info *info, const struct fb_image *image)
  243. {
  244. if ((info->var.bits_per_pixel == 4) && (image->depth == 1)
  245. && ((image->width % 8) == 0) && ((image->dx % 8) == 0)) {
  246. if (info->fix.type == FB_TYPE_INTERLEAVED_PLANES)
  247. s3fb_iplan_imageblit(info, image);
  248. else
  249. s3fb_cfb4_imageblit(info, image);
  250. } else
  251. cfb_imageblit(info, image);
  252. }
  253. static void s3fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
  254. {
  255. if ((info->var.bits_per_pixel == 4)
  256. && ((rect->width % 8) == 0) && ((rect->dx % 8) == 0)
  257. && (info->fix.type == FB_TYPE_INTERLEAVED_PLANES))
  258. s3fb_iplan_fillrect(info, rect);
  259. else
  260. cfb_fillrect(info, rect);
  261. }
  262. /* ------------------------------------------------------------------------- */
  263. static void s3_set_pixclock(struct fb_info *info, u32 pixclock)
  264. {
  265. u16 m, n, r;
  266. u8 regval;
  267. svga_compute_pll(&s3_pll, 1000000000 / pixclock, &m, &n, &r, info->node);
  268. /* Set VGA misc register */
  269. regval = vga_r(NULL, VGA_MIS_R);
  270. vga_w(NULL, VGA_MIS_W, regval | VGA_MIS_ENB_PLL_LOAD);
  271. /* Set S3 clock registers */
  272. vga_wseq(NULL, 0x12, ((n - 2) | (r << 5)));
  273. vga_wseq(NULL, 0x13, m - 2);
  274. udelay(1000);
  275. /* Activate clock - write 0, 1, 0 to seq/15 bit 5 */
  276. regval = vga_rseq (NULL, 0x15); /* | 0x80; */
  277. vga_wseq(NULL, 0x15, regval & ~(1<<5));
  278. vga_wseq(NULL, 0x15, regval | (1<<5));
  279. vga_wseq(NULL, 0x15, regval & ~(1<<5));
  280. }
  281. /* Open framebuffer */
  282. static int s3fb_open(struct fb_info *info, int user)
  283. {
  284. struct s3fb_info *par = info->par;
  285. mutex_lock(&(par->open_lock));
  286. if (par->ref_count == 0) {
  287. memset(&(par->state), 0, sizeof(struct vgastate));
  288. par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS | VGA_SAVE_CMAP;
  289. par->state.num_crtc = 0x70;
  290. par->state.num_seq = 0x20;
  291. save_vga(&(par->state));
  292. }
  293. par->ref_count++;
  294. mutex_unlock(&(par->open_lock));
  295. return 0;
  296. }
  297. /* Close framebuffer */
  298. static int s3fb_release(struct fb_info *info, int user)
  299. {
  300. struct s3fb_info *par = info->par;
  301. mutex_lock(&(par->open_lock));
  302. if (par->ref_count == 0) {
  303. mutex_unlock(&(par->open_lock));
  304. return -EINVAL;
  305. }
  306. if (par->ref_count == 1)
  307. restore_vga(&(par->state));
  308. par->ref_count--;
  309. mutex_unlock(&(par->open_lock));
  310. return 0;
  311. }
  312. /* Validate passed in var */
  313. static int s3fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  314. {
  315. struct s3fb_info *par = info->par;
  316. int rv, mem, step;
  317. /* Find appropriate format */
  318. rv = svga_match_format (s3fb_formats, var, NULL);
  319. if ((rv < 0) || ((par->chip == CHIP_988_VIRGE_VX) ? (rv == 7) : (rv == 6)))
  320. { /* 24bpp on VIRGE VX, 32bpp on others */
  321. printk(KERN_ERR "fb%d: unsupported mode requested\n", info->node);
  322. return rv;
  323. }
  324. /* Do not allow to have real resoulution larger than virtual */
  325. if (var->xres > var->xres_virtual)
  326. var->xres_virtual = var->xres;
  327. if (var->yres > var->yres_virtual)
  328. var->yres_virtual = var->yres;
  329. /* Round up xres_virtual to have proper alignment of lines */
  330. step = s3fb_formats[rv].xresstep - 1;
  331. var->xres_virtual = (var->xres_virtual+step) & ~step;
  332. /* Check whether have enough memory */
  333. mem = ((var->bits_per_pixel * var->xres_virtual) >> 3) * var->yres_virtual;
  334. if (mem > info->screen_size)
  335. {
  336. printk(KERN_ERR "fb%d: not enough framebuffer memory (%d kB requested , %d kB available)\n",
  337. info->node, mem >> 10, (unsigned int) (info->screen_size >> 10));
  338. return -EINVAL;
  339. }
  340. rv = svga_check_timings (&s3_timing_regs, var, info->node);
  341. if (rv < 0)
  342. {
  343. printk(KERN_ERR "fb%d: invalid timings requested\n", info->node);
  344. return rv;
  345. }
  346. return 0;
  347. }
  348. /* Set video mode from par */
  349. static int s3fb_set_par(struct fb_info *info)
  350. {
  351. struct s3fb_info *par = info->par;
  352. u32 value, mode, hmul, offset_value, screen_size, multiplex;
  353. u32 bpp = info->var.bits_per_pixel;
  354. if (bpp != 0) {
  355. info->fix.ypanstep = 1;
  356. info->fix.line_length = (info->var.xres_virtual * bpp) / 8;
  357. info->flags &= ~FBINFO_MISC_TILEBLITTING;
  358. info->tileops = NULL;
  359. offset_value = (info->var.xres_virtual * bpp) / 64;
  360. screen_size = info->var.yres_virtual * info->fix.line_length;
  361. } else {
  362. info->fix.ypanstep = 16;
  363. info->fix.line_length = 0;
  364. info->flags |= FBINFO_MISC_TILEBLITTING;
  365. info->tileops = fasttext ? &s3fb_fast_tile_ops : &s3fb_tile_ops;
  366. offset_value = info->var.xres_virtual / 16;
  367. screen_size = (info->var.xres_virtual * info->var.yres_virtual) / 64;
  368. }
  369. info->var.xoffset = 0;
  370. info->var.yoffset = 0;
  371. info->var.activate = FB_ACTIVATE_NOW;
  372. /* Unlock registers */
  373. vga_wcrt(NULL, 0x38, 0x48);
  374. vga_wcrt(NULL, 0x39, 0xA5);
  375. vga_wseq(NULL, 0x08, 0x06);
  376. svga_wcrt_mask(0x11, 0x00, 0x80);
  377. /* Blank screen and turn off sync */
  378. svga_wseq_mask(0x01, 0x20, 0x20);
  379. svga_wcrt_mask(0x17, 0x00, 0x80);
  380. /* Set default values */
  381. svga_set_default_gfx_regs();
  382. svga_set_default_atc_regs();
  383. svga_set_default_seq_regs();
  384. svga_set_default_crt_regs();
  385. svga_wcrt_multi(s3_line_compare_regs, 0xFFFFFFFF);
  386. svga_wcrt_multi(s3_start_address_regs, 0);
  387. /* S3 specific initialization */
  388. svga_wcrt_mask(0x58, 0x10, 0x10); /* enable linear framebuffer */
  389. svga_wcrt_mask(0x31, 0x08, 0x08); /* enable sequencer access to framebuffer above 256 kB */
  390. /* svga_wcrt_mask(0x33, 0x08, 0x08); */ /* DDR ? */
  391. /* svga_wcrt_mask(0x43, 0x01, 0x01); */ /* DDR ? */
  392. svga_wcrt_mask(0x33, 0x00, 0x08); /* no DDR ? */
  393. svga_wcrt_mask(0x43, 0x00, 0x01); /* no DDR ? */
  394. svga_wcrt_mask(0x5D, 0x00, 0x28); // Clear strange HSlen bits
  395. /* svga_wcrt_mask(0x58, 0x03, 0x03); */
  396. /* svga_wcrt_mask(0x53, 0x12, 0x13); */ /* enable MMIO */
  397. /* svga_wcrt_mask(0x40, 0x08, 0x08); */ /* enable write buffer */
  398. /* Set the offset register */
  399. pr_debug("fb%d: offset register : %d\n", info->node, offset_value);
  400. svga_wcrt_multi(s3_offset_regs, offset_value);
  401. vga_wcrt(NULL, 0x54, 0x18); /* M parameter */
  402. vga_wcrt(NULL, 0x60, 0xff); /* N parameter */
  403. vga_wcrt(NULL, 0x61, 0xff); /* L parameter */
  404. vga_wcrt(NULL, 0x62, 0xff); /* L parameter */
  405. vga_wcrt(NULL, 0x3A, 0x35);
  406. svga_wattr(0x33, 0x00);
  407. if (info->var.vmode & FB_VMODE_DOUBLE)
  408. svga_wcrt_mask(0x09, 0x80, 0x80);
  409. else
  410. svga_wcrt_mask(0x09, 0x00, 0x80);
  411. if (info->var.vmode & FB_VMODE_INTERLACED)
  412. svga_wcrt_mask(0x42, 0x20, 0x20);
  413. else
  414. svga_wcrt_mask(0x42, 0x00, 0x20);
  415. /* Disable hardware graphics cursor */
  416. svga_wcrt_mask(0x45, 0x00, 0x01);
  417. /* Disable Streams engine */
  418. svga_wcrt_mask(0x67, 0x00, 0x0C);
  419. mode = svga_match_format(s3fb_formats, &(info->var), &(info->fix));
  420. /* S3 virge DX hack */
  421. if (par->chip == CHIP_375_VIRGE_DX) {
  422. vga_wcrt(NULL, 0x86, 0x80);
  423. vga_wcrt(NULL, 0x90, 0x00);
  424. }
  425. /* S3 virge VX hack */
  426. if (par->chip == CHIP_988_VIRGE_VX) {
  427. vga_wcrt(NULL, 0x50, 0x00);
  428. vga_wcrt(NULL, 0x67, 0x50);
  429. vga_wcrt(NULL, 0x63, (mode <= 2) ? 0x90 : 0x09);
  430. vga_wcrt(NULL, 0x66, 0x90);
  431. }
  432. svga_wcrt_mask(0x31, 0x00, 0x40);
  433. multiplex = 0;
  434. hmul = 1;
  435. /* Set mode-specific register values */
  436. switch (mode) {
  437. case 0:
  438. pr_debug("fb%d: text mode\n", info->node);
  439. svga_set_textmode_vga_regs();
  440. /* Set additional registers like in 8-bit mode */
  441. svga_wcrt_mask(0x50, 0x00, 0x30);
  442. svga_wcrt_mask(0x67, 0x00, 0xF0);
  443. /* Disable enhanced mode */
  444. svga_wcrt_mask(0x3A, 0x00, 0x30);
  445. if (fasttext) {
  446. pr_debug("fb%d: high speed text mode set\n", info->node);
  447. svga_wcrt_mask(0x31, 0x40, 0x40);
  448. }
  449. break;
  450. case 1:
  451. pr_debug("fb%d: 4 bit pseudocolor\n", info->node);
  452. vga_wgfx(NULL, VGA_GFX_MODE, 0x40);
  453. /* Set additional registers like in 8-bit mode */
  454. svga_wcrt_mask(0x50, 0x00, 0x30);
  455. svga_wcrt_mask(0x67, 0x00, 0xF0);
  456. /* disable enhanced mode */
  457. svga_wcrt_mask(0x3A, 0x00, 0x30);
  458. break;
  459. case 2:
  460. pr_debug("fb%d: 4 bit pseudocolor, planar\n", info->node);
  461. /* Set additional registers like in 8-bit mode */
  462. svga_wcrt_mask(0x50, 0x00, 0x30);
  463. svga_wcrt_mask(0x67, 0x00, 0xF0);
  464. /* disable enhanced mode */
  465. svga_wcrt_mask(0x3A, 0x00, 0x30);
  466. break;
  467. case 3:
  468. pr_debug("fb%d: 8 bit pseudocolor\n", info->node);
  469. if (info->var.pixclock > 20000) {
  470. svga_wcrt_mask(0x50, 0x00, 0x30);
  471. svga_wcrt_mask(0x67, 0x00, 0xF0);
  472. } else {
  473. svga_wcrt_mask(0x50, 0x00, 0x30);
  474. svga_wcrt_mask(0x67, 0x10, 0xF0);
  475. multiplex = 1;
  476. }
  477. break;
  478. case 4:
  479. pr_debug("fb%d: 5/5/5 truecolor\n", info->node);
  480. if (par->chip == CHIP_988_VIRGE_VX) {
  481. if (info->var.pixclock > 20000)
  482. svga_wcrt_mask(0x67, 0x20, 0xF0);
  483. else
  484. svga_wcrt_mask(0x67, 0x30, 0xF0);
  485. } else {
  486. svga_wcrt_mask(0x50, 0x10, 0x30);
  487. svga_wcrt_mask(0x67, 0x30, 0xF0);
  488. hmul = 2;
  489. }
  490. break;
  491. case 5:
  492. pr_debug("fb%d: 5/6/5 truecolor\n", info->node);
  493. if (par->chip == CHIP_988_VIRGE_VX) {
  494. if (info->var.pixclock > 20000)
  495. svga_wcrt_mask(0x67, 0x40, 0xF0);
  496. else
  497. svga_wcrt_mask(0x67, 0x50, 0xF0);
  498. } else {
  499. svga_wcrt_mask(0x50, 0x10, 0x30);
  500. svga_wcrt_mask(0x67, 0x50, 0xF0);
  501. hmul = 2;
  502. }
  503. break;
  504. case 6:
  505. /* VIRGE VX case */
  506. pr_debug("fb%d: 8/8/8 truecolor\n", info->node);
  507. svga_wcrt_mask(0x67, 0xD0, 0xF0);
  508. break;
  509. case 7:
  510. pr_debug("fb%d: 8/8/8/8 truecolor\n", info->node);
  511. svga_wcrt_mask(0x50, 0x30, 0x30);
  512. svga_wcrt_mask(0x67, 0xD0, 0xF0);
  513. break;
  514. default:
  515. printk(KERN_ERR "fb%d: unsupported mode - bug\n", info->node);
  516. return -EINVAL;
  517. }
  518. if (par->chip != CHIP_988_VIRGE_VX) {
  519. svga_wseq_mask(0x15, multiplex ? 0x10 : 0x00, 0x10);
  520. svga_wseq_mask(0x18, multiplex ? 0x80 : 0x00, 0x80);
  521. }
  522. s3_set_pixclock(info, info->var.pixclock);
  523. svga_set_timings(&s3_timing_regs, &(info->var), hmul, 1,
  524. (info->var.vmode & FB_VMODE_DOUBLE) ? 2 : 1,
  525. (info->var.vmode & FB_VMODE_INTERLACED) ? 2 : 1,
  526. hmul, info->node);
  527. /* Set interlaced mode start/end register */
  528. value = info->var.xres + info->var.left_margin + info->var.right_margin + info->var.hsync_len;
  529. value = ((value * hmul) / 8) - 5;
  530. vga_wcrt(NULL, 0x3C, (value + 1) / 2);
  531. memset((u8*)info->screen_base, 0x00, screen_size);
  532. /* Device and screen back on */
  533. svga_wcrt_mask(0x17, 0x80, 0x80);
  534. svga_wseq_mask(0x01, 0x00, 0x20);
  535. return 0;
  536. }
  537. /* Set a colour register */
  538. static int s3fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  539. u_int transp, struct fb_info *fb)
  540. {
  541. switch (fb->var.bits_per_pixel) {
  542. case 0:
  543. case 4:
  544. if (regno >= 16)
  545. return -EINVAL;
  546. if ((fb->var.bits_per_pixel == 4) &&
  547. (fb->var.nonstd == 0)) {
  548. outb(0xF0, VGA_PEL_MSK);
  549. outb(regno*16, VGA_PEL_IW);
  550. } else {
  551. outb(0x0F, VGA_PEL_MSK);
  552. outb(regno, VGA_PEL_IW);
  553. }
  554. outb(red >> 10, VGA_PEL_D);
  555. outb(green >> 10, VGA_PEL_D);
  556. outb(blue >> 10, VGA_PEL_D);
  557. break;
  558. case 8:
  559. if (regno >= 256)
  560. return -EINVAL;
  561. outb(0xFF, VGA_PEL_MSK);
  562. outb(regno, VGA_PEL_IW);
  563. outb(red >> 10, VGA_PEL_D);
  564. outb(green >> 10, VGA_PEL_D);
  565. outb(blue >> 10, VGA_PEL_D);
  566. break;
  567. case 16:
  568. if (regno >= 16)
  569. return -EINVAL;
  570. if (fb->var.green.length == 5)
  571. ((u32*)fb->pseudo_palette)[regno] = ((red & 0xF800) >> 1) |
  572. ((green & 0xF800) >> 6) | ((blue & 0xF800) >> 11);
  573. else if (fb->var.green.length == 6)
  574. ((u32*)fb->pseudo_palette)[regno] = (red & 0xF800) |
  575. ((green & 0xFC00) >> 5) | ((blue & 0xF800) >> 11);
  576. else return -EINVAL;
  577. break;
  578. case 24:
  579. case 32:
  580. if (regno >= 16)
  581. return -EINVAL;
  582. ((u32*)fb->pseudo_palette)[regno] = ((transp & 0xFF00) << 16) | ((red & 0xFF00) << 8) |
  583. (green & 0xFF00) | ((blue & 0xFF00) >> 8);
  584. break;
  585. default:
  586. return -EINVAL;
  587. }
  588. return 0;
  589. }
  590. /* Set the display blanking state */
  591. static int s3fb_blank(int blank_mode, struct fb_info *info)
  592. {
  593. switch (blank_mode) {
  594. case FB_BLANK_UNBLANK:
  595. pr_debug("fb%d: unblank\n", info->node);
  596. svga_wcrt_mask(0x56, 0x00, 0x06);
  597. svga_wseq_mask(0x01, 0x00, 0x20);
  598. break;
  599. case FB_BLANK_NORMAL:
  600. pr_debug("fb%d: blank\n", info->node);
  601. svga_wcrt_mask(0x56, 0x00, 0x06);
  602. svga_wseq_mask(0x01, 0x20, 0x20);
  603. break;
  604. case FB_BLANK_HSYNC_SUSPEND:
  605. pr_debug("fb%d: hsync\n", info->node);
  606. svga_wcrt_mask(0x56, 0x02, 0x06);
  607. svga_wseq_mask(0x01, 0x20, 0x20);
  608. break;
  609. case FB_BLANK_VSYNC_SUSPEND:
  610. pr_debug("fb%d: vsync\n", info->node);
  611. svga_wcrt_mask(0x56, 0x04, 0x06);
  612. svga_wseq_mask(0x01, 0x20, 0x20);
  613. break;
  614. case FB_BLANK_POWERDOWN:
  615. pr_debug("fb%d: sync down\n", info->node);
  616. svga_wcrt_mask(0x56, 0x06, 0x06);
  617. svga_wseq_mask(0x01, 0x20, 0x20);
  618. break;
  619. }
  620. return 0;
  621. }
  622. /* Pan the display */
  623. static int s3fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) {
  624. unsigned int offset;
  625. /* Validate the offsets */
  626. if ((var->xoffset + var->xres) > var->xres_virtual)
  627. return -EINVAL;
  628. if ((var->yoffset + var->yres) > var->yres_virtual)
  629. return -EINVAL;
  630. /* Calculate the offset */
  631. if (var->bits_per_pixel == 0) {
  632. offset = (var->yoffset / 16) * (var->xres_virtual / 2) + (var->xoffset / 2);
  633. offset = offset >> 2;
  634. } else {
  635. offset = (var->yoffset * info->fix.line_length) +
  636. (var->xoffset * var->bits_per_pixel / 8);
  637. offset = offset >> 2;
  638. }
  639. /* Set the offset */
  640. svga_wcrt_multi(s3_start_address_regs, offset);
  641. return 0;
  642. }
  643. /* ------------------------------------------------------------------------- */
  644. /* Frame buffer operations */
  645. static struct fb_ops s3fb_ops = {
  646. .owner = THIS_MODULE,
  647. .fb_open = s3fb_open,
  648. .fb_release = s3fb_release,
  649. .fb_check_var = s3fb_check_var,
  650. .fb_set_par = s3fb_set_par,
  651. .fb_setcolreg = s3fb_setcolreg,
  652. .fb_blank = s3fb_blank,
  653. .fb_pan_display = s3fb_pan_display,
  654. .fb_fillrect = s3fb_fillrect,
  655. .fb_copyarea = cfb_copyarea,
  656. .fb_imageblit = s3fb_imageblit,
  657. };
  658. /* ------------------------------------------------------------------------- */
  659. static int __devinit s3_identification(int chip)
  660. {
  661. if (chip == CHIP_XXX_TRIO) {
  662. u8 cr30 = vga_rcrt(NULL, 0x30);
  663. u8 cr2e = vga_rcrt(NULL, 0x2e);
  664. u8 cr2f = vga_rcrt(NULL, 0x2f);
  665. if ((cr30 == 0xE0) || (cr30 == 0xE1)) {
  666. if (cr2e == 0x10)
  667. return CHIP_732_TRIO32;
  668. if (cr2e == 0x11) {
  669. if (! (cr2f & 0x40))
  670. return CHIP_764_TRIO64;
  671. else
  672. return CHIP_765_TRIO64VP;
  673. }
  674. }
  675. }
  676. if (chip == CHIP_XXX_TRIO64V2_DXGX) {
  677. u8 cr6f = vga_rcrt(NULL, 0x6f);
  678. if (! (cr6f & 0x01))
  679. return CHIP_775_TRIO64V2_DX;
  680. else
  681. return CHIP_785_TRIO64V2_GX;
  682. }
  683. if (chip == CHIP_XXX_VIRGE_DXGX) {
  684. u8 cr6f = vga_rcrt(NULL, 0x6f);
  685. if (! (cr6f & 0x01))
  686. return CHIP_375_VIRGE_DX;
  687. else
  688. return CHIP_385_VIRGE_GX;
  689. }
  690. return CHIP_UNKNOWN;
  691. }
  692. /* PCI probe */
  693. static int __devinit s3_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
  694. {
  695. struct fb_info *info;
  696. struct s3fb_info *par;
  697. int rc;
  698. u8 regval, cr38, cr39;
  699. /* Ignore secondary VGA device because there is no VGA arbitration */
  700. if (! svga_primary_device(dev)) {
  701. dev_info(&(dev->dev), "ignoring secondary device\n");
  702. return -ENODEV;
  703. }
  704. /* Allocate and fill driver data structure */
  705. info = framebuffer_alloc(sizeof(struct s3fb_info), NULL);
  706. if (!info) {
  707. dev_err(&(dev->dev), "cannot allocate memory\n");
  708. return -ENOMEM;
  709. }
  710. par = info->par;
  711. mutex_init(&par->open_lock);
  712. info->flags = FBINFO_PARTIAL_PAN_OK | FBINFO_HWACCEL_YPAN;
  713. info->fbops = &s3fb_ops;
  714. /* Prepare PCI device */
  715. rc = pci_enable_device(dev);
  716. if (rc < 0) {
  717. dev_err(&(dev->dev), "cannot enable PCI device\n");
  718. goto err_enable_device;
  719. }
  720. rc = pci_request_regions(dev, "s3fb");
  721. if (rc < 0) {
  722. dev_err(&(dev->dev), "cannot reserve framebuffer region\n");
  723. goto err_request_regions;
  724. }
  725. info->fix.smem_start = pci_resource_start(dev, 0);
  726. info->fix.smem_len = pci_resource_len(dev, 0);
  727. /* Map physical IO memory address into kernel space */
  728. info->screen_base = pci_iomap(dev, 0, 0);
  729. if (! info->screen_base) {
  730. rc = -ENOMEM;
  731. dev_err(&(dev->dev), "iomap for framebuffer failed\n");
  732. goto err_iomap;
  733. }
  734. /* Unlock regs */
  735. cr38 = vga_rcrt(NULL, 0x38);
  736. cr39 = vga_rcrt(NULL, 0x39);
  737. vga_wseq(NULL, 0x08, 0x06);
  738. vga_wcrt(NULL, 0x38, 0x48);
  739. vga_wcrt(NULL, 0x39, 0xA5);
  740. /* Find how many physical memory there is on card */
  741. /* 0x36 register is accessible even if other registers are locked */
  742. regval = vga_rcrt(NULL, 0x36);
  743. info->screen_size = s3_memsizes[regval >> 5] << 10;
  744. info->fix.smem_len = info->screen_size;
  745. par->chip = id->driver_data & CHIP_MASK;
  746. par->rev = vga_rcrt(NULL, 0x2f);
  747. if (par->chip & CHIP_UNDECIDED_FLAG)
  748. par->chip = s3_identification(par->chip);
  749. /* Find MCLK frequency */
  750. regval = vga_rseq(NULL, 0x10);
  751. par->mclk_freq = ((vga_rseq(NULL, 0x11) + 2) * 14318) / ((regval & 0x1F) + 2);
  752. par->mclk_freq = par->mclk_freq >> (regval >> 5);
  753. /* Restore locks */
  754. vga_wcrt(NULL, 0x38, cr38);
  755. vga_wcrt(NULL, 0x39, cr39);
  756. strcpy(info->fix.id, s3_names [par->chip]);
  757. info->fix.mmio_start = 0;
  758. info->fix.mmio_len = 0;
  759. info->fix.type = FB_TYPE_PACKED_PIXELS;
  760. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  761. info->fix.ypanstep = 0;
  762. info->fix.accel = FB_ACCEL_NONE;
  763. info->pseudo_palette = (void*) (par->pseudo_palette);
  764. /* Prepare startup mode */
  765. rc = fb_find_mode(&(info->var), info, mode, NULL, 0, NULL, 8);
  766. if (! ((rc == 1) || (rc == 2))) {
  767. rc = -EINVAL;
  768. dev_err(&(dev->dev), "mode %s not found\n", mode);
  769. goto err_find_mode;
  770. }
  771. rc = fb_alloc_cmap(&info->cmap, 256, 0);
  772. if (rc < 0) {
  773. dev_err(&(dev->dev), "cannot allocate colormap\n");
  774. goto err_alloc_cmap;
  775. }
  776. rc = register_framebuffer(info);
  777. if (rc < 0) {
  778. dev_err(&(dev->dev), "cannot register framebuffer\n");
  779. goto err_reg_fb;
  780. }
  781. printk(KERN_INFO "fb%d: %s on %s, %d MB RAM, %d MHz MCLK\n", info->node, info->fix.id,
  782. pci_name(dev), info->fix.smem_len >> 20, (par->mclk_freq + 500) / 1000);
  783. if (par->chip == CHIP_UNKNOWN)
  784. printk(KERN_INFO "fb%d: unknown chip, CR2D=%x, CR2E=%x, CRT2F=%x, CRT30=%x\n",
  785. info->node, vga_rcrt(NULL, 0x2d), vga_rcrt(NULL, 0x2e),
  786. vga_rcrt(NULL, 0x2f), vga_rcrt(NULL, 0x30));
  787. /* Record a reference to the driver data */
  788. pci_set_drvdata(dev, info);
  789. #ifdef CONFIG_MTRR
  790. if (mtrr) {
  791. par->mtrr_reg = -1;
  792. par->mtrr_reg = mtrr_add(info->fix.smem_start, info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
  793. }
  794. #endif
  795. return 0;
  796. /* Error handling */
  797. err_reg_fb:
  798. fb_dealloc_cmap(&info->cmap);
  799. err_alloc_cmap:
  800. err_find_mode:
  801. pci_iounmap(dev, info->screen_base);
  802. err_iomap:
  803. pci_release_regions(dev);
  804. err_request_regions:
  805. /* pci_disable_device(dev); */
  806. err_enable_device:
  807. framebuffer_release(info);
  808. return rc;
  809. }
  810. /* PCI remove */
  811. static void __devexit s3_pci_remove(struct pci_dev *dev)
  812. {
  813. struct fb_info *info = pci_get_drvdata(dev);
  814. if (info) {
  815. #ifdef CONFIG_MTRR
  816. struct s3fb_info *par = info->par;
  817. if (par->mtrr_reg >= 0) {
  818. mtrr_del(par->mtrr_reg, 0, 0);
  819. par->mtrr_reg = -1;
  820. }
  821. #endif
  822. unregister_framebuffer(info);
  823. fb_dealloc_cmap(&info->cmap);
  824. pci_iounmap(dev, info->screen_base);
  825. pci_release_regions(dev);
  826. /* pci_disable_device(dev); */
  827. pci_set_drvdata(dev, NULL);
  828. framebuffer_release(info);
  829. }
  830. }
  831. /* PCI suspend */
  832. static int s3_pci_suspend(struct pci_dev* dev, pm_message_t state)
  833. {
  834. struct fb_info *info = pci_get_drvdata(dev);
  835. struct s3fb_info *par = info->par;
  836. dev_info(&(dev->dev), "suspend\n");
  837. acquire_console_sem();
  838. mutex_lock(&(par->open_lock));
  839. if ((state.event == PM_EVENT_FREEZE) || (par->ref_count == 0)) {
  840. mutex_unlock(&(par->open_lock));
  841. release_console_sem();
  842. return 0;
  843. }
  844. fb_set_suspend(info, 1);
  845. pci_save_state(dev);
  846. pci_disable_device(dev);
  847. pci_set_power_state(dev, pci_choose_state(dev, state));
  848. mutex_unlock(&(par->open_lock));
  849. release_console_sem();
  850. return 0;
  851. }
  852. /* PCI resume */
  853. static int s3_pci_resume(struct pci_dev* dev)
  854. {
  855. struct fb_info *info = pci_get_drvdata(dev);
  856. struct s3fb_info *par = info->par;
  857. dev_info(&(dev->dev), "resume\n");
  858. acquire_console_sem();
  859. mutex_lock(&(par->open_lock));
  860. if (par->ref_count == 0) {
  861. mutex_unlock(&(par->open_lock));
  862. release_console_sem();
  863. return 0;
  864. }
  865. pci_set_power_state(dev, PCI_D0);
  866. pci_restore_state(dev);
  867. pci_enable_device(dev);
  868. pci_set_master(dev);
  869. s3fb_set_par(info);
  870. fb_set_suspend(info, 0);
  871. mutex_unlock(&(par->open_lock));
  872. release_console_sem();
  873. return 0;
  874. }
  875. /* List of boards that we are trying to support */
  876. static struct pci_device_id s3_devices[] __devinitdata = {
  877. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8810), .driver_data = CHIP_XXX_TRIO},
  878. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8811), .driver_data = CHIP_XXX_TRIO},
  879. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8812), .driver_data = CHIP_M65_AURORA64VP},
  880. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8814), .driver_data = CHIP_767_TRIO64UVP},
  881. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8901), .driver_data = CHIP_XXX_TRIO64V2_DXGX},
  882. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8902), .driver_data = CHIP_551_PLATO_PX},
  883. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x5631), .driver_data = CHIP_325_VIRGE},
  884. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x883D), .driver_data = CHIP_988_VIRGE_VX},
  885. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A01), .driver_data = CHIP_XXX_VIRGE_DXGX},
  886. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A10), .driver_data = CHIP_356_VIRGE_GX2},
  887. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A11), .driver_data = CHIP_357_VIRGE_GX2P},
  888. {PCI_DEVICE(PCI_VENDOR_ID_S3, 0x8A12), .driver_data = CHIP_359_VIRGE_GX2P},
  889. {0, 0, 0, 0, 0, 0, 0}
  890. };
  891. MODULE_DEVICE_TABLE(pci, s3_devices);
  892. static struct pci_driver s3fb_pci_driver = {
  893. .name = "s3fb",
  894. .id_table = s3_devices,
  895. .probe = s3_pci_probe,
  896. .remove = __devexit_p(s3_pci_remove),
  897. .suspend = s3_pci_suspend,
  898. .resume = s3_pci_resume,
  899. };
  900. /* Parse user speficied options */
  901. #ifndef MODULE
  902. static int __init s3fb_setup(char *options)
  903. {
  904. char *opt;
  905. if (!options || !*options)
  906. return 0;
  907. while ((opt = strsep(&options, ",")) != NULL) {
  908. if (!*opt)
  909. continue;
  910. #ifdef CONFIG_MTRR
  911. else if (!strncmp(opt, "mtrr:", 5))
  912. mtrr = simple_strtoul(opt + 5, NULL, 0);
  913. #endif
  914. else if (!strncmp(opt, "fasttext:", 9))
  915. fasttext = simple_strtoul(opt + 9, NULL, 0);
  916. else
  917. mode = opt;
  918. }
  919. return 0;
  920. }
  921. #endif
  922. /* Cleanup */
  923. static void __exit s3fb_cleanup(void)
  924. {
  925. pr_debug("s3fb: cleaning up\n");
  926. pci_unregister_driver(&s3fb_pci_driver);
  927. }
  928. /* Driver Initialisation */
  929. static int __init s3fb_init(void)
  930. {
  931. #ifndef MODULE
  932. char *option = NULL;
  933. if (fb_get_options("s3fb", &option))
  934. return -ENODEV;
  935. s3fb_setup(option);
  936. #endif
  937. pr_debug("s3fb: initializing\n");
  938. return pci_register_driver(&s3fb_pci_driver);
  939. }
  940. /* ------------------------------------------------------------------------- */
  941. /* Modularization */
  942. module_init(s3fb_init);
  943. module_exit(s3fb_cleanup);