s3c_ltv350qv.c 57 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/errno.h>
  4. #include <linux/string.h>
  5. #include <linux/mm.h>
  6. #include <linux/tty.h>
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <linux/fb.h>
  10. #include <linux/init.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/string.h>
  13. #include <linux/ioctl.h>
  14. #include <linux/clk.h>
  15. #include <asm/io.h>
  16. #include <asm/uaccess.h>
  17. #include <asm/mach/map.h>
  18. #include <asm/arch/regs-lcd.h>
  19. #include <asm/arch/regs-gpio.h>
  20. #include <asm/arch/regs-gpioj.h>
  21. #if defined(CONFIG_CPU_S3C2443)
  22. #include <asm/arch/regs-s3c2443-clock.h>
  23. #elif defined(CONFIG_CPU_S3C2450)
  24. #include <asm/arch/regs-s3c2450-clock.h>
  25. #elif defined(CONFIG_CPU_S3C6400)
  26. #include <asm/arch/regs-s3c6400-clock.h>
  27. #elif defined(CONFIG_CPU_S3C6410)
  28. #include <asm/arch/regs-s3c6410-clock.h>
  29. #endif
  30. #include "s3cfb.h"
  31. #define ON 1
  32. #define OFF 0
  33. #define DEFAULT_BACKLIGHT_LEVEL 2
  34. #define H_FP 3 /* front porch */
  35. #define H_SW 10 /* Hsync width */
  36. #define H_BP 5 /* Back porch */
  37. #define V_FP 3 /* front porch */
  38. #define V_SW 4 /* Vsync width */
  39. #define V_BP 5 /* Back porch */
  40. extern struct s3c_fb_info info[S3C_FB_NUM];
  41. s3c_win_info_t window_info;
  42. //------------------ Virtual Screen -----------------------
  43. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  44. vs_info_t vs_info;
  45. #define START_VIRTUAL_LCD 11
  46. #define STOP_VIRTUAL_LCD 10
  47. #define SET_VIRTUAL_LCD 12
  48. #define VS_MOVE_LEFT 15
  49. #define VS_MOVE_RIGHT 16
  50. #define VS_MOVE_UP 17
  51. #define VS_MOVE_DOWN 18
  52. #define MAX_DISPLAY_OFFSET 200
  53. #define DEF_DISPLAY_OFFSET 100
  54. int virtual_display_offset = DEF_DISPLAY_OFFSET;
  55. #endif
  56. //------------------ OSD (On Screen Display) -----------------------
  57. #define START_OSD 1
  58. #define STOP_OSD 0
  59. // QCIF OSD image
  60. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
  61. #define H_RESOLUTION_OSD 320 /* horizon pixel x resolition */
  62. #define V_RESOLUTION_OSD 240 /* line cnt y resolution */
  63. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  64. #define H_RESOLUTION_OSD 320 /* horizon pixel x resolition */
  65. #define V_RESOLUTION_OSD 240 /* line cnt y resolution */
  66. #endif
  67. #define ALPHA_UP 3
  68. #define ALPHA_DOWN 4
  69. #define MOVE_LEFT 5
  70. #define MOVE_RIGHT 6
  71. #define MOVE_UP 7
  72. #define MOVE_DOWN 8
  73. #define MAX_ALPHA_LEVEL 0x0f
  74. int osd_alpha_level = MAX_ALPHA_LEVEL;
  75. int osd_left_top_x = 0;
  76. int osd_left_top_y = 0;
  77. int osd_right_bottom_x = H_RESOLUTION_OSD-1;
  78. int osd_left_bottom_y = V_RESOLUTION_OSD -1;
  79. //------------------------------------------------------------------------
  80. #define H_RESOLUTION 320 /* horizon pixel x resolition */
  81. #define V_RESOLUTION 240 /* line cnt y resolution */
  82. #define H_RESOLUTION_VIRTUAL 800 /* horizon pixel x resolition */
  83. #define V_RESOLUTION_VIRTUAL 600 /* line cnt y resolution */
  84. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  85. #define VFRAME_FREQ 75 /* frame rate freq */
  86. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  87. #define VFRAME_FREQ 60 /* frame rate freq */
  88. #endif
  89. #define PIXEL_CLOCK VFRAME_FREQ * LCD_PIXEL_CLOCK /* vclk = frame * pixel_count */
  90. #define PIXEL_BPP8 8
  91. #define PIXEL_BPP16 16 /* RGB 5-6-5 format for SMDK EVAL BOARD */
  92. #define PIXEL_BPP24 24 /* RGB 8-8-8 format for SMDK EVAL BOARD */
  93. #define LCD_PIXEL_CLOCK (VFRAME_FREQ *(H_FP+H_SW+H_BP+H_RESOLUTION) * (V_FP+V_SW+V_BP+V_RESOLUTION))
  94. #define MAX_DISPLAY_BRIGHTNESS 9
  95. #define DEF_DISPLAY_BRIGHTNESS 4
  96. int display_brightness = DEF_DISPLAY_BRIGHTNESS;
  97. void set_brightness(int);
  98. struct s3c_fb_mach_info mach_info = {
  99. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  100. .vidcon0= S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_VCLKEN_ENABLE |S3C_VIDCON0_CLKSEL_F_HCLK,
  101. .vidcon1= S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT,
  102. .vidtcon0= S3C_VIDTCON0_VBPD(V_BP-1) | S3C_VIDTCON0_VFPD(V_FP-1) | S3C_VIDTCON0_VSPW(V_SW-1),
  103. .vidtcon1= S3C_VIDTCON1_HBPD(H_BP-1) | S3C_VIDTCON1_HFPD(H_FP-1 ) | S3C_VIDTCON1_HSPW(H_SW-1),
  104. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  105. .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE
  106. | S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P
  107. | S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK |
  108. S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE,
  109. .vidcon1 = S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT |S3C_VIDCON1_IVDEN_INVERT,
  110. .vidtcon0 = S3C_VIDTCON0_VBPDE(0) | S3C_VIDTCON0_VBPD(V_BP-1) | S3C_VIDTCON0_VFPD(V_FP-1) | S3C_VIDTCON0_VSPW(V_SW-1),
  111. .vidtcon1 = S3C_VIDTCON1_VFPDE(0) | S3C_VIDTCON1_HBPD(H_BP-1) | S3C_VIDTCON1_HFPD(H_FP-1) | S3C_VIDTCON1_HSPW(H_SW-1),
  112. #endif
  113. .vidtcon2= S3C_VIDTCON2_LINEVAL(V_RESOLUTION-1) | S3C_VIDTCON2_HOZVAL(H_RESOLUTION-1),
  114. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  115. .dithmode = ( S3C_DITHMODE_RDITHPOS_5BIT |S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT ) & S3C_DITHMODE_DITHERING_DISABLE,
  116. #endif
  117. #if defined (CONFIG_FB_BPP_8)
  118. .wincon0= S3C_WINCONx_BYTSWP_ENABLE |S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL, // 4word burst, 8bpp-palletized,
  119. .wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  120. //.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_A555 | S3C_WINCONx_BLD_PIX_PIXEL| S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  121. #elif defined (CONFIG_FB_BPP_16)
  122. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  123. .wincon0= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565, // 4word burst, 16bpp,
  124. .wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  125. //.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_A555 | S3C_WINCONx_BLD_PIX_PIXEL| S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  126. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  127. // .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  128. .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  129. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  130. S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  131. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  132. S3C_WINCONx_BUFAUTOEN_ENABLE |
  133. #endif
  134. S3C_WINCONx_ENWIN_F_DISABLE, // 4word burst, 16bpp,
  135. .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  136. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  137. S3C_WINCONx_BURSTLEN_16WORD |S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  138. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  139. S3C_WINCONx_BUFAUTOEN_ENABLE |
  140. #endif
  141. S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, // 4word burst, 16bpp,
  142. .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE |
  143. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  144. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  145. S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  146. .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  147. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD |
  148. S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  149. .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  150. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD |
  151. S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  152. #endif
  153. #elif defined (CONFIG_FB_BPP_24)
  154. .wincon0= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888, // 4word burst, 24bpp,
  155. .wincon1= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 24bpp for OSD
  156. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  157. .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  158. .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  159. .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  160. #endif
  161. #endif
  162. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  163. .vidosd0a= S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  164. .vidosd0b= S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION-1),
  165. .vidosd1a= S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  166. .vidosd1b= S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  167. .vidosd1c= S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  168. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  169. .vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  170. .vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION-1),
  171. .vidosd0c = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  172. .vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  173. .vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  174. .vidosd1c= S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  175. .vidosd1d = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  176. .vidosd2a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  177. .vidosd2b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  178. .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  179. .vidosd2d = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  180. .vidosd3a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  181. .vidosd3b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  182. .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  183. .vidosd4a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  184. .vidosd4b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  185. .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  186. #endif
  187. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
  188. .vidintcon= S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_ENABLE | S3C_VIDINTCON0_INTEN_ENABLE,
  189. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  190. // .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_BACK | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_DISABLE,
  191. .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_ENABLE,
  192. .vidintcon1 = 0,
  193. #endif
  194. .width= H_RESOLUTION,
  195. .height= V_RESOLUTION,
  196. .xres= H_RESOLUTION,
  197. .yres= V_RESOLUTION,
  198. .xoffset= 0,
  199. .yoffset= 0,
  200. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  201. .xres_virtual = H_RESOLUTION_VIRTUAL,
  202. .yres_virtual = V_RESOLUTION_VIRTUAL,
  203. #else
  204. .xres_virtual = H_RESOLUTION,
  205. .yres_virtual = V_RESOLUTION,
  206. #endif
  207. .osd_width= H_RESOLUTION_OSD,
  208. .osd_height= V_RESOLUTION_OSD,
  209. .osd_xres= H_RESOLUTION_OSD,
  210. .osd_yres= V_RESOLUTION_OSD,
  211. .osd_xres_virtual= H_RESOLUTION_OSD,
  212. .osd_yres_virtual= V_RESOLUTION_OSD,
  213. #if defined (CONFIG_FB_BPP_8)
  214. .bpp= PIXEL_BPP8,
  215. .bytes_per_pixel= 1,
  216. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  217. .wpalcon= W0PAL_24BIT,
  218. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  219. .wpalcon= W0PAL_16BIT,
  220. #endif
  221. #elif defined (CONFIG_FB_BPP_16)
  222. .bpp= PIXEL_BPP16,
  223. .bytes_per_pixel= 2,
  224. #elif defined (CONFIG_FB_BPP_24)
  225. .bpp= PIXEL_BPP24,
  226. .bytes_per_pixel= 4,
  227. #endif
  228. .pixclock= PIXEL_CLOCK,
  229. .hsync_len= H_SW,
  230. .vsync_len= V_SW,
  231. .left_margin= H_FP,
  232. .upper_margin= V_FP,
  233. .right_margin= H_BP,
  234. .lower_margin= V_BP,
  235. .sync= 0,
  236. .cmap_static= 1,
  237. };
  238. #if defined(CONFIG_S3C6400_PWM)
  239. void set_brightness(int val)
  240. {
  241. int channel = 1; // must use channel-1
  242. int usec = 0; // don't care value
  243. unsigned long tcnt=1000;
  244. unsigned long tcmp=0;
  245. if(val < 0) val=0;
  246. if(val > MAX_DISPLAY_BRIGHTNESS) val=MAX_DISPLAY_BRIGHTNESS;
  247. display_brightness = val;
  248. switch (val) {
  249. case 0:
  250. tcmp= 0;
  251. break;
  252. case 1:
  253. tcmp= 50;
  254. break;
  255. case 2:
  256. tcmp= 100;
  257. break;
  258. case 3:
  259. tcmp= 150;
  260. break;
  261. case 4:
  262. tcmp= 200;
  263. break;
  264. case 5:
  265. tcmp= 250;
  266. break;
  267. case 6:
  268. tcmp= 300;
  269. break;
  270. case 7:
  271. tcmp= 350;
  272. break;
  273. case 8:
  274. tcmp= 400;
  275. break;
  276. case 9:
  277. tcmp= 450;
  278. break;
  279. } // end of switch (level)
  280. s3c6400_timer_setup (channel, usec, tcnt, tcmp);
  281. }
  282. #endif
  283. #if defined(CONFIG_S3C2443_PWM)
  284. /*
  285. * Function for PWM Control of S3C2443
  286. */
  287. void set_brightness(int val)
  288. {
  289. int channel = 3; // must use channel-3
  290. int usec = 0; // don't care value
  291. unsigned long tcnt=1000;
  292. unsigned long tcmp=0;
  293. if(val < 0) val=0;
  294. if(val > MAX_DISPLAY_BRIGHTNESS) val=MAX_DISPLAY_BRIGHTNESS;
  295. display_brightness = val;
  296. switch (val) {
  297. case 0:
  298. tcmp= 0;
  299. break;
  300. case 1:
  301. tcmp= 50;
  302. break;
  303. case 2:
  304. tcmp= 100;
  305. break;
  306. case 3:
  307. tcmp= 150;
  308. break;
  309. case 4:
  310. tcmp= 200;
  311. break;
  312. case 5:
  313. tcmp= 250;
  314. break;
  315. case 6:
  316. tcmp= 300;
  317. break;
  318. case 7:
  319. tcmp= 350;
  320. break;
  321. case 8:
  322. tcmp= 400;
  323. break;
  324. case 9:
  325. tcmp= 450;
  326. break;
  327. }
  328. s3c2443_timer_setup (channel, usec, tcnt, tcmp);
  329. }
  330. #endif
  331. #if defined(CONFIG_S3C2450_PWM)
  332. /*
  333. * Function for PWM Control of S3C2450
  334. */
  335. void set_brightness(int val)
  336. {
  337. int channel = 1; // must use channel-3
  338. int usec = 0; // don't care value
  339. unsigned long tcnt=1000;
  340. unsigned long tcmp=0;
  341. if(val < 0) val=0;
  342. if(val > MAX_DISPLAY_BRIGHTNESS) val=MAX_DISPLAY_BRIGHTNESS;
  343. display_brightness = val;
  344. switch (val) {
  345. case 0:
  346. tcmp= 0;
  347. break;
  348. case 1:
  349. tcmp= 50;
  350. break;
  351. case 2:
  352. tcmp= 100;
  353. break;
  354. case 3:
  355. tcmp= 150;
  356. break;
  357. case 4:
  358. tcmp= 200;
  359. break;
  360. case 5:
  361. tcmp= 250;
  362. break;
  363. case 6:
  364. tcmp= 300;
  365. break;
  366. case 7:
  367. tcmp= 350;
  368. break;
  369. case 8:
  370. tcmp= 400;
  371. break;
  372. case 9:
  373. tcmp= 450;
  374. break;
  375. }
  376. s3c2450_timer_setup (channel, usec, tcnt, tcmp);
  377. }
  378. #endif
  379. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  380. void set_virtual_display_offset(int val)
  381. {
  382. if(val < 1)
  383. val = 1;
  384. if(val > MAX_DISPLAY_OFFSET)
  385. val = MAX_DISPLAY_OFFSET;
  386. virtual_display_offset = val;
  387. }
  388. int set_vs_info(vs_info_t vs_info_from_app )
  389. {
  390. /* check invalid value */
  391. if(vs_info_from_app.width != H_RESOLUTION || vs_info_from_app.height != V_RESOLUTION ){
  392. return 1;
  393. }
  394. if(!(vs_info_from_app.bpp==8 ||vs_info_from_app.bpp==16 ||vs_info_from_app.bpp==24 || vs_info_from_app.bpp==32) ){
  395. return 1;
  396. }
  397. if(vs_info_from_app.offset<0){
  398. return 1;
  399. }
  400. if(vs_info_from_app.v_width != H_RESOLUTION_VIRTUAL || vs_info_from_app.v_height != V_RESOLUTION_VIRTUAL){
  401. return 1;
  402. }
  403. /* save virtual screen information */
  404. vs_info = vs_info_from_app;
  405. set_virtual_display_offset(vs_info.offset);
  406. return 0;
  407. }
  408. int set_virtual_display_register(int vs_cmd)
  409. {
  410. int PageWidth, Offset;
  411. int ShiftValue;
  412. PageWidth = mach_info.xres * mach_info.bytes_per_pixel;
  413. Offset = (mach_info.xres_virtual - mach_info.xres) * mach_info.bytes_per_pixel;
  414. switch(vs_cmd){
  415. case SET_VIRTUAL_LCD:
  416. /* size of buffer */
  417. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  418. mach_info.vidw00add2b0 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  419. mach_info.vidw00add2b1 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  420. __raw_writel(mach_info.vidw00add2b0, S3C_VIDW00ADD2B0);
  421. __raw_writel(mach_info.vidw00add2b1, S3C_VIDW00ADD2B1);
  422. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  423. mach_info.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  424. __raw_writel(mach_info.vidw00add2, S3C_VIDW00ADD2);
  425. #endif
  426. break;
  427. case VS_MOVE_LEFT:
  428. if(mach_info.xoffset < virtual_display_offset){
  429. ShiftValue = mach_info.xoffset;
  430. }
  431. else ShiftValue = virtual_display_offset;
  432. mach_info.xoffset -= ShiftValue;
  433. /* For buffer start address */
  434. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 - ShiftValue*mach_info.bytes_per_pixel;
  435. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 - ShiftValue*mach_info.bytes_per_pixel;
  436. break;
  437. case VS_MOVE_RIGHT:
  438. if((vs_info.v_width - (mach_info.xoffset + vs_info.width) )< (virtual_display_offset)){
  439. ShiftValue = vs_info.v_width - (mach_info.xoffset + vs_info.width);
  440. }
  441. else ShiftValue = virtual_display_offset;
  442. mach_info.xoffset += ShiftValue;
  443. /* For buffer start address */
  444. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 + ShiftValue*mach_info.bytes_per_pixel;
  445. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 + ShiftValue*mach_info.bytes_per_pixel;
  446. break;
  447. case VS_MOVE_UP:
  448. if(mach_info.yoffset < virtual_display_offset){
  449. ShiftValue = mach_info.yoffset;
  450. }
  451. else ShiftValue = virtual_display_offset;
  452. mach_info.yoffset -= ShiftValue;
  453. /* For buffer start address */
  454. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 - ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  455. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 - ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  456. break;
  457. case VS_MOVE_DOWN:
  458. if((vs_info.v_height - (mach_info.yoffset + vs_info.height) )< (virtual_display_offset)){
  459. ShiftValue = vs_info.v_height - (mach_info.yoffset + vs_info.height);
  460. }
  461. else ShiftValue = virtual_display_offset;
  462. mach_info.yoffset += ShiftValue;
  463. /* For buffer start address */
  464. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 + ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  465. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 + ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  466. break;
  467. default:
  468. return -EINVAL;
  469. }
  470. /* End address */
  471. mach_info.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(mach_info.vidw00add0b0 + (PageWidth + Offset) * (mach_info.yres));
  472. mach_info.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(mach_info.vidw00add0b1 + (PageWidth + Offset) * (mach_info.yres));
  473. __raw_writel(mach_info.vidw00add0b0, S3C_VIDW00ADD0B0);
  474. __raw_writel(mach_info.vidw00add0b1, S3C_VIDW00ADD0B1);
  475. __raw_writel(mach_info.vidw00add1b0, S3C_VIDW00ADD1B0);
  476. __raw_writel(mach_info.vidw00add1b1, S3C_VIDW00ADD1B1);
  477. return 0;
  478. }
  479. #endif
  480. /*
  481. * As LCD-Brightness is best related to Display and hence FrameBuffer,
  482. * so we put the brightness control in /dev/fb.
  483. */
  484. #define GET_DISPLAY_BRIGHTNESS _IOR('F', 1, u_int) /* get brightness */
  485. #define SET_DISPLAY_BRIGHTNESS _IOW('F', 2, u_int) /* set brightness */
  486. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  487. #define SET_VS_START _IO('F', 103)
  488. #define SET_VS_STOP _IO('F', 104)
  489. #define SET_VS_INFO _IOW('F', 105, vs_info_t)
  490. #define SET_VS_MOVE _IOW('F', 106, u_int)
  491. #endif
  492. #define SET_OSD_START _IO('F', 201)
  493. #define SET_OSD_STOP _IO('F', 202)
  494. #define SET_OSD_ALPHA_UP _IO('F', 203)
  495. #define SET_OSD_ALPHA_DOWN _IO('F', 204)
  496. #define SET_OSD_MOVE_LEFT _IO('F', 205)
  497. #define SET_OSD_MOVE_RIGHT _IO('F', 206)
  498. #define SET_OSD_MOVE_UP _IO('F', 207)
  499. #define SET_OSD_MOVE_DOWN _IO('F', 208)
  500. #define SET_OSD_INFO _IOW('F', 209, s3c_win_info_t)
  501. #define SET_OSD_BRIGHT _IOW('F', 210, int)
  502. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  503. #define GET_FB_NUM _IOWR('F', 301, u_int)
  504. #endif
  505. int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  506. {
  507. struct s3c_fb_info *fbi = container_of(info, struct s3c_fb_info, fb);
  508. struct fb_var_screeninfo *var= &fbi->fb.var;
  509. int brightness;
  510. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  511. u_int f_num_val;
  512. #endif
  513. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  514. vs_info_t vs_info_from_app;
  515. #endif
  516. s3c_win_info_t win_info_from_app;
  517. // int bright_level_from_app;
  518. switch(cmd){
  519. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  520. case SET_VS_START:
  521. mach_info.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE);
  522. __raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE|S3C_WINCONx_BUFAUTOEN_ENABLE, S3C_WINCON0); /* Double buffer auto enable bit */
  523. fbi->fb.var.xoffset = mach_info.xoffset;
  524. fbi->fb.var.yoffset = mach_info.yoffset;
  525. break;
  526. case SET_VS_STOP:
  527. break;
  528. case SET_VS_INFO:
  529. if(copy_from_user
  530. (&vs_info_from_app, (vs_info_t *) arg,
  531. sizeof(vs_info_t)))
  532. return -EFAULT;
  533. if(set_vs_info(vs_info_from_app)){
  534. // invalid value is input. so return Error
  535. return -EINVAL;
  536. }
  537. set_virtual_display_register(SET_VIRTUAL_LCD);
  538. fbi->fb.var.xoffset = mach_info.xoffset;
  539. fbi->fb.var.yoffset = mach_info.yoffset;
  540. break;
  541. case SET_VS_MOVE:
  542. set_virtual_display_register(arg);
  543. fbi->fb.var.xoffset = mach_info.xoffset;
  544. fbi->fb.var.yoffset = mach_info.yoffset;
  545. break;
  546. #endif
  547. case SET_OSD_INFO :
  548. if(copy_from_user
  549. (&win_info_from_app, (s3c_win_info_t *) arg,
  550. sizeof(s3c_win_info_t)))
  551. return -EFAULT;
  552. s3c_fb_init_win(fbi, win_info_from_app.Bpp,
  553. win_info_from_app.LeftTop_x, win_info_from_app.LeftTop_y, win_info_from_app.Width, win_info_from_app.Height, OFF);
  554. break;
  555. case SET_OSD_START :
  556. #if 0
  557. if(fbi->win_id==1){
  558. win_info_from_app.LeftTop_x=0;
  559. win_info_from_app.LeftTop_y=0;
  560. }
  561. else if(fbi->win_id==2){
  562. win_info_from_app.LeftTop_x=160;
  563. win_info_from_app.LeftTop_y=0;
  564. }
  565. else if(fbi->win_id==3){
  566. win_info_from_app.LeftTop_x=0;
  567. win_info_from_app.LeftTop_y=120;
  568. }
  569. else if(fbi->win_id==4){
  570. win_info_from_app.LeftTop_x=160;
  571. win_info_from_app.LeftTop_y=120;
  572. }
  573. win_info_from_app.Bpp=16;
  574. win_info_from_app.Width=160;
  575. win_info_from_app.Height=120;
  576. s3c_fb_init_win(fbi, win_info_from_app.Bpp,
  577. win_info_from_app.LeftTop_x, win_info_from_app.LeftTop_y, win_info_from_app.Width, win_info_from_app.Height, OFF);
  578. #endif
  579. #if 0
  580. win_info_from_app.LeftTop_x=0;
  581. win_info_from_app.LeftTop_y=0;
  582. win_info_from_app.Bpp=16;
  583. win_info_from_app.Width=100;
  584. win_info_from_app.Height=30;
  585. s3c_fb_init_win(fbi, win_info_from_app.Bpp,
  586. win_info_from_app.LeftTop_x, win_info_from_app.LeftTop_y, win_info_from_app.Width, win_info_from_app.Height, OFF);
  587. #endif
  588. s3c_fb_win_onoff(fbi, ON); // on
  589. break;
  590. case SET_OSD_STOP:
  591. s3c_fb_win_onoff(fbi, OFF); // off
  592. break;
  593. case SET_OSD_ALPHA_UP:
  594. if(osd_alpha_level < MAX_ALPHA_LEVEL) osd_alpha_level ++;
  595. s3c_fb_set_alpha_level(fbi);
  596. break;
  597. case SET_OSD_ALPHA_DOWN:
  598. if(osd_alpha_level > 0) osd_alpha_level --;
  599. s3c_fb_set_alpha_level(fbi);
  600. break;
  601. case SET_OSD_MOVE_LEFT:
  602. if(var->xoffset>0) var->xoffset--;
  603. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  604. break;
  605. case SET_OSD_MOVE_RIGHT:
  606. if(var->xoffset < (H_RESOLUTION - var->xres)) var->xoffset ++;
  607. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  608. break;
  609. case SET_OSD_MOVE_UP:
  610. if(var->yoffset>0) var->yoffset--;
  611. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  612. break;
  613. case SET_OSD_MOVE_DOWN:
  614. if(var->yoffset < (V_RESOLUTION - var->yres)) var->yoffset ++;
  615. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  616. break;
  617. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  618. case GET_FB_NUM:
  619. copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int));
  620. copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int));
  621. break;
  622. #endif
  623. case SET_DISPLAY_BRIGHTNESS:
  624. if(copy_from_user(&brightness, (int *) arg, sizeof(int)))
  625. return -EFAULT;
  626. #if defined(CONFIG_S3C6400_PWM)
  627. set_brightness(brightness);
  628. #endif
  629. #if defined(CONFIG_S3C2443_PWM)
  630. set_brightness(brightness);
  631. #endif
  632. #if defined(CONFIG_S3C2450_PWM)
  633. set_brightness(brightness);
  634. #endif
  635. case GET_DISPLAY_BRIGHTNESS:
  636. if(copy_to_user((void *)arg, (const void *) &display_brightness, sizeof(int)))
  637. return -EFAULT;
  638. break;
  639. default:
  640. return -EINVAL;
  641. }
  642. return 0;
  643. }
  644. /*
  645. * s3c_fb_map_video_memory():
  646. * Allocates the DRAM memory for the frame buffer. This buffer is
  647. * remapped into a non-cached, non-buffered, memory region to
  648. * allow palette and pixel writes to occur without flushing the
  649. * cache. Once this area is remapped, all virtual memory
  650. * access to the video memory should occur at the new region.
  651. */
  652. int __init s3c_fb_map_video_memory(struct s3c_fb_info *fbi)
  653. {
  654. dprintk("map_video_memory(fbi=%p)\n", fbi);
  655. fbi->map_size_f1 = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  656. fbi->map_cpu_f1 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f1,
  657. &fbi->map_dma_f1, GFP_KERNEL);
  658. fbi->map_size_f1 = fbi->fb.fix.smem_len;
  659. if (fbi->map_cpu_f1) {
  660. /* prevent initial garbage on screen */
  661. printk("Window[%d]- FB1 : map_video_memory: clear %p:%08x\n",
  662. fbi->win_id, fbi->map_cpu_f1, fbi->map_size_f1);
  663. memset(fbi->map_cpu_f1, 0xf0, fbi->map_size_f1);
  664. fbi->screen_dma_f1 = fbi->map_dma_f1;
  665. fbi->fb.screen_base = fbi->map_cpu_f1;
  666. fbi->fb.fix.smem_start = fbi->screen_dma_f1;
  667. printk(" FB1 : map_video_memory: dma=%08x cpu=%p size=%08x\n",
  668. fbi->map_dma_f1, fbi->map_cpu_f1, fbi->fb.fix.smem_len);
  669. }
  670. if( !fbi->map_cpu_f1)
  671. return -ENOMEM;
  672. #if !defined(CONFIG_FB_VIRTUAL_SCREEN) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  673. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  674. if(fbi->win_id<1){ // WIN0 support double-buffer
  675. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  676. if(fbi->win_id<2){ // WIN0, WIN1 support double-buffer
  677. #endif
  678. fbi->map_size_f2 = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  679. fbi->map_cpu_f2 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f2,
  680. &fbi->map_dma_f2, GFP_KERNEL);
  681. fbi->map_size_f2 = fbi->fb.fix.smem_len;
  682. if (fbi->map_cpu_f2) {
  683. /* prevent initial garbage on screen */
  684. printk("Window[%d] - FB2 : map_video_memory: clear %p:%08x\n",
  685. fbi->win_id, fbi->map_cpu_f2, fbi->map_size_f2);
  686. memset(fbi->map_cpu_f2, 0xf0, fbi->map_size_f2);
  687. fbi->screen_dma_f2 = fbi->map_dma_f2;
  688. printk(" FB2 : map_video_memory: dma=%08x cpu=%p size=%08x\n",
  689. fbi->map_dma_f2, fbi->map_cpu_f2, fbi->fb.fix.smem_len);
  690. }
  691. if( !fbi->map_cpu_f2)
  692. return -ENOMEM;
  693. }
  694. #endif
  695. return 0;
  696. }
  697. void s3c_fb_unmap_video_memory(struct s3c_fb_info *fbi)
  698. {
  699. dma_free_writecombine(fbi->dev, fbi->map_size_f1, fbi->map_cpu_f1, fbi->map_dma_f1);
  700. #if !defined(CONFIG_FB_VIRTUAL_SCREEN) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  701. dma_free_writecombine(fbi->dev, fbi->map_size_f2, fbi->map_cpu_f2, fbi->map_dma_f2);
  702. #endif
  703. }
  704. /*
  705. * s3c_fb_init_registers - Initialise all LCD-related registers
  706. */
  707. int s3c_fb_init_registers(struct s3c_fb_info *fbi)
  708. {
  709. u_long flags = 0;
  710. u_long PageWidth = 0, Offset = 0;
  711. int win_num = fbi->win_id;
  712. struct clk *lcd_clock;
  713. struct fb_var_screeninfo *var= &fbi->fb.var;
  714. unsigned long VideoPhysicalTemp_f1 = fbi->screen_dma_f1;
  715. unsigned long VideoPhysicalTemp_f2 = fbi->screen_dma_f2;
  716. /* Initialise LCD with values from hare */
  717. local_irq_save(flags);
  718. if(win_num==0){
  719. mach_info.vidcon0 = mach_info.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
  720. __raw_writel(mach_info.vidcon0, S3C_VIDCON0);
  721. lcd_clock = clk_get(NULL, "lcd");
  722. mach_info.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int)((clk_get_rate(lcd_clock) / LCD_PIXEL_CLOCK) - 1));
  723. }
  724. /* For buffer start address */
  725. __raw_writel(VideoPhysicalTemp_f1, S3C_VIDW00ADD0B0+(0x08*win_num));
  726. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  727. if(win_num==0) __raw_writel(VideoPhysicalTemp_f2, S3C_VIDW00ADD0B1);
  728. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  729. if(win_num<2) __raw_writel(VideoPhysicalTemp_f2, S3C_VIDW00ADD0B1+(0x08*win_num));
  730. #endif
  731. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  732. if(win_num==0){
  733. mach_info.vidw00add0b0=VideoPhysicalTemp_f1;
  734. mach_info.vidw00add0b1=VideoPhysicalTemp_f2;
  735. }
  736. #endif
  737. PageWidth = var->xres * mach_info.bytes_per_pixel;
  738. Offset = (var->xres_virtual - var->xres) * mach_info.bytes_per_pixel;
  739. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  740. if(win_num==0) Offset=0;
  741. #endif
  742. /* End address */
  743. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f1 + (PageWidth + Offset) * (var->yres)),
  744. S3C_VIDW00ADD1B0+(0x08*win_num));
  745. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  746. if(win_num==0)
  747. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres)),
  748. S3C_VIDW00ADD1B1);
  749. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  750. if(win_num<2)
  751. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres)),
  752. S3C_VIDW00ADD1B1+(0x08*win_num));
  753. #endif
  754. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  755. if(win_num==0){
  756. mach_info.vidw00add1b0=S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f1 + (PageWidth + Offset) * (var->yres));
  757. mach_info.vidw00add1b1=S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres));
  758. }
  759. #endif
  760. /* size of buffer */
  761. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  762. __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2B0+(0x08*win_num));
  763. if(win_num==0) __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2B1);
  764. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  765. __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2+(0x04*win_num));
  766. #endif
  767. switch(win_num){
  768. case 0:
  769. __raw_writel(mach_info.wincon0, S3C_WINCON0);
  770. __raw_writel(mach_info.vidcon0, S3C_VIDCON0);
  771. __raw_writel(mach_info.vidcon1, S3C_VIDCON1);
  772. __raw_writel(mach_info.vidtcon0, S3C_VIDTCON0);
  773. __raw_writel(mach_info.vidtcon1, S3C_VIDTCON1);
  774. __raw_writel(mach_info.vidtcon2, S3C_VIDTCON2);
  775. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
  776. __raw_writel(mach_info.vidintcon, S3C_VIDINTCON);
  777. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  778. __raw_writel(mach_info.dithmode, S3C_DITHMODE);
  779. __raw_writel(mach_info.vidintcon0, S3C_VIDINTCON0);
  780. __raw_writel(mach_info.vidintcon1, S3C_VIDINTCON1);
  781. #endif
  782. __raw_writel(mach_info.vidosd0a, S3C_VIDOSD0A);
  783. __raw_writel(mach_info.vidosd0b, S3C_VIDOSD0B);
  784. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  785. __raw_writel(mach_info.vidosd0c, S3C_VIDOSD0C);
  786. #endif
  787. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  788. s3c_fb_win_onoff(fbi, ON);
  789. break;
  790. case 1:
  791. __raw_writel(mach_info.wincon1, S3C_WINCON1);
  792. __raw_writel(mach_info.vidosd1a, S3C_VIDOSD1A);
  793. __raw_writel(mach_info.vidosd1b, S3C_VIDOSD1B);
  794. __raw_writel(mach_info.vidosd1c, S3C_VIDOSD1C);
  795. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  796. __raw_writel(mach_info.vidosd1d, S3C_VIDOSD1D);
  797. #endif
  798. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  799. s3c_fb_win_onoff(fbi, OFF);
  800. break;
  801. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  802. case 2:
  803. __raw_writel(mach_info.wincon2, S3C_WINCON2);
  804. __raw_writel(mach_info.vidosd2a, S3C_VIDOSD2A);
  805. __raw_writel(mach_info.vidosd2b, S3C_VIDOSD2B);
  806. __raw_writel(mach_info.vidosd2c, S3C_VIDOSD2C);
  807. __raw_writel(mach_info.vidosd2d, S3C_VIDOSD2D);
  808. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  809. s3c_fb_win_onoff(fbi, OFF);
  810. break;
  811. case 3:
  812. __raw_writel(mach_info.wincon3, S3C_WINCON3);
  813. __raw_writel(mach_info.vidosd3a, S3C_VIDOSD3A);
  814. __raw_writel(mach_info.vidosd3b, S3C_VIDOSD3B);
  815. __raw_writel(mach_info.vidosd3c, S3C_VIDOSD3C);
  816. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  817. s3c_fb_win_onoff(fbi, OFF);
  818. break;
  819. case 4:
  820. __raw_writel(mach_info.wincon4, S3C_WINCON4);
  821. __raw_writel(mach_info.vidosd4a, S3C_VIDOSD4A);
  822. __raw_writel(mach_info.vidosd4b, S3C_VIDOSD4B);
  823. __raw_writel(mach_info.vidosd4c, S3C_VIDOSD4C);
  824. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  825. s3c_fb_win_onoff(fbi, OFF);
  826. break;
  827. #endif
  828. }
  829. local_irq_restore(flags);
  830. return 0;
  831. }
  832. /* s3c_fb_set_lcdaddr
  833. *
  834. * initialise lcd controller address pointers
  835. */
  836. void s3c_fb_set_lcdaddr(struct s3c_fb_info *fbi)
  837. {
  838. #if 0
  839. struct fb_var_screeninfo *var = &fbi->fb.var;
  840. unsigned long VideoPhysicalTemp_f1 = fbi->screen_dma_f1;
  841. unsigned long VideoPhysicalTemp_f2 = fbi->screen_dma_f2;
  842. /* For buffer start address */
  843. mach_info.vidw00add0b0 = VideoPhysicalTemp_f1;
  844. mach_info.vidw00add0b1 = VideoPhysicalTemp_f2;
  845. __raw_writel(mach_info.vidw00add0b0, S3C_VIDW00ADD0B0);
  846. __raw_writel(mach_info.vidw00add0b1, S3C_VIDW00ADD0B1);
  847. #endif
  848. }
  849. void s3c_fb_set_fb_change(int req_fb) {
  850. info[req_fb].fb_change_ready = 0;
  851. #if (defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  852. // Software-based trigger
  853. __raw_writel((1<<0), S3C_CPUTRIGCON2);
  854. #elif (defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  855. // Software-based trigger
  856. __raw_writel((3<<0), S3C_TRIGCON);
  857. #endif // #if defined(CONFIG_CPU_S3C2443)
  858. }
  859. /* s3c_fb_activate_var
  860. *
  861. * activate (set) the controller from the given framebuffer
  862. * information
  863. */
  864. void s3c_fb_activate_var(struct s3c_fb_info *fbi,
  865. struct fb_var_screeninfo *var)
  866. {
  867. dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
  868. switch (var->bits_per_pixel) {
  869. case 8:
  870. mach_info.wincon0= S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL; // 4word burst, 8bpp-palletized,
  871. mach_info.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  872. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  873. mach_info.wincon2= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  874. mach_info.wincon3= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  875. mach_info.wincon4= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  876. #endif
  877. mach_info.bpp= PIXEL_BPP8;
  878. mach_info.bytes_per_pixel= 1;
  879. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
  880. mach_info.wpalcon= S3C_WPALCON_W0PAL_24BIT;
  881. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  882. mach_info.wpalcon= S3C_WPALCON_W0PAL_16BIT;
  883. #endif
  884. break;
  885. case 16:
  886. mach_info.wincon0= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565; // 4word burst, 16bpp,
  887. mach_info.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  888. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  889. mach_info.wincon2= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  890. mach_info.wincon3= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  891. mach_info.wincon4= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  892. #endif
  893. mach_info.bpp= PIXEL_BPP16;
  894. mach_info.bytes_per_pixel= 2;
  895. break;
  896. case 24:
  897. mach_info.wincon0= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888; // 4word burst, 24bpp,,
  898. mach_info.wincon1= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  899. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  900. mach_info.wincon2= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  901. mach_info.wincon3= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  902. mach_info.wincon4= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  903. #endif
  904. mach_info.bpp= PIXEL_BPP24;
  905. mach_info.bytes_per_pixel= 4;
  906. break;
  907. case 32:
  908. mach_info.bytes_per_pixel= 4;
  909. break;
  910. }
  911. /* write new registers */
  912. __raw_writel(mach_info.wincon0, S3C_WINCON0);
  913. __raw_writel(mach_info.wincon1, S3C_WINCON1);
  914. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  915. __raw_writel(mach_info.wincon2, S3C_WINCON2);
  916. __raw_writel(mach_info.wincon3, S3C_WINCON3);
  917. __raw_writel(mach_info.wincon4, S3C_WINCON4);
  918. #endif
  919. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  920. /* set lcd address pointers */
  921. #if 0
  922. s3c_fb_set_lcdaddr(fbi);
  923. #endif
  924. __raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE|S3C_WINCONx_BUFAUTOEN_ENABLE, S3C_WINCON0); /* Double buffer auto enable bit */
  925. __raw_writel(mach_info.vidcon0|S3C_VIDCON0_ENVID_ENABLE|S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
  926. }
  927. int s3c_fb_init_win (struct s3c_fb_info *fbi, int Bpp, int LeftTop_x, int LeftTop_y, int Width, int Height, int OnOff)
  928. {
  929. s3c_fb_win_onoff(fbi, OFF); // off
  930. s3c_fb_set_bpp(fbi, Bpp);
  931. s3c_fb_set_position_win(fbi, LeftTop_x, LeftTop_y, Width, Height);
  932. s3c_fb_set_size_win(fbi, Width, Height);
  933. s3c_fb_set_memory_size_win(fbi);
  934. // s3c_fb_set_alpha_mode(fbi, int Alpha_mode, int Alpha_level)
  935. s3c_fb_win_onoff(fbi, OnOff); // off
  936. return 0;
  937. }
  938. int s3c_fb_win_onoff(struct s3c_fb_info *fbi, int On)
  939. {
  940. int win_num = fbi->win_id;
  941. if(On)
  942. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_ENWIN_F_ENABLE,
  943. S3C_WINCON0+(0x04*win_num)); // ON
  944. else
  945. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))&~(S3C_WINCONx_ENWIN_F_ENABLE),
  946. S3C_WINCON0+(0x04*win_num)); // OFF
  947. return 0;
  948. }
  949. int s3c_fb_set_alpha_level(struct s3c_fb_info *fbi)
  950. {
  951. unsigned long alpha_val;
  952. int win_num = fbi->win_id;
  953. if(win_num==0){
  954. printk("WIN0 do not support alpha blending.\n");
  955. return -1;
  956. }
  957. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  958. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
  959. __raw_writel(alpha_val, S3C_VIDOSD1C);
  960. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  961. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  962. #endif
  963. return 0;
  964. }
  965. int s3c_fb_set_alpha_mode(struct s3c_fb_info *fbi, int Alpha_mode, int Alpha_level)
  966. {
  967. unsigned long alpha_val;
  968. int win_num = fbi->win_id;
  969. if(win_num==0){
  970. printk("WIN0 do not support alpha blending.\n");
  971. return -1;
  972. }
  973. switch(Alpha_mode){
  974. case 0: // Plane Blending
  975. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BLD_PIX_PLANE,
  976. S3C_WINCON0+(0x04*win_num));
  977. break;
  978. case 1: // Pixel Blending
  979. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BLD_PIX_PIXEL,
  980. S3C_WINCON0+(0x04*win_num));
  981. break;
  982. }
  983. osd_alpha_level = Alpha_level;
  984. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  985. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  986. __raw_writel(alpha_val, S3C_VIDOSD1C);
  987. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  988. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  989. #endif
  990. return 0;
  991. }
  992. #if 0
  993. int s3c_fb_alpha_onoff(struct s3c_fb_info *fbi)
  994. {
  995. }
  996. int s3c_fb_set_color_key(struct s3c_fb_info *fbi)
  997. {
  998. }
  999. int s3c_fb_color_key_onoff(struct s3c_fb_info *fbi, int On)
  1000. {
  1001. int win_num = fbi->win_id;
  1002. if(On)
  1003. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_ENWIN_F_ENABLE,
  1004. S3C_WINCON0+(0x04*win_num)); // ON
  1005. else
  1006. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))&~(S3C_WINCONx_ENWIN_F_ENABLE),
  1007. S3C_WINCON0+(0x04*win_num)); // OFF
  1008. }
  1009. int s3c_fb_set_color_key_level(struct s3c_fb_info *fbi)
  1010. {
  1011. unsigned long alpha_val;
  1012. int win_num = fbi->win_id;
  1013. if(win_num==0){
  1014. printk("WIN0 do not support color-key.\n");
  1015. return -1;
  1016. }
  1017. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  1018. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  1019. return 0;
  1020. }
  1021. #endif
  1022. int s3c_fb_set_position_win(struct s3c_fb_info *fbi, int LeftTop_x, int LeftTop_y, int Width, int Height)
  1023. {
  1024. struct fb_var_screeninfo *var= &fbi->fb.var;
  1025. int win_num = fbi->win_id;
  1026. if(win_num==0){
  1027. printk("WIN0 do not support window position control.\n");
  1028. return -1;
  1029. }
  1030. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  1031. __raw_writel(S3C_VIDOSDxA_OSD_LTX_F(LeftTop_x) | S3C_VIDOSDxA_OSD_LTY_F(LeftTop_y),
  1032. S3C_VIDOSD0A+(0x0c*win_num));
  1033. __raw_writel(S3C_VIDOSDxB_OSD_RBX_F(Width-1 + LeftTop_x) | S3C_VIDOSDxB_OSD_RBY_F(Height-1 + LeftTop_y),
  1034. S3C_VIDOSD0B+(0x0c*win_num));
  1035. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1036. __raw_writel(S3C_VIDOSDxA_OSD_LTX_F(LeftTop_x) | S3C_VIDOSDxA_OSD_LTY_F(LeftTop_y),
  1037. S3C_VIDOSD0A+(0x10*win_num));
  1038. __raw_writel(S3C_VIDOSDxB_OSD_RBX_F(Width-1 + LeftTop_x) | S3C_VIDOSDxB_OSD_RBY_F(Height-1 + LeftTop_y),
  1039. S3C_VIDOSD0B+(0x10*win_num));
  1040. #endif
  1041. var->xoffset=LeftTop_x;
  1042. var->yoffset=LeftTop_y;
  1043. return 0;
  1044. }
  1045. int s3c_fb_set_size_win(struct s3c_fb_info *fbi, int Width, int Height)
  1046. {
  1047. struct fb_var_screeninfo *var= &fbi->fb.var;
  1048. int win_num = fbi->win_id;
  1049. if(win_num==0){
  1050. printk("WIN0 do not support window size control.\n");
  1051. return -1;
  1052. }
  1053. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1054. if(win_num==1)
  1055. __raw_writel(S3C_VIDOSD0C_OSDSIZE(Width*Height),S3C_VIDOSD1D);
  1056. else if(win_num==2)
  1057. __raw_writel(S3C_VIDOSD0C_OSDSIZE(Width*Height),S3C_VIDOSD2D);
  1058. #endif
  1059. var->xres = Width;
  1060. var->yres = Height;
  1061. var->xres_virtual = Width;
  1062. var->yres_virtual= Height;
  1063. return 0;
  1064. }
  1065. int s3c_fb_set_bpp(struct s3c_fb_info *fbi, int Bpp)
  1066. {
  1067. struct fb_var_screeninfo *var= &fbi->fb.var;
  1068. int win_num = fbi->win_id;
  1069. switch(Bpp){
  1070. case 1:
  1071. // What should I do???
  1072. break;
  1073. case 2:
  1074. // What should I do???
  1075. break;
  1076. case 4:
  1077. // What should I do???
  1078. break;
  1079. case 8:
  1080. // What should I do???
  1081. break;
  1082. case 16:
  1083. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BPPMODE_F_16BPP_565,
  1084. S3C_WINCON0+(0x04*win_num));
  1085. var->bits_per_pixel=16;
  1086. break;
  1087. case 24:
  1088. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BPPMODE_F_24BPP_888,
  1089. S3C_WINCON0+(0x04*win_num));
  1090. var->bits_per_pixel=24;
  1091. break;
  1092. case 32:
  1093. var->bits_per_pixel=32;
  1094. break;
  1095. }
  1096. return 0;
  1097. }
  1098. int s3c_fb_set_memory_size_win(struct s3c_fb_info *fbi)
  1099. {
  1100. struct fb_var_screeninfo *var= &fbi->fb.var;
  1101. int win_num = fbi->win_id;
  1102. unsigned long Offset = 0;
  1103. unsigned long PageWidth = 0;
  1104. unsigned long FrameBufferSize = 0;
  1105. PageWidth = var->xres * mach_info.bytes_per_pixel;
  1106. Offset = (var->xres_virtual - var->xres) * mach_info.bytes_per_pixel;
  1107. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  1108. if(win_num==0) Offset=0;
  1109. #endif
  1110. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long)__raw_readl(S3C_VIDW00ADD0B0+(0x08*win_num)) + (PageWidth + Offset) * (var->yres)),
  1111. S3C_VIDW00ADD1B0+(0x08*win_num));
  1112. if(win_num==1)
  1113. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long)__raw_readl(S3C_VIDW00ADD0B1+(0x08*win_num)) + (PageWidth + Offset) * (var->yres)),
  1114. S3C_VIDW00ADD1B1+(0x08*win_num));
  1115. /* size of frame buffer */
  1116. FrameBufferSize = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  1117. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  1118. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2B0+(0x08*win_num));
  1119. if(win_num==0)
  1120. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2B1);
  1121. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1122. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2+(0x04*win_num));
  1123. #endif
  1124. return 0;
  1125. }
  1126. int s3c_fb_set_out_path(struct s3c_fb_info *fbi, int Path)
  1127. {
  1128. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1129. switch(Path){
  1130. case 0: // RGB I/F
  1131. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P, S3C_VIDCON0);
  1132. break;
  1133. case 1: // TV Encoder T/F
  1134. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TV, S3C_VIDCON0);
  1135. break;
  1136. case 2: // Indirect I80 I/F-0
  1137. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_I80IF0, S3C_VIDCON0);
  1138. break;
  1139. case 3: // Indirect I80 I/F-1
  1140. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_I80IF1, S3C_VIDCON0);
  1141. break;
  1142. case 4: // TV Encoder & RGB I/F
  1143. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNRGBIF, S3C_VIDCON0);
  1144. break;
  1145. case 6: // TV Encoder & Indirect I80 I/F-0
  1146. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNI80IF0, S3C_VIDCON0);
  1147. break;
  1148. case 7: // TV Encoder & Indirect I80 I/F-1
  1149. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNI80IF1, S3C_VIDCON0);
  1150. break;
  1151. default: // RGB I/F
  1152. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P, S3C_VIDCON0);
  1153. break;
  1154. }
  1155. #endif
  1156. return 0;
  1157. }
  1158. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1159. #define LCD_TV 1
  1160. // LCD display controller configuration functions
  1161. void s3c_fb_set_output_path(int out)
  1162. {
  1163. u32 tmp;
  1164. //printk("s3c_fb_set_output_path() called.\n");
  1165. tmp = __raw_readl(S3C_VIDCON0);
  1166. // if output mode is LCD mode, Scan mode always should be progressive mode
  1167. if(out == LCD_TV) {
  1168. tmp &=~(1<<29);
  1169. }
  1170. tmp &=~(0x7<<26);
  1171. tmp |= (out<<26);
  1172. __raw_writel(tmp, S3C_VIDCON0);
  1173. }
  1174. void s3c_fb_set_clkval(u32 clkval)
  1175. {
  1176. u32 tmp;
  1177. //printk("s3c_fb_set_clkval() called.\n");
  1178. tmp = __raw_readl(S3C_VIDCON0);
  1179. tmp &=~(0x1<<4);
  1180. tmp &=~(0xff<<6);
  1181. __raw_writel(tmp | (clkval<<6) | (1<<4), S3C_VIDCON0);
  1182. }
  1183. void s3c_fb_enable_rgbport(u32 on_off)
  1184. {
  1185. //printk("s3c_fb_enable_rgbport() called.\n");
  1186. if(on_off) //enable
  1187. __raw_writel(0x380, S3C_VIDCON2);
  1188. else //disable
  1189. __raw_writel(0x0, S3C_VIDCON2);
  1190. }
  1191. EXPORT_SYMBOL(s3c_fb_set_output_path);
  1192. EXPORT_SYMBOL(s3c_fb_set_clkval);
  1193. EXPORT_SYMBOL(s3c_fb_enable_rgbport);
  1194. #endif
  1195. void SetLcdPort(void)
  1196. {
  1197. unsigned long gpdat;
  1198. unsigned long gpcon;
  1199. unsigned long hclkcon; //, sclkcon;
  1200. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  1201. //Enable clock to LCD
  1202. hclkcon = __raw_readl(S3C2443_HCLKCON);
  1203. hclkcon |= S3C2443_HCLKCON_LCDC;
  1204. __raw_writel(hclkcon, S3C2443_HCLKCON);
  1205. // To select TFT LCD type
  1206. gpdat = __raw_readl(S3C2410_MISCCR);
  1207. gpdat |= (1<<28);
  1208. __raw_writel(gpdat, S3C2410_MISCCR);
  1209. __raw_writel(0xaaaaaaaa, S3C2410_GPCCON); // CTRL, VD[7:0]
  1210. __raw_writel(0xaaaaaaaa, S3C2410_GPDCON); // VD[23:8]
  1211. /* LCD Backlight Enable control */
  1212. gpcon = __raw_readl(S3C2410_GPBCON);
  1213. gpcon = (gpcon & ~(3<<6)) | (1<<6); // Backlight(GPB3) Enable control
  1214. __raw_writel(gpcon, S3C2410_GPBCON);
  1215. /* LCD Backlight ON */
  1216. gpdat = __raw_readl(S3C2410_GPBDAT);
  1217. gpdat |= (1<<3);
  1218. __raw_writel(gpdat, S3C2410_GPBDAT);
  1219. // LCD _nRESET control
  1220. gpcon = __raw_readl(S3C2410_GPBCON);
  1221. gpcon = (gpcon & ~(3<<2)) |(1<<2);
  1222. __raw_writel(gpcon, S3C2410_GPBCON);
  1223. gpdat = __raw_readl(S3C2410_GPBDAT);
  1224. gpdat |= (1<<1);
  1225. __raw_writel(gpdat, S3C2410_GPBDAT);
  1226. // LCD module reset
  1227. gpdat = __raw_readl(S3C2410_GPBDAT);
  1228. gpdat |= (1<<2);
  1229. __raw_writel(gpdat, S3C2410_GPBDAT);
  1230. gpdat = __raw_readl(S3C2410_GPBDAT);
  1231. gpdat &= ~(1<<2); // goes to LOW
  1232. __raw_writel(gpdat, S3C2410_GPBDAT);
  1233. mdelay(10);
  1234. gpdat = __raw_readl(S3C2410_GPBDAT);
  1235. gpdat |= (1<<2); // goes to HIGH
  1236. __raw_writel(gpdat, S3C2410_GPBDAT);
  1237. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1238. //Must be '0' for Normal-path instead of By-pass
  1239. // (*(volatile unsigned *)0x7410800c)=0;
  1240. __raw_writel(0x0, S3C_HOSTIFB_MIFPCON); // VD[15:0]
  1241. //Enable clock to LCD
  1242. hclkcon = __raw_readl(S3C_HCLK_GATE);
  1243. hclkcon |= S3C_CLKCON_HCLK_LCD;
  1244. __raw_writel(hclkcon, S3C_HCLK_GATE);
  1245. // To select TFT LCD type (RGB I/F)
  1246. gpdat = __raw_readl(S3C_SPCON);
  1247. gpdat &= ~0x3;
  1248. gpdat |= (1<<0);
  1249. __raw_writel(gpdat, S3C_SPCON);
  1250. __raw_writel(0xaaaaaaaa, S3C_GPICON); // VD[15:0]
  1251. __raw_writel(0xaaaaaaaa, S3C_GPJCON); // VD[23:16], Ctrl
  1252. #if 0
  1253. /* Dummy code : remove to LCD pwm control (ryu)*/
  1254. /* LCD Backlight Enable control */
  1255. gpcon = __raw_readl(S3C_GPFCON);
  1256. gpcon = (gpcon & ~(3<<30)) | (1<<30); // Backlight(GPF15) Enable control
  1257. __raw_writel(gpcon, S3C_GPFCON);
  1258. /* LCD Backlight ON */
  1259. gpdat = __raw_readl(S3C_GPFDAT);
  1260. gpdat |= (1<<15);
  1261. __raw_writel(gpdat, S3C_GPFDAT);
  1262. #endif
  1263. // LCD _nRESET control
  1264. gpcon = __raw_readl(S3C_GPNCON);
  1265. gpcon = (gpcon & ~(3<<10)) |(1<<10);
  1266. __raw_writel(gpcon, S3C_GPNCON);
  1267. gpdat = __raw_readl(S3C_GPNDAT);
  1268. gpdat |= (1<<5);
  1269. __raw_writel(gpdat, S3C_GPNDAT);
  1270. mdelay(100);
  1271. gpdat = __raw_readl(S3C_GPNDAT);
  1272. gpdat |= (0<<5);
  1273. __raw_writel(gpdat, S3C_GPNDAT);
  1274. mdelay(10);
  1275. gpdat = __raw_readl(S3C_GPNDAT);
  1276. gpdat |= (1<<5);
  1277. __raw_writel(gpdat, S3C_GPNDAT);
  1278. mdelay(10);
  1279. #endif
  1280. }
  1281. #if defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2450)
  1282. #define LCD_DEN (1<<14)
  1283. #define LCD_DSERI (1<<11)
  1284. #define LCD_DCLK (1<<10)
  1285. #define LCD_DEN_BIT 14
  1286. #define LCD_DSERI_BIT 11
  1287. #define LCD_DCLK_BIT 10
  1288. #define LCD_nRESET 1
  1289. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1290. #define LCD_DEN (1<<7)
  1291. #define LCD_DSERI (1<<6)
  1292. #define LCD_DCLK (1<<5)
  1293. #define LCD_DEN_BIT 7
  1294. #define LCD_DSERI_BIT 6
  1295. #define LCD_DCLK_BIT 5
  1296. #define LCD_nRESET 5
  1297. #endif
  1298. #define LCD_RESET (0)
  1299. #define LCD_RESET_Lo (0)
  1300. #define LCD_RESET_Hi (1)
  1301. #if defined(CONFIG_CPU_S3C2443)||defined(CONFIG_CPU_S3C2450)
  1302. #define LCD_DEN_Lo { gpdat = __raw_readl(S3C2443_GPLDAT); \
  1303. gpdat &= ~LCD_DEN; \
  1304. __raw_writel(gpdat, S3C2443_GPLDAT); \
  1305. }
  1306. #define LCD_DEN_Hi { gpdat = __raw_readl(S3C2443_GPLDAT); \
  1307. gpdat |= LCD_DEN; \
  1308. __raw_writel(gpdat, S3C2443_GPLDAT); \
  1309. }
  1310. #define LCD_DCLK_Lo { gpdat = __raw_readl(S3C2443_GPLDAT); \
  1311. gpdat &= ~LCD_DCLK; \
  1312. __raw_writel(gpdat, S3C2443_GPLDAT); \
  1313. }
  1314. #define LCD_DCLK_Hi { gpdat = __raw_readl(S3C2443_GPLDAT); \
  1315. gpdat |= LCD_DCLK; \
  1316. __raw_writel(gpdat, S3C2443_GPLDAT); \
  1317. }
  1318. #define LCD_DSERI_Lo { gpdat = __raw_readl(S3C2443_GPLDAT); \
  1319. gpdat &= ~LCD_DSERI; \
  1320. __raw_writel(gpdat, S3C2443_GPLDAT); \
  1321. }
  1322. #define LCD_DSERI_Hi { gpdat = __raw_readl(S3C2443_GPLDAT); \
  1323. gpdat |= LCD_DSERI; \
  1324. __raw_writel(gpdat, S3C2443_GPLDAT); \
  1325. }
  1326. #define SET_LCD_DATA { gpdat= __raw_readl(S3C2443_GPLCON); \
  1327. gpdat &= ~(((3<<(LCD_DEN_BIT*2))) | ((3<<(LCD_DCLK_BIT*2))) | ((3<<(LCD_DSERI_BIT*2)))); \
  1328. gpdat |= (((1<<(LCD_DEN_BIT*2))) | ((1<<(LCD_DCLK_BIT*2))) | ((1<<(LCD_DSERI_BIT*2)))); \
  1329. __raw_writel(gpdat, S3C2443_GPLCON); \
  1330. gpfpu = __raw_readl(S3C2443_GPLUDP); \
  1331. gpfpu |= ~(((3<<(LCD_DEN_BIT*2))) | ((3<<(LCD_DCLK_BIT*2))) | ((3<<(LCD_DSERI_BIT*2)))); \
  1332. gpfpu |= (((2<<(LCD_DEN_BIT*2))) | ((2<<(LCD_DCLK_BIT*2))) | ((2<<(LCD_DSERI_BIT*2)))); \
  1333. __raw_writel(gpfpu, S3C2443_GPLUDP); \
  1334. }
  1335. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1336. #define LCD_DEN_Lo { gpdat = __raw_readl(S3C_GPCDAT); \
  1337. gpdat &= ~LCD_DEN; \
  1338. __raw_writel(gpdat, S3C_GPCDAT); \
  1339. }
  1340. #define LCD_DEN_Hi { gpdat = __raw_readl(S3C_GPCDAT); \
  1341. gpdat |= LCD_DEN; \
  1342. __raw_writel(gpdat, S3C_GPCDAT); \
  1343. }
  1344. #define LCD_DCLK_Lo { gpdat = __raw_readl(S3C_GPCDAT); \
  1345. gpdat &= ~LCD_DCLK; \
  1346. __raw_writel(gpdat, S3C_GPCDAT); \
  1347. }
  1348. #define LCD_DCLK_Hi { gpdat = __raw_readl(S3C_GPCDAT); \
  1349. gpdat |= LCD_DCLK; \
  1350. __raw_writel(gpdat, S3C_GPCDAT); \
  1351. }
  1352. #define LCD_DSERI_Lo { gpdat = __raw_readl(S3C_GPCDAT); \
  1353. gpdat &= ~LCD_DSERI; \
  1354. __raw_writel(gpdat, S3C_GPCDAT); \
  1355. }
  1356. #define LCD_DSERI_Hi { gpdat = __raw_readl(S3C_GPCDAT); \
  1357. gpdat |= LCD_DSERI; \
  1358. __raw_writel(gpdat, S3C_GPCDAT); \
  1359. }
  1360. #define SET_LCD_DATA { gpdat= __raw_readl(S3C_GPCCON); \
  1361. gpdat &= ~(((0xF<<(LCD_DEN_BIT*4))) | ((0xF<<(LCD_DCLK_BIT*4))) | ((0xF<<(LCD_DSERI_BIT*4)))); \
  1362. gpdat |= (((1<<(LCD_DEN_BIT*4))) | ((1<<(LCD_DCLK_BIT*4))) | ((1<<(LCD_DSERI_BIT*4)))); \
  1363. __raw_writel(gpdat, S3C_GPCCON); \
  1364. gpfpu = __raw_readl(S3C_GPCPU); \
  1365. gpfpu &= ~(((3<<(LCD_DEN_BIT*2))) | ((3<<(LCD_DCLK_BIT*2))) | ((3<<(LCD_DSERI_BIT*2)))); \
  1366. __raw_writel(gpfpu, S3C_GPCPU); \
  1367. }
  1368. #endif
  1369. void delayLoop(int count)
  1370. {
  1371. int j;
  1372. for(j = 0; j < count; j++) ;
  1373. }
  1374. void Write_LDI_LTV350(int address, int data)
  1375. {
  1376. unsigned char dev_id_code=0x1D;
  1377. int j;
  1378. unsigned char DELAY=50;
  1379. unsigned long gpdat;
  1380. LCD_DEN_Hi; // EN = High CS high
  1381. LCD_DCLK_Hi; // SCL High
  1382. LCD_DSERI_Hi; // Data Low
  1383. delayLoop(DELAY);
  1384. LCD_DEN_Lo; // EN = Low CS Low
  1385. delayLoop(DELAY);
  1386. for (j = 5; j >= 0; j--)
  1387. {
  1388. LCD_DCLK_Lo; // SCL Low
  1389. if ((dev_id_code >> j) & 0x0001) // DATA HIGH or LOW
  1390. {
  1391. LCD_DSERI_Hi;
  1392. }
  1393. else
  1394. {
  1395. LCD_DSERI_Lo;
  1396. }
  1397. delayLoop(DELAY);
  1398. LCD_DCLK_Hi; // CLOCK = High
  1399. delayLoop(DELAY);
  1400. }
  1401. // RS = "0" : index data
  1402. LCD_DCLK_Lo; // CLOCK = Low
  1403. LCD_DSERI_Lo;
  1404. delayLoop(DELAY);
  1405. LCD_DCLK_Hi; // CLOCK = High
  1406. delayLoop(DELAY);
  1407. // Write
  1408. LCD_DCLK_Lo; // CLOCK = Low
  1409. LCD_DSERI_Lo;
  1410. delayLoop(DELAY);
  1411. LCD_DCLK_Hi; // CLOCK = High
  1412. delayLoop(DELAY);
  1413. for (j = 15; j >= 0; j--)
  1414. {
  1415. LCD_DCLK_Lo; // SCL Low
  1416. if ((address >> j) & 0x0001) // DATA HIGH or LOW
  1417. {
  1418. LCD_DSERI_Hi;
  1419. }
  1420. else
  1421. {
  1422. LCD_DSERI_Lo;
  1423. }
  1424. delayLoop(DELAY);
  1425. LCD_DCLK_Hi; // CLOCK = High
  1426. delayLoop(DELAY);
  1427. }
  1428. LCD_DSERI_Hi;
  1429. delayLoop(DELAY);
  1430. LCD_DEN_Hi; // EN = High
  1431. delayLoop(DELAY*10);
  1432. LCD_DEN_Lo; // EN = Low CS Low
  1433. delayLoop(DELAY);
  1434. for (j = 5; j >= 0; j--)
  1435. {
  1436. LCD_DCLK_Lo; // SCL Low
  1437. if ((dev_id_code >> j) & 0x0001) // DATA HIGH or LOW
  1438. {
  1439. LCD_DSERI_Hi;
  1440. }
  1441. else
  1442. {
  1443. LCD_DSERI_Lo;
  1444. }
  1445. delayLoop(DELAY);
  1446. LCD_DCLK_Hi; // CLOCK = High
  1447. delayLoop(DELAY);
  1448. }
  1449. // RS = "1" instruction data
  1450. LCD_DCLK_Lo; // CLOCK = Low
  1451. LCD_DSERI_Hi;
  1452. delayLoop(DELAY);
  1453. LCD_DCLK_Hi; // CLOCK = High
  1454. delayLoop(DELAY);
  1455. // Write
  1456. LCD_DCLK_Lo; // CLOCK = Low
  1457. LCD_DSERI_Lo;
  1458. delayLoop(DELAY);
  1459. LCD_DCLK_Hi; // CLOCK = High
  1460. delayLoop(DELAY);
  1461. for (j = 15; j >= 0; j--)
  1462. {
  1463. LCD_DCLK_Lo; // SCL Low
  1464. if ((data >> j) & 0x0001) // DATA HIGH or LOW
  1465. {
  1466. LCD_DSERI_Hi;
  1467. }
  1468. else
  1469. {
  1470. LCD_DSERI_Lo;
  1471. }
  1472. delayLoop(DELAY);
  1473. LCD_DCLK_Hi; // CLOCK = High
  1474. delayLoop(DELAY);
  1475. }
  1476. LCD_DEN_Hi; // EN = High
  1477. delayLoop(DELAY);
  1478. }
  1479. void Init_LDI(void)
  1480. {
  1481. unsigned long gpdat, gpfpu; // lcdcon1,
  1482. printk(KERN_INFO "LCD TYPE :: S3C_LTV350QV LCD will be initialized\n");
  1483. SetLcdPort();
  1484. SET_LCD_DATA;
  1485. mdelay(5);
  1486. LCD_DEN_Hi;
  1487. LCD_DCLK_Hi;
  1488. LCD_DSERI_Hi;
  1489. Write_LDI_LTV350(0x01,0x001d);
  1490. Write_LDI_LTV350(0x02,0x0000);
  1491. Write_LDI_LTV350(0x03,0x0000);
  1492. Write_LDI_LTV350(0x04,0x0000);
  1493. Write_LDI_LTV350(0x05,0x50a3);
  1494. Write_LDI_LTV350(0x06,0x0000);
  1495. Write_LDI_LTV350(0x07,0x0000);
  1496. Write_LDI_LTV350(0x08,0x0000);
  1497. Write_LDI_LTV350(0x09,0x0000);
  1498. Write_LDI_LTV350(0x0a,0x0000);
  1499. Write_LDI_LTV350(0x10,0x0000);
  1500. Write_LDI_LTV350(0x11,0x0000);
  1501. Write_LDI_LTV350(0x12,0x0000);
  1502. Write_LDI_LTV350(0x13,0x0000);
  1503. Write_LDI_LTV350(0x14,0x0000);
  1504. Write_LDI_LTV350(0x15,0x0000);
  1505. Write_LDI_LTV350(0x16,0x0000);
  1506. Write_LDI_LTV350(0x17,0x0000);
  1507. Write_LDI_LTV350(0x18,0x0000);
  1508. Write_LDI_LTV350(0x19,0x0000);
  1509. mdelay(10);
  1510. Write_LDI_LTV350(0x09,0x4055);
  1511. Write_LDI_LTV350(0x0a,0x0000);
  1512. mdelay(10);
  1513. Write_LDI_LTV350(0x0a,0x2000);
  1514. mdelay(50);
  1515. Write_LDI_LTV350(0x01,0x409d);
  1516. Write_LDI_LTV350(0x02,0x0204);
  1517. Write_LDI_LTV350(0x03,0x2100);
  1518. Write_LDI_LTV350(0x04,0x1000);
  1519. Write_LDI_LTV350(0x05,0x5003);
  1520. Write_LDI_LTV350(0x06,0x0009); //vbp
  1521. Write_LDI_LTV350(0x07,0x000f); //hbp
  1522. Write_LDI_LTV350(0x08,0x0800);
  1523. Write_LDI_LTV350(0x10,0x0000);
  1524. Write_LDI_LTV350(0x11,0x0000);
  1525. Write_LDI_LTV350(0x12,0x000f);
  1526. Write_LDI_LTV350(0x13,0x1f00);
  1527. Write_LDI_LTV350(0x14,0x0000);
  1528. Write_LDI_LTV350(0x15,0x0000);
  1529. Write_LDI_LTV350(0x16,0x0000);
  1530. Write_LDI_LTV350(0x17,0x0000);
  1531. Write_LDI_LTV350(0x18,0x0000);
  1532. Write_LDI_LTV350(0x19,0x0000);
  1533. mdelay(50);
  1534. // __raw_writel(mach_info.vidcon0 |ENVID|ENVID_F, S3C_VIDCON0);
  1535. Write_LDI_LTV350(0x09,0x4a55);
  1536. Write_LDI_LTV350(0x0a,0x2000);
  1537. }