s3c_lms480qc.c 54 KB

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  1. #include <linux/module.h>
  2. #include <linux/kernel.h>
  3. #include <linux/errno.h>
  4. #include <linux/string.h>
  5. #include <linux/mm.h>
  6. #include <linux/tty.h>
  7. #include <linux/slab.h>
  8. #include <linux/delay.h>
  9. #include <linux/fb.h>
  10. #include <linux/init.h>
  11. #include <linux/dma-mapping.h>
  12. #include <linux/string.h>
  13. #include <linux/ioctl.h>
  14. #include <linux/clk.h>
  15. #include <asm/io.h>
  16. #include <asm/uaccess.h>
  17. #include <asm/mach/map.h>
  18. #include <asm/arch/regs-lcd.h>
  19. #include <asm/arch/regs-gpio.h>
  20. #include <asm/arch/regs-spi.h>
  21. #include <asm/arch/regs-s3c6400-clock.h>
  22. #include "s3cfb.h"
  23. #define ON 1
  24. #define OFF 0
  25. #define DEFAULT_BACKLIGHT_LEVEL 2
  26. #define H_FP 10 /* front porch */
  27. #define H_SW 1 /* Hsync width */
  28. #define H_BP 104 /* Back porch */
  29. #define V_FP 8 /* front porch */
  30. #define V_SW 1 /* Vsync width */
  31. #define V_BP 21 /* Back porch */
  32. extern struct s3c_fb_info info[S3C_FB_NUM];
  33. s3c_win_info_t window_info;
  34. /* for spi controller */
  35. static void __iomem *spi_base;
  36. //------------------ Virtual Screen -----------------------
  37. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  38. vs_info_t vs_info;
  39. #define START_VIRTUAL_LCD 11
  40. #define STOP_VIRTUAL_LCD 10
  41. #define SET_VIRTUAL_LCD 12
  42. #define VS_MOVE_LEFT 15
  43. #define VS_MOVE_RIGHT 16
  44. #define VS_MOVE_UP 17
  45. #define VS_MOVE_DOWN 18
  46. #define MAX_DISPLAY_OFFSET 200
  47. #define DEF_DISPLAY_OFFSET 100
  48. int virtual_display_offset = DEF_DISPLAY_OFFSET;
  49. #endif
  50. //------------------ OSD (On Screen Display) -----------------------
  51. #define START_OSD 1
  52. #define STOP_OSD 0
  53. // QCIF OSD image
  54. #if defined(CONFIG_CPU_S3C2443)
  55. #define H_RESOLUTION_OSD 100 /* horizon pixel x resolition */
  56. #define V_RESOLUTION_OSD 30 /* line cnt y resolution */
  57. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  58. #define H_RESOLUTION_OSD 800 /* horizon pixel x resolition */
  59. #define V_RESOLUTION_OSD 480 /* line cnt y resolution */
  60. #endif
  61. #define ALPHA_UP 3
  62. #define ALPHA_DOWN 4
  63. #define MOVE_LEFT 5
  64. #define MOVE_RIGHT 6
  65. #define MOVE_UP 7
  66. #define MOVE_DOWN 8
  67. #define MAX_ALPHA_LEVEL 0x0f
  68. int osd_alpha_level = MAX_ALPHA_LEVEL;
  69. int osd_left_top_x = 0;
  70. int osd_left_top_y = 0;
  71. int osd_right_bottom_x = H_RESOLUTION_OSD-1;
  72. int osd_left_bottom_y = V_RESOLUTION_OSD -1;
  73. //------------------------------------------------------------------------
  74. #define H_RESOLUTION 800 /* horizon pixel x resolition */
  75. #define V_RESOLUTION 480 /* line cnt y resolution */
  76. #define H_RESOLUTION_VIRTUAL 800 /* horizon pixel x resolition */
  77. #define V_RESOLUTION_VIRTUAL 600 /* line cnt y resolution */
  78. #if defined(CONFIG_CPU_S3C2443)
  79. #define VFRAME_FREQ 75 /* frame rate freq */
  80. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  81. #define VFRAME_FREQ 60 /* frame rate freq */
  82. #endif
  83. #define PIXEL_BPP8 8
  84. #define PIXEL_BPP16 16 /* RGB 5-6-5 format for SMDK EVAL BOARD */
  85. #define PIXEL_BPP24 24 /* RGB 8-8-8 format for SMDK EVAL BOARD */
  86. #define LCD_PIXEL_CLOCK (VFRAME_FREQ *(H_FP+H_SW+H_BP+H_RESOLUTION) * (V_FP+V_SW+V_BP+V_RESOLUTION))
  87. #define PIXEL_CLOCK VFRAME_FREQ * LCD_PIXEL_CLOCK /* vclk = frame * pixel_count */
  88. #define MAX_DISPLAY_BRIGHTNESS 9
  89. #define DEF_DISPLAY_BRIGHTNESS 4
  90. int display_brightness = DEF_DISPLAY_BRIGHTNESS;
  91. void set_brightness(int);
  92. struct s3c_fb_mach_info mach_info = {
  93. #if defined(CONFIG_CPU_S3C2443)
  94. .vidcon0= S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK,
  95. .vidcon1= S3C_VIDCON1_IHSYNC_INVERT | S3C_VIDCON1_IVSYNC_INVERT,
  96. .vidtcon0= S3C_VIDTCON0_VBPDE(V_BP-1) | S3C_VIDTCON0_VFPD(V_FP-1) | S3C_VIDTCON0_VSPW(V_SW-1),
  97. .vidtcon1= S3C_VIDTCON1_HBPD(H_BP-1) | S3C_VIDTCON1_HFPD(H_FP-1 ) | S3C_VIDTCON1_HSPW(H_SW-1),
  98. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  99. .vidcon0 = S3C_VIDCON0_INTERLACE_F_PROGRESSIVE | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_L1_DATA16_SUB_16_MODE
  100. | S3C_VIDCON0_L0_DATA16_MAIN_16_MODE | S3C_VIDCON0_PNRMODE_RGB_P
  101. | S3C_VIDCON0_CLKVALUP_ALWAYS | S3C_VIDCON0_CLKDIR_DIVIDED | S3C_VIDCON0_CLKSEL_F_HCLK |
  102. S3C_VIDCON0_ENVID_DISABLE | S3C_VIDCON0_ENVID_F_DISABLE,
  103. .vidcon1 = S3C_VIDCON1_IHSYNC_NORMAL | S3C_VIDCON1_IVSYNC_NORMAL |S3C_VIDCON1_IVDEN_NORMAL | S3C_VIDCON1_IVCLK_FALL_EDGE,
  104. .vidtcon0 = S3C_VIDTCON0_VBPDE(0) | S3C_VIDTCON0_VBPD(V_BP-1) | S3C_VIDTCON0_VFPD(V_FP-1) | S3C_VIDTCON0_VSPW(V_SW-1),
  105. .vidtcon1 = S3C_VIDTCON1_VFPDE(0) | S3C_VIDTCON1_HBPD(H_BP-1) | S3C_VIDTCON1_HFPD(H_FP-1) | S3C_VIDTCON1_HSPW(H_SW-1),
  106. #endif
  107. .vidtcon2= S3C_VIDTCON2_LINEVAL(V_RESOLUTION-1) | S3C_VIDTCON2_HOZVAL(H_RESOLUTION-1),
  108. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  109. .dithmode = (S3C_DITHMODE_RDITHPOS_5BIT | S3C_DITHMODE_GDITHPOS_6BIT | S3C_DITHMODE_BDITHPOS_5BIT) & S3C_DITHMODE_DITHERING_DISABLE,
  110. //24 bit: .dithmode = (S3C_DITHMODE_RDITHPOS_8BIT | S3C_DITHMODE_GDITHPOS_8BIT | S3C_DITHMODE_BDITHPOS_8BIT) & S3C_DITHMODE_DITHERING_DISABLE,
  111. #endif
  112. #if defined (CONFIG_FB_BPP_8)
  113. .wincon0= S3C_WINCONx_BYTSWP_ENABLE |S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL, // 4word burst, 8bpp-palletized,
  114. .wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  115. //.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_A555 | S3C_WINCONx_BLD_PIX_PIXEL| S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  116. #elif defined (CONFIG_FB_BPP_16)
  117. #if defined(CONFIG_CPU_S3C2443)
  118. .wincon0= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565, // 4word burst, 16bpp,
  119. .wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  120. //.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_A555 | S3C_WINCONx_BLD_PIX_PIXEL| S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 16bpp for OSD
  121. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  122. // .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  123. .wincon0 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_1 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  124. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  125. S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  126. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  127. //S3C_WINCONx_BUFAUTOEN_ENABLE |
  128. #endif
  129. S3C_WINCONx_ENWIN_F_DISABLE, // 4word burst, 16bpp,
  130. .wincon1 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BUFSEL_0 | S3C_WINCONx_BUFAUTOEN_DISABLE | S3C_WINCONx_BITSWP_DISABLE |
  131. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE |
  132. S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  133. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  134. //S3C_WINCONx_BUFAUTOEN_ENABLE |
  135. #endif
  136. S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE, // 4word burst, 16bpp,
  137. .wincon2 = S3C_WINCONx_ENLOCAL_DMA | S3C_WINCONx_BITSWP_DISABLE |
  138. S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  139. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_BPPMODE_F_16BPP_565 |
  140. S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  141. .wincon3 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE |
  142. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE |
  143. S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  144. .wincon4 = S3C_WINCONx_BITSWP_DISABLE | S3C_WINCONx_BYTSWP_DISABLE | S3C_WINCONx_HAWSWP_ENABLE|
  145. S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BLD_PIX_PLANE |
  146. S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_ALPHA_SEL_1 | S3C_WINCONx_ENWIN_F_DISABLE,
  147. #endif
  148. #elif defined (CONFIG_FB_BPP_24)
  149. .wincon0= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888, // 4word burst, 24bpp,
  150. .wincon1= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1, // 4word burst, 24bpp for OSD
  151. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  152. .wincon2 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  153. .wincon3 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  154. .wincon4 = S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1,
  155. #endif
  156. #endif
  157. #if defined(CONFIG_CPU_S3C2443)
  158. .vidosd0a= S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  159. .vidosd0b= S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION-1),
  160. .vidosd1a= S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  161. .vidosd1b= S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  162. .vidosd1c= S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  163. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  164. .vidosd0a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  165. .vidosd0b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION-1),
  166. .vidosd0c = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  167. .vidosd1a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  168. .vidosd1b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  169. .vidosd1c= S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  170. .vidosd1d = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  171. .vidosd2a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  172. .vidosd2b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  173. .vidosd2c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  174. .vidosd2d = S3C_VIDOSDxD_OSDSIZE(H_RESOLUTION*V_RESOLUTION),
  175. .vidosd3a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  176. .vidosd3b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  177. .vidosd3c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  178. .vidosd4a = S3C_VIDOSDxA_OSD_LTX_F(0) | S3C_VIDOSDxA_OSD_LTY_F(0),
  179. .vidosd4b = S3C_VIDOSDxB_OSD_RBX_F(H_RESOLUTION_OSD-1) | S3C_VIDOSDxB_OSD_RBY_F(V_RESOLUTION_OSD-1),
  180. .vidosd4c = S3C_VIDOSDxC_ALPHA1_B(MAX_ALPHA_LEVEL) | S3C_VIDOSDxC_ALPHA1_G(MAX_ALPHA_LEVEL) |S3C_VIDOSDxC_ALPHA1_R(MAX_ALPHA_LEVEL),
  181. #endif
  182. #if defined(CONFIG_CPU_S3C2443)
  183. .vidintcon= S3C_VIDINTCON0_FRAMESEL0_VSYNC | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_ENABLE | S3C_VIDINTCON0_INTEN_ENABLE,
  184. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  185. .vidintcon0 = S3C_VIDINTCON0_FRAMESEL0_BACK | S3C_VIDINTCON0_FRAMESEL1_NONE | S3C_VIDINTCON0_INTFRMEN_DISABLE | S3C_VIDINTCON0_FIFOSEL_WIN0 | S3C_VIDINTCON0_FIFOLEVEL_25 | S3C_VIDINTCON0_INTFIFOEN_DISABLE | S3C_VIDINTCON0_INTEN_DISABLE,
  186. .vidintcon1 = 0,
  187. #endif
  188. .width= H_RESOLUTION,
  189. .height= V_RESOLUTION,
  190. .xres= H_RESOLUTION,
  191. .yres= V_RESOLUTION,
  192. .xoffset= 0,
  193. .yoffset= 0,
  194. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  195. .xres_virtual = H_RESOLUTION_VIRTUAL,
  196. .yres_virtual = V_RESOLUTION_VIRTUAL,
  197. #else
  198. .xres_virtual = H_RESOLUTION,
  199. .yres_virtual = V_RESOLUTION,
  200. #endif
  201. .osd_width= H_RESOLUTION_OSD,
  202. .osd_height= V_RESOLUTION_OSD,
  203. .osd_xres= H_RESOLUTION_OSD,
  204. .osd_yres= V_RESOLUTION_OSD,
  205. .osd_xres_virtual= H_RESOLUTION_OSD,
  206. .osd_yres_virtual= V_RESOLUTION_OSD,
  207. #if defined (CONFIG_FB_BPP_8)
  208. .bpp= PIXEL_BPP8,
  209. .bytes_per_pixel= 1,
  210. #if defined(CONFIG_CPU_S3C2443)
  211. .wpalcon= W0PAL_24BIT,
  212. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  213. .wpalcon= W0PAL_16BIT,
  214. #endif
  215. #elif defined (CONFIG_FB_BPP_16)
  216. .bpp= PIXEL_BPP16,
  217. .bytes_per_pixel= 2,
  218. #elif defined (CONFIG_FB_BPP_24)
  219. .bpp= PIXEL_BPP24,
  220. .bytes_per_pixel= 4,
  221. #endif
  222. .pixclock= PIXEL_CLOCK,
  223. .w1keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  224. S3C_WxKEYCON0_COMPKEY(0x0),
  225. .w1keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  226. .w2keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  227. S3C_WxKEYCON0_COMPKEY(0x0),
  228. .w2keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  229. .w3keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  230. S3C_WxKEYCON0_COMPKEY(0x0),
  231. .w3keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  232. .w4keycon0= S3C_WxKEYCON0_KEYBLEN_DISABLE | S3C_WxKEYCON0_KEYEN_F_DISABLE | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE |
  233. S3C_WxKEYCON0_COMPKEY(0x0),
  234. .w4keycon1= S3C_WxKEYCON1_COLVAL(0xffffff),
  235. .hsync_len= H_SW,
  236. .vsync_len= V_SW,
  237. .left_margin= H_FP,
  238. .upper_margin= V_FP,
  239. .right_margin= H_BP,
  240. .lower_margin= V_BP,
  241. .sync= 0,
  242. .cmap_static= 1,
  243. };
  244. #if defined(CONFIG_S3C6400_PWM)
  245. void set_brightness(int val)
  246. {
  247. int channel = 1; // must use channel-1
  248. int usec = 0; // don't care value
  249. unsigned long tcnt=1000;
  250. unsigned long tcmp=0;
  251. if(val < 0) val=0;
  252. if(val > MAX_DISPLAY_BRIGHTNESS) val=MAX_DISPLAY_BRIGHTNESS;
  253. display_brightness = val;
  254. switch (val) {
  255. case 0:
  256. tcmp= 0;
  257. break;
  258. case 1:
  259. tcmp= 50;
  260. break;
  261. case 2:
  262. tcmp= 100;
  263. break;
  264. case 3:
  265. tcmp= 150;
  266. break;
  267. case 4:
  268. tcmp= 200;
  269. break;
  270. case 5:
  271. tcmp= 250;
  272. break;
  273. case 6:
  274. tcmp= 300;
  275. break;
  276. case 7:
  277. tcmp= 350;
  278. break;
  279. case 8:
  280. tcmp= 400;
  281. break;
  282. case 9:
  283. tcmp= 450;
  284. break;
  285. } // end of switch (level)
  286. s3c6400_timer_setup (channel, usec, tcnt, tcmp);
  287. }
  288. #endif
  289. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  290. void set_virtual_display_offset(int val)
  291. {
  292. if(val < 1)
  293. val = 1;
  294. if(val > MAX_DISPLAY_OFFSET)
  295. val = MAX_DISPLAY_OFFSET;
  296. virtual_display_offset = val;
  297. }
  298. int set_vs_info(vs_info_t vs_info_from_app )
  299. {
  300. /* check invalid value */
  301. if(vs_info_from_app.width != H_RESOLUTION || vs_info_from_app.height != V_RESOLUTION ){
  302. return 1;
  303. }
  304. if(!(vs_info_from_app.bpp==8 ||vs_info_from_app.bpp==16 ||vs_info_from_app.bpp==24 || vs_info_from_app.bpp==32) ){
  305. return 1;
  306. }
  307. if(vs_info_from_app.offset<0){
  308. return 1;
  309. }
  310. if(vs_info_from_app.v_width != H_RESOLUTION_VIRTUAL || vs_info_from_app.v_height != V_RESOLUTION_VIRTUAL){
  311. return 1;
  312. }
  313. /* save virtual screen information */
  314. vs_info = vs_info_from_app;
  315. set_virtual_display_offset(vs_info.offset);
  316. return 0;
  317. }
  318. int set_virtual_display_register(int vs_cmd)
  319. {
  320. int PageWidth, Offset;
  321. int ShiftValue;
  322. PageWidth = mach_info.xres * mach_info.bytes_per_pixel;
  323. Offset = (mach_info.xres_virtual - mach_info.xres) * mach_info.bytes_per_pixel;
  324. switch(vs_cmd){
  325. case SET_VIRTUAL_LCD:
  326. /* size of buffer */
  327. #if defined(CONFIG_CPU_S3C2443)
  328. mach_info.vidw00add2b0 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  329. mach_info.vidw00add2b1 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  330. __raw_writel(mach_info.vidw00add2b0, S3C_VIDW00ADD2B0);
  331. __raw_writel(mach_info.vidw00add2b1, S3C_VIDW00ADD2B1);
  332. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  333. mach_info.vidw00add2 = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  334. __raw_writel(mach_info.vidw00add2, S3C_VIDW00ADD2);
  335. #endif
  336. break;
  337. case VS_MOVE_LEFT:
  338. if(mach_info.xoffset < virtual_display_offset){
  339. ShiftValue = mach_info.xoffset;
  340. }
  341. else ShiftValue = virtual_display_offset;
  342. mach_info.xoffset -= ShiftValue;
  343. /* For buffer start address */
  344. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 - ShiftValue*mach_info.bytes_per_pixel;
  345. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 - ShiftValue*mach_info.bytes_per_pixel;
  346. break;
  347. case VS_MOVE_RIGHT:
  348. if((vs_info.v_width - (mach_info.xoffset + vs_info.width) )< (virtual_display_offset)){
  349. ShiftValue = vs_info.v_width - (mach_info.xoffset + vs_info.width);
  350. }
  351. else ShiftValue = virtual_display_offset;
  352. mach_info.xoffset += ShiftValue;
  353. /* For buffer start address */
  354. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 + ShiftValue*mach_info.bytes_per_pixel;
  355. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 + ShiftValue*mach_info.bytes_per_pixel;
  356. break;
  357. case VS_MOVE_UP:
  358. if(mach_info.yoffset < virtual_display_offset){
  359. ShiftValue = mach_info.yoffset;
  360. }
  361. else ShiftValue = virtual_display_offset;
  362. mach_info.yoffset -= ShiftValue;
  363. /* For buffer start address */
  364. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 - ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  365. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 - ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  366. break;
  367. case VS_MOVE_DOWN:
  368. if((vs_info.v_height - (mach_info.yoffset + vs_info.height) )< (virtual_display_offset)){
  369. ShiftValue = vs_info.v_height - (mach_info.yoffset + vs_info.height);
  370. }
  371. else ShiftValue = virtual_display_offset;
  372. mach_info.yoffset += ShiftValue;
  373. /* For buffer start address */
  374. mach_info.vidw00add0b0 = mach_info.vidw00add0b0 + ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  375. mach_info.vidw00add0b1 = mach_info.vidw00add0b1 + ShiftValue*mach_info.xres_virtual*mach_info.bytes_per_pixel;
  376. break;
  377. default:
  378. return -EINVAL;
  379. }
  380. /* End address */
  381. mach_info.vidw00add1b0 = S3C_VIDWxxADD1_VBASEL_F(mach_info.vidw00add0b0 + (PageWidth + Offset) * (mach_info.yres));
  382. mach_info.vidw00add1b1 = S3C_VIDWxxADD1_VBASEL_F(mach_info.vidw00add0b1 + (PageWidth + Offset) * (mach_info.yres));
  383. __raw_writel(mach_info.vidw00add0b0, S3C_VIDW00ADD0B0);
  384. __raw_writel(mach_info.vidw00add0b1, S3C_VIDW00ADD0B1);
  385. __raw_writel(mach_info.vidw00add1b0, S3C_VIDW00ADD1B0);
  386. __raw_writel(mach_info.vidw00add1b1, S3C_VIDW00ADD1B1);
  387. return 0;
  388. }
  389. #endif
  390. /*
  391. * As LCD-Brightness is best related to Display and hence FrameBuffer,
  392. * so we put the brightness control in /dev/fb.
  393. */
  394. #define GET_DISPLAY_BRIGHTNESS _IOR('F', 1, u_int) /* get brightness */
  395. #define SET_DISPLAY_BRIGHTNESS _IOW('F', 2, u_int) /* set brightness */
  396. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  397. #define SET_VS_START _IO('F', 103)
  398. #define SET_VS_STOP _IO('F', 104)
  399. #define SET_VS_INFO _IOW('F', 105, vs_info_t)
  400. #define SET_VS_MOVE _IOW('F', 106, u_int)
  401. #endif
  402. #define SET_OSD_START _IO('F', 201)
  403. #define SET_OSD_STOP _IO('F', 202)
  404. #define SET_OSD_ALPHA_UP _IO('F', 203)
  405. #define SET_OSD_ALPHA_DOWN _IO('F', 204)
  406. #define SET_OSD_MOVE_LEFT _IO('F', 205)
  407. #define SET_OSD_MOVE_RIGHT _IO('F', 206)
  408. #define SET_OSD_MOVE_UP _IO('F', 207)
  409. #define SET_OSD_MOVE_DOWN _IO('F', 208)
  410. #define SET_OSD_INFO _IOW('F', 209, s3c_win_info_t)
  411. #if 0
  412. #define SET_OSD_BRIGHT _IOW('F', 210, int)
  413. #endif
  414. #define SET_COLOR_KEY_START _IO('F', 300)
  415. #define SET_COLOR_KEY_STOP _IO('F', 301)
  416. #define SET_COLOR_KEY_ALPHA_START _IO('F', 302)
  417. #define SET_COLOR_KEY_ALPHA_STOP _IO('F', 303)
  418. #define SET_COLOR_KEY_INFO _IOW('F', 304, s3c_color_key_info_t)
  419. #define SET_COLOR_KEY_COLVAL _IOW('F', 305, s3c_color_val_info_t)
  420. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  421. #define GET_FB_NUM _IOWR('F', 306, u_int)
  422. #endif
  423. int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  424. {
  425. struct s3c_fb_info *fbi = container_of(info, struct s3c_fb_info, fb);
  426. struct fb_var_screeninfo *var= &fbi->fb.var;
  427. int brightness;
  428. s3c_win_info_t win_info_from_app;
  429. s3c_color_key_info_t colkey_info;
  430. s3c_color_val_info_t colval_info;
  431. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  432. u_int f_num_val;
  433. #endif
  434. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  435. vs_info_t vs_info_from_app;
  436. #endif
  437. switch(cmd){
  438. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  439. case SET_VS_START:
  440. mach_info.wincon0 &= ~(S3C_WINCONx_ENWIN_F_ENABLE);
  441. __raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
  442. fbi->fb.var.xoffset = mach_info.xoffset;
  443. fbi->fb.var.yoffset = mach_info.yoffset;
  444. break;
  445. case SET_VS_STOP:
  446. break;
  447. case SET_VS_INFO:
  448. if(copy_from_user(&vs_info_from_app, (vs_info_t *) arg, sizeof(vs_info_t)))
  449. return -EFAULT;
  450. if(set_vs_info(vs_info_from_app)){
  451. printk("Error SET_VS_INFO\n");
  452. return -EINVAL;
  453. }
  454. set_virtual_display_register(SET_VIRTUAL_LCD);
  455. fbi->fb.var.xoffset = mach_info.xoffset;
  456. fbi->fb.var.yoffset = mach_info.yoffset;
  457. break;
  458. case SET_VS_MOVE:
  459. set_virtual_display_register(arg);
  460. fbi->fb.var.xoffset = mach_info.xoffset;
  461. fbi->fb.var.yoffset = mach_info.yoffset;
  462. break;
  463. #endif
  464. case SET_OSD_INFO :
  465. if(copy_from_user
  466. (&win_info_from_app, (s3c_win_info_t *) arg,
  467. sizeof(s3c_win_info_t)))
  468. return -EFAULT;
  469. s3c_fb_init_win(fbi, win_info_from_app.Bpp,
  470. win_info_from_app.LeftTop_x, win_info_from_app.LeftTop_y, win_info_from_app.Width, win_info_from_app.Height, OFF);
  471. break;
  472. case SET_OSD_START :
  473. s3c_fb_win_onoff(fbi, ON); // on
  474. break;
  475. case SET_OSD_STOP:
  476. s3c_fb_win_onoff(fbi, OFF); // off
  477. break;
  478. case SET_OSD_ALPHA_UP:
  479. if(osd_alpha_level < MAX_ALPHA_LEVEL) osd_alpha_level ++;
  480. s3c_fb_set_alpha_level(fbi);
  481. break;
  482. case SET_OSD_ALPHA_DOWN:
  483. if(osd_alpha_level > 0) osd_alpha_level --;
  484. s3c_fb_set_alpha_level(fbi);
  485. break;
  486. case SET_OSD_MOVE_LEFT:
  487. if(var->xoffset>0) var->xoffset--;
  488. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  489. break;
  490. case SET_OSD_MOVE_RIGHT:
  491. if(var->xoffset < (H_RESOLUTION - var->xres)) var->xoffset ++;
  492. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  493. break;
  494. case SET_OSD_MOVE_UP:
  495. if(var->yoffset>0) var->yoffset--;
  496. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  497. break;
  498. case SET_OSD_MOVE_DOWN:
  499. if(var->yoffset < (V_RESOLUTION - var->yres)) var->yoffset ++;
  500. s3c_fb_set_position_win(fbi, var->xoffset, var->yoffset, var->xres, var->yres);
  501. break;
  502. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  503. case GET_FB_NUM:
  504. if(copy_from_user((void *)&f_num_val, (const void *)arg, sizeof(u_int)))
  505. return -EFAULT;
  506. if(copy_to_user((void *)arg, (const void *) &f_num_val, sizeof(u_int)))
  507. return -EFAULT;
  508. break;
  509. #endif
  510. case SET_DISPLAY_BRIGHTNESS:
  511. if(copy_from_user(&brightness, (int *) arg, sizeof(int)))
  512. return -EFAULT;
  513. #if defined(CONFIG_S3C6400_PWM)
  514. set_brightness(brightness);
  515. #endif
  516. break;
  517. case GET_DISPLAY_BRIGHTNESS:
  518. if(copy_to_user((void *)arg, (const void *) &display_brightness, sizeof(int)))
  519. return -EFAULT;
  520. break;
  521. //(WAITFORVSYNC)
  522. case FBIO_WAITFORVSYNC:
  523. {
  524. u_int32_t crt;
  525. if (get_user(crt, (u_int32_t __user *)arg))
  526. return -EFAULT;
  527. return s3cfb_wait_for_sync(crt);
  528. }
  529. //(WAITFORVSYNC)
  530. case SET_COLOR_KEY_START:
  531. s3c_fb_color_key_onoff(fbi, ON);
  532. break;
  533. case SET_COLOR_KEY_STOP:
  534. s3c_fb_color_key_onoff(fbi, OFF);
  535. break;
  536. case SET_COLOR_KEY_ALPHA_START:
  537. s3c_fb_color_key_alpha_onoff(fbi, ON);
  538. break;
  539. case SET_COLOR_KEY_ALPHA_STOP:
  540. s3c_fb_color_key_alpha_onoff(fbi, OFF);
  541. break;
  542. case SET_COLOR_KEY_INFO:
  543. if(copy_from_user(&colkey_info, (s3c_color_key_info_t *) arg,
  544. sizeof(s3c_color_key_info_t)))
  545. return -EFAULT;
  546. s3c_fb_setup_color_key_register(fbi, colkey_info);
  547. break;
  548. case SET_COLOR_KEY_COLVAL:
  549. if(copy_from_user(&colval_info, (s3c_color_val_info_t *) arg,
  550. sizeof(s3c_color_val_info_t)))
  551. return -EFAULT;
  552. s3c_fb_set_color_value(fbi, colval_info);
  553. break;
  554. default:
  555. return -EINVAL;
  556. }
  557. return 0;
  558. }
  559. /*
  560. * s3c_fb_map_video_memory():
  561. * Allocates the DRAM memory for the frame buffer. This buffer is
  562. * remapped into a non-cached, non-buffered, memory region to
  563. * allow palette and pixel writes to occur without flushing the
  564. * cache. Once this area is remapped, all virtual memory
  565. * access to the video memory should occur at the new region.
  566. */
  567. int __init s3c_fb_map_video_memory(struct s3c_fb_info *fbi)
  568. {
  569. dprintk("map_video_memory(fbi=%p)\n", fbi);
  570. fbi->map_size_f1 = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  571. fbi->map_cpu_f1 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f1,
  572. &fbi->map_dma_f1, GFP_KERNEL);
  573. fbi->map_size_f1 = fbi->fb.fix.smem_len;
  574. if (fbi->map_cpu_f1) {
  575. /* prevent initial garbage on screen */
  576. printk("Window[%d]- FB1 : map_video_memory: clear %p:%08x\n",
  577. fbi->win_id, fbi->map_cpu_f1, fbi->map_size_f1);
  578. memset(fbi->map_cpu_f1, 0xf0, fbi->map_size_f1);
  579. fbi->screen_dma_f1 = fbi->map_dma_f1;
  580. fbi->fb.screen_base = fbi->map_cpu_f1;
  581. fbi->fb.fix.smem_start = fbi->screen_dma_f1;
  582. printk(" FB1 : map_video_memory: dma=%08x cpu=%p size=%08x\n",
  583. fbi->map_dma_f1, fbi->map_cpu_f1, fbi->fb.fix.smem_len);
  584. }
  585. if( !fbi->map_cpu_f1)
  586. return -ENOMEM;
  587. //#if !defined(CONFIG_FB_VIRTUAL_SCREEN) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  588. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  589. #if defined(CONFIG_CPU_S3C2443)
  590. if(fbi->win_id<1){ // WIN0 support double-buffer
  591. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  592. if(fbi->win_id<2){ // WIN0, WIN1 support double-buffer
  593. #endif
  594. fbi->map_size_f2 = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  595. fbi->map_cpu_f2 = dma_alloc_writecombine(fbi->dev, fbi->map_size_f2,
  596. &fbi->map_dma_f2, GFP_KERNEL);
  597. fbi->map_size_f2 = fbi->fb.fix.smem_len;
  598. if (fbi->map_cpu_f2) {
  599. /* prevent initial garbage on screen */
  600. printk("Window[%d] - FB2 : map_video_memory: clear %p:%08x\n",
  601. fbi->win_id, fbi->map_cpu_f2, fbi->map_size_f2);
  602. memset(fbi->map_cpu_f2, 0xf0, fbi->map_size_f2);
  603. fbi->screen_dma_f2 = fbi->map_dma_f2;
  604. printk(" FB2 : map_video_memory: dma=%08x cpu=%p size=%08x\n",
  605. fbi->map_dma_f2, fbi->map_cpu_f2, fbi->fb.fix.smem_len);
  606. }
  607. if( !fbi->map_cpu_f2)
  608. return -ENOMEM;
  609. }
  610. #endif
  611. return 0;
  612. }
  613. void s3c_fb_unmap_video_memory(struct s3c_fb_info *fbi)
  614. {
  615. dma_free_writecombine(fbi->dev, fbi->map_size_f1, fbi->map_cpu_f1, fbi->map_dma_f1);
  616. //#if !defined(CONFIG_FB_VIRTUAL_SCREEN) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  617. #if defined(CONFIG_FB_DOUBLE_BUFFERING)
  618. dma_free_writecombine(fbi->dev, fbi->map_size_f2, fbi->map_cpu_f2, fbi->map_dma_f2);
  619. #endif
  620. }
  621. /*
  622. * s3c_fb_init_registers - Initialise all LCD-related registers
  623. */
  624. int s3c_fb_init_registers(struct s3c_fb_info *fbi)
  625. {
  626. u_long flags = 0;
  627. u_long PageWidth = 0, Offset = 0;
  628. int win_num = fbi->win_id;
  629. struct clk *lcd_clock;
  630. struct fb_var_screeninfo *var= &fbi->fb.var;
  631. unsigned long VideoPhysicalTemp_f1 = fbi->screen_dma_f1;
  632. unsigned long VideoPhysicalTemp_f2 = fbi->screen_dma_f2;
  633. /* Initialise LCD with values from hare */
  634. local_irq_save(flags);
  635. if(win_num==0){
  636. mach_info.vidcon0 = mach_info.vidcon0 & ~(S3C_VIDCON0_ENVID_ENABLE | S3C_VIDCON0_ENVID_F_ENABLE);
  637. __raw_writel(mach_info.vidcon0, S3C_VIDCON0);
  638. lcd_clock = clk_get(NULL, "lcd");
  639. mach_info.vidcon0 |= S3C_VIDCON0_CLKVAL_F((int)((clk_get_rate(lcd_clock) / LCD_PIXEL_CLOCK) - 1));
  640. }
  641. /* For buffer start address */
  642. __raw_writel(VideoPhysicalTemp_f1, S3C_VIDW00ADD0B0+(0x08*win_num));
  643. #if defined(CONFIG_CPU_S3C2443)
  644. if(win_num==0) __raw_writel(VideoPhysicalTemp_f2, S3C_VIDW00ADD0B1);
  645. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  646. if(win_num<2) __raw_writel(VideoPhysicalTemp_f2, S3C_VIDW00ADD0B1+(0x08*win_num));
  647. #endif
  648. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  649. if(win_num==0){
  650. mach_info.vidw00add0b0=VideoPhysicalTemp_f1;
  651. mach_info.vidw00add0b1=VideoPhysicalTemp_f2;
  652. }
  653. #endif
  654. PageWidth = var->xres * mach_info.bytes_per_pixel;
  655. Offset = (var->xres_virtual - var->xres) * mach_info.bytes_per_pixel;
  656. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  657. if(win_num==0) Offset=0;
  658. #endif
  659. /* End address */
  660. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f1 + (PageWidth + Offset) * (var->yres)),
  661. S3C_VIDW00ADD1B0+(0x08*win_num));
  662. #if defined(CONFIG_CPU_S3C2443)
  663. if(win_num==0)
  664. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres)),
  665. S3C_VIDW00ADD1B1);
  666. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  667. if(win_num<2)
  668. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres)),
  669. S3C_VIDW00ADD1B1+(0x08*win_num));
  670. #endif
  671. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  672. if(win_num==0){
  673. mach_info.vidw00add1b0=S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f1 + (PageWidth + Offset) * (var->yres));
  674. mach_info.vidw00add1b1=S3C_VIDWxxADD1_VBASEL_F((unsigned long) VideoPhysicalTemp_f2 + (PageWidth + Offset) * (var->yres));
  675. }
  676. #endif
  677. /* size of buffer */
  678. #if defined(CONFIG_CPU_S3C2443)
  679. __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2B0+(0x08*win_num));
  680. if(win_num==0) __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2B1);
  681. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  682. __raw_writel(S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth)), S3C_VIDW00ADD2+(0x04*win_num));
  683. #endif
  684. switch(win_num){
  685. case 0:
  686. __raw_writel(mach_info.wincon0, S3C_WINCON0);
  687. __raw_writel(mach_info.vidcon0, S3C_VIDCON0);
  688. __raw_writel(mach_info.vidcon1, S3C_VIDCON1);
  689. __raw_writel(mach_info.vidtcon0, S3C_VIDTCON0);
  690. __raw_writel(mach_info.vidtcon1, S3C_VIDTCON1);
  691. __raw_writel(mach_info.vidtcon2, S3C_VIDTCON2);
  692. #if defined(CONFIG_CPU_S3C2443)
  693. __raw_writel(mach_info.vidintcon, S3C_VIDINTCON);
  694. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  695. __raw_writel(mach_info.dithmode, S3C_DITHMODE);
  696. __raw_writel(mach_info.vidintcon0, S3C_VIDINTCON0);
  697. __raw_writel(mach_info.vidintcon1, S3C_VIDINTCON1);
  698. #endif
  699. __raw_writel(mach_info.vidosd0a, S3C_VIDOSD0A);
  700. __raw_writel(mach_info.vidosd0b, S3C_VIDOSD0B);
  701. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  702. __raw_writel(mach_info.vidosd0c, S3C_VIDOSD0C);
  703. #endif
  704. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  705. s3c_fb_win_onoff(fbi, ON);
  706. break;
  707. case 1:
  708. __raw_writel(mach_info.wincon1, S3C_WINCON1);
  709. __raw_writel(mach_info.vidosd1a, S3C_VIDOSD1A);
  710. __raw_writel(mach_info.vidosd1b, S3C_VIDOSD1B);
  711. __raw_writel(mach_info.vidosd1c, S3C_VIDOSD1C);
  712. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  713. __raw_writel(mach_info.vidosd1d, S3C_VIDOSD1D);
  714. #endif
  715. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  716. s3c_fb_win_onoff(fbi, OFF);
  717. break;
  718. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  719. case 2:
  720. __raw_writel(mach_info.wincon2, S3C_WINCON2);
  721. __raw_writel(mach_info.vidosd2a, S3C_VIDOSD2A);
  722. __raw_writel(mach_info.vidosd2b, S3C_VIDOSD2B);
  723. __raw_writel(mach_info.vidosd2c, S3C_VIDOSD2C);
  724. __raw_writel(mach_info.vidosd2d, S3C_VIDOSD2D);
  725. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  726. s3c_fb_win_onoff(fbi, OFF);
  727. break;
  728. case 3:
  729. __raw_writel(mach_info.wincon3, S3C_WINCON3);
  730. __raw_writel(mach_info.vidosd3a, S3C_VIDOSD3A);
  731. __raw_writel(mach_info.vidosd3b, S3C_VIDOSD3B);
  732. __raw_writel(mach_info.vidosd3c, S3C_VIDOSD3C);
  733. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  734. s3c_fb_win_onoff(fbi, OFF);
  735. break;
  736. case 4:
  737. __raw_writel(mach_info.wincon4, S3C_WINCON4);
  738. __raw_writel(mach_info.vidosd4a, S3C_VIDOSD4A);
  739. __raw_writel(mach_info.vidosd4b, S3C_VIDOSD4B);
  740. __raw_writel(mach_info.vidosd4c, S3C_VIDOSD4C);
  741. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  742. s3c_fb_win_onoff(fbi, OFF);
  743. break;
  744. #endif
  745. }
  746. local_irq_restore(flags);
  747. return 0;
  748. }
  749. /* s3c_fb_set_lcdaddr
  750. *
  751. * initialise lcd controller address pointers
  752. */
  753. void s3c_fb_set_lcdaddr(struct s3c_fb_info *fbi)
  754. {
  755. u32 start;
  756. unsigned long VideoPhysicalTemp_f1 = fbi->screen_dma_f1;
  757. start = fbi->fb.fix.line_length * fbi->fb.var.yoffset;
  758. /* For buffer start address */
  759. mach_info.vidw00add0b0 = VideoPhysicalTemp_f1+start;
  760. mach_info.vidw00add1b0 = mach_info.vidw00add0b0+(fbi->fb.fix.line_length*fbi->fb.var.yres);
  761. __raw_writel(mach_info.vidw00add0b0, S3C_VIDW00ADD0B0);
  762. __raw_writel(mach_info.vidw00add1b0, S3C_VIDW00ADD1B0);
  763. }
  764. void s3c_fb_set_fb_change(int req_fb) {
  765. info[req_fb].fb_change_ready = 0;
  766. #if defined(CONFIG_CPU_S3C2443) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  767. // Software-based trigger
  768. __raw_writel((1<<0), S3C_CPUTRIGCON2);
  769. #elif (defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)) && defined(CONFIG_FB_DOUBLE_BUFFERING)
  770. // Software-based trigger
  771. __raw_writel((3<<0), S3C_TRIGCON);
  772. #endif // #if defined(CONFIG_CPU_S3C2443)
  773. }
  774. /* s3c_fb_activate_var
  775. *
  776. * activate (set) the controller from the given framebuffer
  777. * information
  778. */
  779. void s3c_fb_activate_var(struct s3c_fb_info *fbi,
  780. struct fb_var_screeninfo *var)
  781. {
  782. dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
  783. switch (var->bits_per_pixel) {
  784. case 8:
  785. mach_info.wincon0= S3C_WINCONx_BYTSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_8BPP_PAL; // 4word burst, 8bpp-palletized,
  786. mach_info.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  787. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  788. mach_info.wincon2= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  789. mach_info.wincon3= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  790. mach_info.wincon4= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 16bpp for OSD
  791. #endif
  792. mach_info.bpp= PIXEL_BPP8;
  793. mach_info.bytes_per_pixel= 1;
  794. #if defined(CONFIG_CPU_S3C2443)
  795. mach_info.wpalcon= S3C_WPALCON_W0PAL_24BIT;
  796. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  797. mach_info.wpalcon= S3C_WPALCON_W0PAL_16BIT;
  798. #endif
  799. break;
  800. case 16:
  801. mach_info.wincon0= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565; // 4word burst, 16bpp,
  802. mach_info.wincon1= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  803. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  804. mach_info.wincon2= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  805. mach_info.wincon3= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  806. mach_info.wincon4= S3C_WINCONx_HAWSWP_ENABLE | S3C_WINCONx_BURSTLEN_4WORD | S3C_WINCONx_BPPMODE_F_16BPP_565 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; //
  807. #endif
  808. mach_info.bpp= PIXEL_BPP16;
  809. mach_info.bytes_per_pixel= 2;
  810. break;
  811. case 24:
  812. mach_info.wincon0= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888; // 4word burst, 24bpp,,
  813. mach_info.wincon1= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  814. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  815. mach_info.wincon2= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  816. mach_info.wincon3= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  817. mach_info.wincon4= S3C_WINCONx_HAWSWP_DISABLE | S3C_WINCONx_BURSTLEN_16WORD | S3C_WINCONx_BPPMODE_F_24BPP_888 | S3C_WINCONx_BLD_PIX_PLANE | S3C_WINCONx_ALPHA_SEL_1; // 4word burst, 24bpp for OSD
  818. #endif
  819. mach_info.bpp= PIXEL_BPP24;
  820. mach_info.bytes_per_pixel= 4;
  821. break;
  822. case 32:
  823. mach_info.bytes_per_pixel= 4;
  824. break;
  825. }
  826. /* write new registers */
  827. __raw_writel(mach_info.wincon0, S3C_WINCON0);
  828. __raw_writel(mach_info.wincon1, S3C_WINCON1);
  829. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  830. __raw_writel(mach_info.wincon2, S3C_WINCON2);
  831. __raw_writel(mach_info.wincon3, S3C_WINCON3);
  832. __raw_writel(mach_info.wincon4, S3C_WINCON4);
  833. #endif
  834. __raw_writel(mach_info.wpalcon, S3C_WPALCON);
  835. #if 0
  836. /* set lcd address pointers */
  837. s3c_fb_set_lcdaddr(fbi);
  838. #endif
  839. //__raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE|S3C_WINCONx_BUFAUTOEN_ENABLE, S3C_WINCON0); /* Double buffer auto enable bit */
  840. __raw_writel(mach_info.wincon0|S3C_WINCONx_ENWIN_F_ENABLE, S3C_WINCON0);
  841. __raw_writel(mach_info.vidcon0|S3C_VIDCON0_ENVID_ENABLE|S3C_VIDCON0_ENVID_F_ENABLE, S3C_VIDCON0);
  842. }
  843. int s3c_fb_init_win (struct s3c_fb_info *fbi, int Bpp, int LeftTop_x, int LeftTop_y, int Width, int Height, int OnOff)
  844. {
  845. s3c_fb_win_onoff(fbi, OFF); // off
  846. s3c_fb_set_bpp(fbi, Bpp);
  847. s3c_fb_set_position_win(fbi, LeftTop_x, LeftTop_y, Width, Height);
  848. s3c_fb_set_size_win(fbi, Width, Height);
  849. s3c_fb_set_memory_size_win(fbi);
  850. s3c_fb_win_onoff(fbi, OnOff); // off
  851. return 0;
  852. }
  853. int s3c_fb_win_onoff(struct s3c_fb_info *fbi, int On)
  854. {
  855. int win_num = fbi->win_id;
  856. if(On)
  857. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_ENWIN_F_ENABLE,
  858. S3C_WINCON0+(0x04*win_num)); // ON
  859. else
  860. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))&~(S3C_WINCONx_ENWIN_F_ENABLE),
  861. S3C_WINCON0+(0x04*win_num)); // OFF
  862. return 0;
  863. }
  864. int s3c_fb_set_alpha_level(struct s3c_fb_info *fbi)
  865. {
  866. unsigned long alpha_val;
  867. int win_num = fbi->win_id;
  868. if(win_num==0){
  869. printk("WIN0 do not support alpha blending.\n");
  870. return -1;
  871. }
  872. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  873. #if defined(CONFIG_CPU_S3C2443)
  874. __raw_writel(alpha_val, S3C_VIDOSD1C);
  875. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  876. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  877. #endif
  878. return 0;
  879. }
  880. int s3c_fb_set_alpha_mode(struct s3c_fb_info *fbi, int Alpha_mode, int Alpha_level)
  881. {
  882. unsigned long alpha_val;
  883. int win_num = fbi->win_id;
  884. if(win_num==0){
  885. printk("WIN0 do not support alpha blending.\n");
  886. return -1;
  887. }
  888. switch(Alpha_mode){
  889. case 0: // Plane Blending
  890. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BLD_PIX_PLANE,
  891. S3C_WINCON0+(0x04*win_num));
  892. break;
  893. case 1: // Pixel Blending & chroma(color) key
  894. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BLD_PIX_PIXEL|S3C_WINCONx_ALPHA_SEL_0,
  895. S3C_WINCON0+(0x04*win_num));
  896. break;
  897. }
  898. osd_alpha_level = Alpha_level;
  899. alpha_val = S3C_VIDOSDxC_ALPHA1_B(osd_alpha_level) | S3C_VIDOSDxC_ALPHA1_G(osd_alpha_level) |S3C_VIDOSDxC_ALPHA1_R(osd_alpha_level);
  900. #if defined(CONFIG_CPU_S3C2443)
  901. __raw_writel(alpha_val, S3C_VIDOSD1C);
  902. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  903. __raw_writel(alpha_val, S3C_VIDOSD0C+(0x10*win_num));
  904. #endif
  905. return 0;
  906. }
  907. /*------------------------- Set up color key ------------------------------*/
  908. int s3c_fb_color_key_alpha_onoff(struct s3c_fb_info *fbi, int On)
  909. {
  910. int win_num = fbi->win_id;
  911. win_num--;
  912. if(On)
  913. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))|S3C_WxKEYCON0_KEYBLEN_ENABLE,
  914. S3C_W1KEYCON0+(0x08*win_num)); // ON
  915. else
  916. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))&~(S3C_WxKEYCON0_KEYBLEN_ENABLE),
  917. S3C_W1KEYCON0+(0x08*win_num)); // OFF
  918. return 0;
  919. }
  920. int s3c_fb_color_key_onoff(struct s3c_fb_info *fbi, int On)
  921. {
  922. int win_num = fbi->win_id;
  923. win_num--;
  924. if(On)
  925. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))|S3C_WxKEYCON0_KEYEN_F_ENABLE,
  926. S3C_W1KEYCON0+(0x08*win_num)); // ON
  927. else
  928. __raw_writel(__raw_readl(S3C_W1KEYCON0+(0x08*win_num))&~(S3C_WxKEYCON0_KEYEN_F_ENABLE),
  929. S3C_W1KEYCON0+(0x08*win_num)); // OFF
  930. return 0;
  931. }
  932. int s3c_fb_setup_color_key_register(struct s3c_fb_info *fbi, s3c_color_key_info_t colkey_info)
  933. {
  934. unsigned int compkey = 0;
  935. int win_num = fbi->win_id;
  936. if(win_num==0){
  937. printk("WIN0 do not support color-key.\n");
  938. return -1;
  939. }
  940. win_num--;
  941. if(fbi->fb.var.bits_per_pixel == PIXEL_BPP16) {
  942. /* RGB 5-6-5 mode */
  943. compkey = (((colkey_info.compkey_red & 0x1F) << 19) | 0x70000);
  944. compkey |= (((colkey_info.compkey_green & 0x3F) << 10) | 0x300);
  945. compkey |= (((colkey_info.compkey_blue & 0x1F) << 3 )| 0x7);
  946. }
  947. else if (fbi->fb.var.bits_per_pixel == PIXEL_BPP24) {
  948. /* currently RGB 8-8-8 mode */
  949. compkey = ((colkey_info.compkey_red & 0xFF) << 16);
  950. compkey |= ((colkey_info.compkey_green & 0xFF) << 8);
  951. compkey |= ((colkey_info.compkey_blue & 0xFF) << 0);
  952. }
  953. else
  954. printk("Invalid BPP has been given !\n");
  955. if(colkey_info.direction == COLOR_KEY_DIR_BG_DISPLAY)
  956. __raw_writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_FG_IMAGE, S3C_W1KEYCON0+(0x08*win_num));
  957. else if (colkey_info.direction == COLOR_KEY_DIR_FG_DISPLAY)
  958. __raw_writel(S3C_WxKEYCON0_COMPKEY(compkey) | S3C_WxKEYCON0_DIRCON_MATCH_BG_IMAGE, S3C_W1KEYCON0+(0x08*win_num));
  959. else
  960. printk("Color key direction is not correct :: %d!!!\n", colkey_info.direction);
  961. return 0;
  962. }
  963. int s3c_fb_set_color_value(struct s3c_fb_info *fbi, s3c_color_val_info_t colval_info)
  964. {
  965. unsigned int colval = 0;
  966. int win_num = fbi->win_id;
  967. if(win_num==0){
  968. printk("WIN0 do not support color-key value.\n");
  969. return -1;
  970. }
  971. win_num--;
  972. if(fbi->fb.var.bits_per_pixel == PIXEL_BPP16) {
  973. /* RGB 5-6-5 mode */
  974. colval = (((colval_info.colval_red & 0x1F) << 19) | 0x70000);
  975. colval |= (((colval_info.colval_green & 0x3F) << 10) | 0x300);
  976. colval |= (((colval_info.colval_blue & 0x1F) << 3 )| 0x7);
  977. }
  978. else if (fbi->fb.var.bits_per_pixel == PIXEL_BPP24) {
  979. /* currently RGB 8-8-8 mode */
  980. colval = ((colval_info.colval_red & 0xFF) << 16);
  981. colval |= ((colval_info.colval_green & 0xFF) << 8);
  982. colval |= ((colval_info.colval_blue & 0xFF) << 0);
  983. }
  984. else
  985. printk("Invalid BPP has been given !\n");
  986. __raw_writel(S3C_WxKEYCON1_COLVAL(colval), S3C_W1KEYCON1+(0x08*win_num));
  987. return 0;
  988. }
  989. /*--------------------------------------------------------------------------*/
  990. int s3c_fb_set_position_win(struct s3c_fb_info *fbi, int LeftTop_x, int LeftTop_y, int Width, int Height)
  991. {
  992. struct fb_var_screeninfo *var= &fbi->fb.var;
  993. int win_num = fbi->win_id;
  994. #if 0
  995. if(win_num==0){
  996. printk("WIN0 do not support window position control.\n");
  997. return -1;
  998. }
  999. #endif
  1000. #if defined(CONFIG_CPU_S3C2443)
  1001. __raw_writel(S3C_VIDOSDxA_OSD_LTX_F(LeftTop_x) | S3C_VIDOSDxA_OSD_LTY_F(LeftTop_y),
  1002. S3C_VIDOSD0A+(0x0c*win_num));
  1003. __raw_writel(S3C_VIDOSDxB_OSD_RBX_F(Width-1 + LeftTop_x) | S3C_VIDOSDxB_OSD_RBY_F(Height-1 + LeftTop_y),
  1004. S3C_VIDOSD0B+(0x0c*win_num));
  1005. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1006. __raw_writel(S3C_VIDOSDxA_OSD_LTX_F(LeftTop_x) | S3C_VIDOSDxA_OSD_LTY_F(LeftTop_y),
  1007. S3C_VIDOSD0A+(0x10*win_num));
  1008. __raw_writel(S3C_VIDOSDxB_OSD_RBX_F(Width-1 + LeftTop_x) | S3C_VIDOSDxB_OSD_RBY_F(Height-1 + LeftTop_y),
  1009. S3C_VIDOSD0B+(0x10*win_num));
  1010. #endif
  1011. var->xoffset=LeftTop_x;
  1012. var->yoffset=LeftTop_y;
  1013. return 0;
  1014. }
  1015. int s3c_fb_set_size_win(struct s3c_fb_info *fbi, int Width, int Height)
  1016. {
  1017. struct fb_var_screeninfo *var= &fbi->fb.var;
  1018. int win_num = fbi->win_id;
  1019. #if 0
  1020. if(win_num==0){
  1021. printk("WIN0 do not support window size control.\n");
  1022. return -1;
  1023. }
  1024. #endif
  1025. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1026. if(win_num==1)
  1027. __raw_writel(S3C_VIDOSD0C_OSDSIZE(Width*Height),S3C_VIDOSD1D);
  1028. else if(win_num==2)
  1029. __raw_writel(S3C_VIDOSD0C_OSDSIZE(Width*Height),S3C_VIDOSD2D);
  1030. #endif
  1031. var->xres = Width;
  1032. var->yres = Height;
  1033. var->xres_virtual = Width;
  1034. var->yres_virtual= Height;
  1035. return 0;
  1036. }
  1037. int s3c_fb_set_bpp(struct s3c_fb_info *fbi, int Bpp)
  1038. {
  1039. struct fb_var_screeninfo *var= &fbi->fb.var;
  1040. int win_num = fbi->win_id;
  1041. switch(Bpp){
  1042. case 1:
  1043. case 2:
  1044. case 4:
  1045. case 8:
  1046. // What should I do???
  1047. break;
  1048. case 16:
  1049. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BPPMODE_F_16BPP_565,
  1050. S3C_WINCON0+(0x04*win_num));
  1051. var->bits_per_pixel=16;
  1052. break;
  1053. case 24:
  1054. __raw_writel(__raw_readl(S3C_WINCON0+(0x04*win_num))|S3C_WINCONx_BPPMODE_F_24BPP_888,
  1055. S3C_WINCON0+(0x04*win_num));
  1056. var->bits_per_pixel=24;
  1057. break;
  1058. case 32:
  1059. var->bits_per_pixel=32;
  1060. break;
  1061. }
  1062. return 0;
  1063. }
  1064. int s3c_fb_set_memory_size_win(struct s3c_fb_info *fbi)
  1065. {
  1066. struct fb_var_screeninfo *var= &fbi->fb.var;
  1067. int win_num = fbi->win_id;
  1068. unsigned long Offset = 0;
  1069. unsigned long PageWidth = 0;
  1070. unsigned long FrameBufferSize = 0;
  1071. PageWidth = var->xres * mach_info.bytes_per_pixel;
  1072. Offset = (var->xres_virtual - var->xres) * mach_info.bytes_per_pixel;
  1073. #if defined(CONFIG_FB_VIRTUAL_SCREEN)
  1074. if(win_num==0) Offset=0;
  1075. #endif
  1076. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long)__raw_readl(S3C_VIDW00ADD0B0+(0x08*win_num)) + (PageWidth + Offset) * (var->yres)),
  1077. S3C_VIDW00ADD1B0+(0x08*win_num));
  1078. if(win_num==1)
  1079. __raw_writel(S3C_VIDWxxADD1_VBASEL_F((unsigned long)__raw_readl(S3C_VIDW00ADD0B1+(0x08*win_num)) + (PageWidth + Offset) * (var->yres)),
  1080. S3C_VIDW00ADD1B1+(0x08*win_num));
  1081. /* size of frame buffer */
  1082. FrameBufferSize = S3C_VIDWxxADD2_OFFSIZE_F(Offset) | (S3C_VIDWxxADD2_PAGEWIDTH_F(PageWidth));
  1083. #if defined(CONFIG_CPU_S3C2443)
  1084. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2B0+(0x08*win_num));
  1085. if(win_num==0)
  1086. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2B1);
  1087. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1088. __raw_writel(FrameBufferSize, S3C_VIDW00ADD2+(0x04*win_num));
  1089. #endif
  1090. return 0;
  1091. }
  1092. int s3c_fb_set_out_path(struct s3c_fb_info *fbi, int Path)
  1093. {
  1094. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1095. switch(Path){
  1096. case 0: // RGB I/F
  1097. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P, S3C_VIDCON0);
  1098. break;
  1099. case 1: // TV Encoder T/F
  1100. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TV, S3C_VIDCON0);
  1101. break;
  1102. case 2: // Indirect I80 I/F-0
  1103. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_I80IF0, S3C_VIDCON0);
  1104. break;
  1105. case 3: // Indirect I80 I/F-1
  1106. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_I80IF1, S3C_VIDCON0);
  1107. break;
  1108. case 4: // TV Encoder & RGB I/F
  1109. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNRGBIF, S3C_VIDCON0);
  1110. break;
  1111. case 6: // TV Encoder & Indirect I80 I/F-0
  1112. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNI80IF0, S3C_VIDCON0);
  1113. break;
  1114. case 7: // TV Encoder & Indirect I80 I/F-1
  1115. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_TVNI80IF1, S3C_VIDCON0);
  1116. break;
  1117. default: // RGB I/F
  1118. __raw_writel(__raw_readl(S3C_VIDCON0) | S3C_VIDCON0_VIDOUT_RGB_IF | S3C_VIDCON0_PNRMODE_RGB_P, S3C_VIDCON0);
  1119. break;
  1120. }
  1121. #endif
  1122. return 0;
  1123. }
  1124. #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1125. #define LCD_TV 1
  1126. // LCD display controller configuration functions
  1127. void s3c_fb_set_output_path(int out)
  1128. {
  1129. u32 tmp;
  1130. //printk("s3c_fb_set_output_path() called.\n");
  1131. tmp = __raw_readl(S3C_VIDCON0);
  1132. // if output mode is LCD mode, Scan mode always should be progressive mode
  1133. if(out == LCD_TV) {
  1134. tmp &=~(1<<29);
  1135. }
  1136. tmp &=~(0x7<<26);
  1137. tmp |= (out<<26);
  1138. __raw_writel(tmp, S3C_VIDCON0);
  1139. }
  1140. void s3c_fb_set_clkval(u32 clkval)
  1141. {
  1142. u32 tmp;
  1143. //printk("s3c_fb_set_clkval() called.\n");
  1144. tmp = __raw_readl(S3C_VIDCON0);
  1145. tmp &=~(0x1<<4);
  1146. tmp &=~(0xff<<6);
  1147. __raw_writel(tmp | (clkval<<6) | (1<<4), S3C_VIDCON0);
  1148. }
  1149. void s3c_fb_enable_rgbport(u32 on_off)
  1150. {
  1151. //printk("s3c_fb_enable_rgbport() called.\n");
  1152. if(on_off) //enable
  1153. __raw_writel(0x380, S3C_VIDCON2);
  1154. else //disable
  1155. __raw_writel(0x0, S3C_VIDCON2);
  1156. }
  1157. EXPORT_SYMBOL(s3c_fb_set_output_path);
  1158. EXPORT_SYMBOL(s3c_fb_set_clkval);
  1159. EXPORT_SYMBOL(s3c_fb_enable_rgbport);
  1160. #endif
  1161. void SetLcdPort(void)
  1162. {
  1163. unsigned long gpdat;
  1164. unsigned long gpcon;
  1165. unsigned long hclkcon; //, sclkcon;
  1166. #if defined(CONFIG_CPU_S3C2443)
  1167. //Enable clock to LCD
  1168. hclkcon = __raw_readl(S3C_HCLKCON);
  1169. hclkcon |= S3C_HCLKCON_LCD;
  1170. __raw_writel(hclkcon, S3C_HCLKCON);
  1171. // To select TFT LCD type
  1172. gpdat = __raw_readl(S3C_MISCCR);
  1173. gpdat |= (1<<28);
  1174. __raw_writel(gpdat, S3C_MISCCR);
  1175. __raw_writel(0xaaaaaaaa, S3C_GPCCON); // CTRL, VD[7:0]
  1176. __raw_writel(0xaaaaaaaa, S3C_GPDCON); // VD[23:8]
  1177. /* LCD Backlight Enable control */
  1178. gpcon = __raw_readl(S3C_GPBCON);
  1179. gpcon = (gpcon & ~(3<<6)) | (1<<6); // Backlight(GPB3) Enable control
  1180. __raw_writel(gpcon, S3C_GPBCON);
  1181. /* LCD Backlight ON */
  1182. gpdat = __raw_readl(S3C_GPBDAT);
  1183. gpdat |= (1<<3);
  1184. __raw_writel(gpdat, S3C_GPBDAT);
  1185. // LCD _nRESET control
  1186. gpcon = __raw_readl(S3C_GPBCON);
  1187. gpcon = (gpcon & ~(3<<2)) |(1<<2);
  1188. __raw_writel(gpcon, S3C_GPBCON);
  1189. gpdat = __raw_readl(S3C_GPBDAT);
  1190. gpdat |= (1<<1);
  1191. __raw_writel(gpdat, S3C_GPBDAT);
  1192. // LCD module reset
  1193. gpdat = __raw_readl(S3C_GPBDAT);
  1194. gpdat |= (1<<2);
  1195. __raw_writel(gpdat, S3C_GPBDAT);
  1196. gpdat = __raw_readl(S3C_GPBDAT);
  1197. gpdat &= ~(1<<2); // goes to LOW
  1198. __raw_writel(gpdat, S3C_GPBDAT);
  1199. mdelay(10);
  1200. gpdat = __raw_readl(S3C_GPBDAT);
  1201. gpdat |= (1<<2); // goes to HIGH
  1202. __raw_writel(gpdat, S3C_GPBDAT);
  1203. #elif defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
  1204. //Must be '0' for Normal-path instead of By-pass
  1205. // (*(volatile unsigned *)0x7410800c)=0;
  1206. __raw_writel(0x0, S3C_HOSTIFB_MIFPCON);
  1207. //Enable clock to LCD
  1208. hclkcon = __raw_readl(S3C_HCLK_GATE);
  1209. hclkcon |= S3C_CLKCON_HCLK_LCD;
  1210. __raw_writel(hclkcon, S3C_HCLK_GATE);
  1211. // To select TFT LCD type (RGB I/F)
  1212. gpdat = __raw_readl(S3C_SPCON);
  1213. gpdat &= ~0x3;
  1214. gpdat |= (1<<0);
  1215. __raw_writel(gpdat, S3C_SPCON);
  1216. __raw_writel(0xaaaaaaaa, S3C_GPICON); // VD[15:0]
  1217. __raw_writel(0xaaaaaaaa, S3C_GPJCON); // VD[23:16], Ctrl
  1218. /* PWM for back-light control */
  1219. s3c_gpio_cfgpin(S3C_GPF15, 1);
  1220. s3c_gpio_setpin(S3C_GPF15, 1);
  1221. s3c_gpio_cfgpin(S3C_GPN5, 1);
  1222. s3c_gpio_setpin(S3C_GPN5, 0);
  1223. s3c_gpio_setpin(S3C_GPN5, 1);
  1224. mdelay(100);
  1225. #if 0
  1226. /* Dummy code : remove to LCD pwm control (ryu)*/
  1227. /* LCD Backlight Enable control */
  1228. gpcon = __raw_readl(S3C_GPFCON);
  1229. gpcon = (gpcon & ~(3<<30)) | (1<<30); // Backlight(GPF15) Enable control
  1230. __raw_writel(gpcon, S3C_GPFCON);
  1231. /* LCD Backlight ON */
  1232. gpdat = __raw_readl(S3C_GPFDAT);
  1233. gpdat |= (1<<15);
  1234. __raw_writel(gpdat, S3C_GPFDAT);
  1235. #endif
  1236. // LCD _nRESET control
  1237. gpcon = __raw_readl(S3C_GPNCON);
  1238. gpcon = (gpcon & ~(3<<10)) |(1<<10);
  1239. __raw_writel(gpcon, S3C_GPNCON);
  1240. gpdat = __raw_readl(S3C_GPNDAT);
  1241. gpdat |= (0<<5);
  1242. __raw_writel(gpdat, S3C_GPNDAT);
  1243. mdelay(10);
  1244. gpdat = __raw_readl(S3C_GPNDAT);
  1245. gpdat |= (1<<5);
  1246. __raw_writel(gpdat, S3C_GPNDAT);
  1247. #endif
  1248. }
  1249. /****************************************************************************/
  1250. #define LCD_DELAY_1MS 18000
  1251. static const unsigned int lms480qc0_rgb_initialize[][3] =
  1252. {
  1253. {0x0063,0,0}, // default vlaue // set driver output 100% , hareware pin stanby
  1254. {0x0155,0,0}, // default vlaue // interlaced display mode
  1255. {0x0203,0,0}, // vertical display position setting 0x3(-13H) backporch period setting. default 0x10
  1256. {0x0311,0,0}, // horizontal display position setting 0x11(-111NCLK) default 0x80
  1257. {0x0400,0,0}, // default vlaue
  1258. {0x0511,0,0}, // default vlaue
  1259. {0x0600,0,0}, // signal polarity setting ODD/EVEN(high), CK(falling edge), HD(Low), VD(Low)
  1260. {0x0700,0,0}, // default vlaue
  1261. {0x0844,0,0}, // default vlaue
  1262. {0x0902,0,0}, // BSEQ(0x2) ODD/Even Line 1,4,2,5,3,6 ?
  1263. {0x0a2a,0,0}, // Bank Non Overlap time BNO[5:0]=0x2a(+10NCLK)
  1264. {0x0b28,0,0}, // bank switch turn on time // default 0x40
  1265. {0x0c2a,0,0}, // Gate non-overlap setting // default 0x40
  1266. {0x0d3e,0,0}, // Gate source ouput delay setting // default 0x20
  1267. {0x0e20,0,0}, // default vlaue
  1268. {0x0f20,0,0}, // default vlaue
  1269. {0x10f9,0,0}, // default 0xf0
  1270. {0x11f4,0,0}, // default 0xf4
  1271. {0x1210,0,0}, // default vlaue
  1272. {0x1320,0,0}, // default vlaue
  1273. {0x1420,0,0}, // default vlaue
  1274. {0x1520,0,0}, // default vlaue
  1275. {0x1680,0,0}, // default vlaue
  1276. {0x1780,0,0}, // default vlaue
  1277. {0x1880,0,0}, // default vlaue
  1278. {0x2086,0,0},
  1279. {0x2106,0,0},
  1280. {0x220b,0,0},
  1281. {0x2316,0,0},
  1282. {0x2458,0,0},
  1283. {0x2594,0,0},
  1284. {0x26cf,0,0},
  1285. {0x2755,0,0},
  1286. {0x28bc,0,0},
  1287. {0x2918,0,0},
  1288. {0x2a69,0,0},
  1289. {0x2bfe,0,0},
  1290. {0x2c54,0,0},
  1291. {0x2d95,0,0},
  1292. {0x2efe,0,0},
  1293. {0x5086,0,0},
  1294. {0x5106,0,0},
  1295. {0x520b,0,0},
  1296. {0x5316,0,0},
  1297. {0x5458,0,0},
  1298. {0x5594,0,0},
  1299. {0x56cf,0,0},
  1300. {0x5755,0,0},
  1301. {0x58bc,0,0},
  1302. {0x5918,0,0},
  1303. {0x5a69,0,0},
  1304. {0x5bfe,0,0},
  1305. {0x5c54,0,0},
  1306. {0x5d95,0,0},
  1307. {0x5efe,0,0},
  1308. {0x2f21,0,0},
  1309. {0,0,0}
  1310. };
  1311. static void spi_init(void)
  1312. {
  1313. spi_base = ioremap(S3C24XX_PA_SPI, S3C24XX_SZ_SPI);
  1314. s3c_gpio_cfgpin(S3C_GPC4, 2);
  1315. s3c_gpio_cfgpin(S3C_GPC5, 2);
  1316. s3c_gpio_cfgpin(S3C_GPC6, 2);
  1317. s3c_gpio_cfgpin(S3C_GPC7, 2);
  1318. s3c_gpio_pullup(S3C_GPC4, 0);
  1319. s3c_gpio_pullup(S3C_GPC5, 0);
  1320. s3c_gpio_pullup(S3C_GPC6, 0);
  1321. s3c_gpio_pullup(S3C_GPC7, 0);
  1322. writel(SPI_CH_FORMAT_B | SPI_CH_FALLING, spi_base + S3C_CH_CFG);
  1323. writel(SPI_ENCLK_ENABLE | 0xff, spi_base + S3C_CLK_CFG);
  1324. writel(0x0, spi_base + S3C_MODE_CFG);
  1325. writel(0x1, spi_base + S3C_SLAVE_SEL);
  1326. writel(0x0, spi_base + S3C_SPI_INT_EN);
  1327. }
  1328. static void spi_start(void)
  1329. {
  1330. writel(readl(spi_base + S3C_CH_CFG) | 0x1, spi_base + S3C_CH_CFG);
  1331. }
  1332. static void spi_cscontrol(int cs)
  1333. {
  1334. volatile u32 tmp;
  1335. tmp = readl(spi_base + S3C_SLAVE_SEL);
  1336. if (cs)
  1337. tmp |= 0x1;
  1338. else
  1339. tmp &= ~0x1;
  1340. writel(tmp, spi_base + S3C_SLAVE_SEL);
  1341. }
  1342. static void spi_delay_loop(u32 count)
  1343. {
  1344. u32 i;
  1345. for(i = 0; i < count; i++);
  1346. }
  1347. static void spi_delay_1ms(int msec)
  1348. {
  1349. volatile int i;
  1350. for(i = 0; i < LCD_DELAY_1MS * msec; i++);
  1351. }
  1352. static void spi_write(u8 data1, u8 data2)
  1353. {
  1354. spi_cscontrol(0);
  1355. spi_delay_loop(0xffff);
  1356. writeb(data1, spi_base + S3C_SPI_TX_DATA);
  1357. writeb(data2, spi_base + S3C_SPI_TX_DATA);
  1358. spi_delay_loop(0xffff);
  1359. spi_cscontrol(1);
  1360. spi_delay_loop(0xffff);
  1361. }
  1362. static void lti_command(u16 data)
  1363. {
  1364. spi_write((u8) ((data >> 8) & 0xff), (u8) (data & 0xff));
  1365. }
  1366. void Init_LDI(void)
  1367. {
  1368. int i;
  1369. printk(KERN_INFO "LCD TYPE :: S3C_LMS480QC LCD will be initialized\n");
  1370. SetLcdPort();
  1371. /* init & start spi */
  1372. spi_init();
  1373. spi_start();
  1374. i = 0;
  1375. while (1) {
  1376. lti_command(lms480qc0_rgb_initialize[i][0]);
  1377. if (lms480qc0_rgb_initialize[i][2])
  1378. spi_delay_1ms(lms480qc0_rgb_initialize[i][2]);
  1379. i++;
  1380. if ((lms480qc0_rgb_initialize[i][0] == 0) && (lms480qc0_rgb_initialize[i][1] == 0))
  1381. break;
  1382. }
  1383. spi_delay_1ms(1);
  1384. mdelay(100);
  1385. }