s3c2410fb.c 26 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037
  1. /*
  2. * linux/drivers/video/s3c2410fb.c
  3. * Copyright (c) Arnaud Patard, Ben Dooks
  4. *
  5. * This file is subject to the terms and conditions of the GNU General Public
  6. * License. See the file COPYING in the main directory of this archive for
  7. * more details.
  8. *
  9. * S3C2410 LCD Controller Frame Buffer Driver
  10. * based on skeletonfb.c, sa1100fb.c and others
  11. *
  12. * ChangeLog
  13. * 2005-04-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  14. * - u32 state -> pm_message_t state
  15. * - S3C2410_{VA,SZ}_LCD -> S3C24XX
  16. *
  17. * 2005-03-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  18. * - Removed the ioctl
  19. * - use readl/writel instead of __raw_writel/__raw_readl
  20. *
  21. * 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
  22. * - Added the possibility to set on or off the
  23. * debugging mesaages
  24. * - Replaced 0 and 1 by on or off when reading the
  25. * /sys files
  26. *
  27. * 2005-03-23: Ben Dooks <ben-linux@fluff.org>
  28. * - added non 16bpp modes
  29. * - updated platform information for range of x/y/bpp
  30. * - add code to ensure palette is written correctly
  31. * - add pixel clock divisor control
  32. *
  33. * 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
  34. * - Removed the use of currcon as it no more exist
  35. * - Added LCD power sysfs interface
  36. *
  37. * 2004-11-03: Ben Dooks <ben-linux@fluff.org>
  38. * - minor cleanups
  39. * - add suspend/resume support
  40. * - s3c2410fb_setcolreg() not valid in >8bpp modes
  41. * - removed last CONFIG_FB_S3C2410_FIXED
  42. * - ensure lcd controller stopped before cleanup
  43. * - added sysfs interface for backlight power
  44. * - added mask for gpio configuration
  45. * - ensured IRQs disabled during GPIO configuration
  46. * - disable TPAL before enabling video
  47. *
  48. * 2004-09-20: Arnaud Patard <arnaud.patard@rtp-net.org>
  49. * - Suppress command line options
  50. *
  51. * 2004-09-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  52. * - code cleanup
  53. *
  54. * 2004-09-07: Arnaud Patard <arnaud.patard@rtp-net.org>
  55. * - Renamed from h1940fb.c to s3c2410fb.c
  56. * - Add support for different devices
  57. * - Backlight support
  58. *
  59. * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
  60. * - added clock (de-)allocation code
  61. * - added fixem fbmem option
  62. *
  63. * 2004-07-27: Arnaud Patard <arnaud.patard@rtp-net.org>
  64. * - code cleanup
  65. * - added a forgotten return in h1940fb_init
  66. *
  67. * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
  68. * - code cleanup and extended debugging
  69. *
  70. * 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
  71. * - First version
  72. */
  73. #include <linux/module.h>
  74. #include <linux/kernel.h>
  75. #include <linux/errno.h>
  76. #include <linux/string.h>
  77. #include <linux/mm.h>
  78. #include <linux/slab.h>
  79. #include <linux/delay.h>
  80. #include <linux/fb.h>
  81. #include <linux/init.h>
  82. #include <linux/dma-mapping.h>
  83. #include <linux/interrupt.h>
  84. #include <linux/workqueue.h>
  85. #include <linux/wait.h>
  86. #include <linux/platform_device.h>
  87. #include <linux/clk.h>
  88. #include <asm/io.h>
  89. #include <asm/uaccess.h>
  90. #include <asm/div64.h>
  91. #include <asm/mach/map.h>
  92. #include <asm/arch/regs-lcd.h>
  93. #include <asm/arch/regs-gpio.h>
  94. #include <asm/arch/fb.h>
  95. #ifdef CONFIG_PM
  96. #include <linux/pm.h>
  97. #endif
  98. #include "s3c2410fb.h"
  99. static struct s3c2410fb_mach_info *mach_info;
  100. /* Debugging stuff */
  101. #ifdef CONFIG_FB_S3C2410_DEBUG
  102. static int debug = 1;
  103. #else
  104. static int debug = 0;
  105. #endif
  106. #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
  107. /* useful functions */
  108. /* s3c2410fb_set_lcdaddr
  109. *
  110. * initialise lcd controller address pointers
  111. */
  112. static void s3c2410fb_set_lcdaddr(struct s3c2410fb_info *fbi)
  113. {
  114. struct fb_var_screeninfo *var = &fbi->fb->var;
  115. unsigned long saddr1, saddr2, saddr3;
  116. saddr1 = fbi->fb->fix.smem_start >> 1;
  117. saddr2 = fbi->fb->fix.smem_start;
  118. saddr2 += (var->xres * var->yres * var->bits_per_pixel)/8;
  119. saddr2>>= 1;
  120. saddr3 = S3C2410_OFFSIZE(0) | S3C2410_PAGEWIDTH((var->xres * var->bits_per_pixel / 16) & 0x3ff);
  121. dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
  122. dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
  123. dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
  124. writel(saddr1, S3C2410_LCDSADDR1);
  125. writel(saddr2, S3C2410_LCDSADDR2);
  126. writel(saddr3, S3C2410_LCDSADDR3);
  127. }
  128. /* s3c2410fb_calc_pixclk()
  129. *
  130. * calculate divisor for clk->pixclk
  131. */
  132. static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
  133. unsigned long pixclk)
  134. {
  135. unsigned long clk = clk_get_rate(fbi->clk);
  136. unsigned long long div;
  137. /* pixclk is in picoseoncds, our clock is in Hz
  138. *
  139. * Hz -> picoseconds is / 10^-12
  140. */
  141. div = (unsigned long long)clk * pixclk;
  142. do_div(div,1000000UL);
  143. do_div(div,1000000UL);
  144. dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
  145. return div;
  146. }
  147. /*
  148. * s3c2410fb_check_var():
  149. * Get the video params out of 'var'. If a value doesn't fit, round it up,
  150. * if it's too big, return -EINVAL.
  151. *
  152. */
  153. static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
  154. struct fb_info *info)
  155. {
  156. struct s3c2410fb_info *fbi = info->par;
  157. dprintk("check_var(var=%p, info=%p)\n", var, info);
  158. /* validate x/y resolution */
  159. if (var->yres > fbi->mach_info->yres.max)
  160. var->yres = fbi->mach_info->yres.max;
  161. else if (var->yres < fbi->mach_info->yres.min)
  162. var->yres = fbi->mach_info->yres.min;
  163. if (var->xres > fbi->mach_info->xres.max)
  164. var->yres = fbi->mach_info->xres.max;
  165. else if (var->xres < fbi->mach_info->xres.min)
  166. var->xres = fbi->mach_info->xres.min;
  167. /* validate bpp */
  168. if (var->bits_per_pixel > fbi->mach_info->bpp.max)
  169. var->bits_per_pixel = fbi->mach_info->bpp.max;
  170. else if (var->bits_per_pixel < fbi->mach_info->bpp.min)
  171. var->bits_per_pixel = fbi->mach_info->bpp.min;
  172. /* set r/g/b positions */
  173. switch (var->bits_per_pixel) {
  174. case 1:
  175. case 2:
  176. case 4:
  177. var->red.offset = 0;
  178. var->red.length = var->bits_per_pixel;
  179. var->green = var->red;
  180. var->blue = var->red;
  181. var->transp.offset = 0;
  182. var->transp.length = 0;
  183. break;
  184. case 8:
  185. if ( fbi->mach_info->type != S3C2410_LCDCON1_TFT ) {
  186. /* 8 bpp 332 */
  187. var->red.length = 3;
  188. var->red.offset = 5;
  189. var->green.length = 3;
  190. var->green.offset = 2;
  191. var->blue.length = 2;
  192. var->blue.offset = 0;
  193. var->transp.length = 0;
  194. } else {
  195. var->red.offset = 0;
  196. var->red.length = var->bits_per_pixel;
  197. var->green = var->red;
  198. var->blue = var->red;
  199. var->transp.offset = 0;
  200. var->transp.length = 0;
  201. }
  202. break;
  203. case 12:
  204. /* 12 bpp 444 */
  205. var->red.length = 4;
  206. var->red.offset = 8;
  207. var->green.length = 4;
  208. var->green.offset = 4;
  209. var->blue.length = 4;
  210. var->blue.offset = 0;
  211. var->transp.length = 0;
  212. break;
  213. default:
  214. case 16:
  215. if (fbi->regs.lcdcon5 & S3C2410_LCDCON5_FRM565 ) {
  216. /* 16 bpp, 565 format */
  217. var->red.offset = 11;
  218. var->green.offset = 5;
  219. var->blue.offset = 0;
  220. var->red.length = 5;
  221. var->green.length = 6;
  222. var->blue.length = 5;
  223. var->transp.length = 0;
  224. } else {
  225. /* 16 bpp, 5551 format */
  226. var->red.offset = 11;
  227. var->green.offset = 6;
  228. var->blue.offset = 1;
  229. var->red.length = 5;
  230. var->green.length = 5;
  231. var->blue.length = 5;
  232. var->transp.length = 0;
  233. }
  234. break;
  235. case 24:
  236. /* 24 bpp 888 */
  237. var->red.length = 8;
  238. var->red.offset = 16;
  239. var->green.length = 8;
  240. var->green.offset = 8;
  241. var->blue.length = 8;
  242. var->blue.offset = 0;
  243. var->transp.length = 0;
  244. break;
  245. }
  246. return 0;
  247. }
  248. /* s3c2410fb_activate_var
  249. *
  250. * activate (set) the controller from the given framebuffer
  251. * information
  252. */
  253. static void s3c2410fb_activate_var(struct s3c2410fb_info *fbi,
  254. struct fb_var_screeninfo *var)
  255. {
  256. int hs;
  257. fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
  258. fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
  259. dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
  260. dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
  261. dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
  262. fbi->regs.lcdcon1 |= fbi->mach_info->type;
  263. if (fbi->mach_info->type == S3C2410_LCDCON1_TFT)
  264. switch (var->bits_per_pixel) {
  265. case 1:
  266. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
  267. break;
  268. case 2:
  269. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
  270. break;
  271. case 4:
  272. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
  273. break;
  274. case 8:
  275. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
  276. break;
  277. case 16:
  278. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
  279. break;
  280. default:
  281. /* invalid pixel depth */
  282. dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel);
  283. }
  284. else
  285. switch (var->bits_per_pixel) {
  286. case 1:
  287. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
  288. break;
  289. case 2:
  290. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
  291. break;
  292. case 4:
  293. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
  294. break;
  295. case 8:
  296. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
  297. break;
  298. case 12:
  299. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
  300. break;
  301. default:
  302. /* invalid pixel depth */
  303. dev_err(fbi->dev, "invalid bpp %d\n", var->bits_per_pixel);
  304. }
  305. /* check to see if we need to update sync/borders */
  306. if (!fbi->mach_info->fixed_syncs) {
  307. dprintk("setting vert: up=%d, low=%d, sync=%d\n",
  308. var->upper_margin, var->lower_margin,
  309. var->vsync_len);
  310. dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
  311. var->left_margin, var->right_margin,
  312. var->hsync_len);
  313. fbi->regs.lcdcon2 =
  314. S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
  315. S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
  316. S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
  317. fbi->regs.lcdcon3 =
  318. S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
  319. S3C2410_LCDCON3_HFPD(var->left_margin - 1);
  320. fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
  321. fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
  322. }
  323. /* update X/Y info */
  324. fbi->regs.lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
  325. fbi->regs.lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
  326. switch(fbi->mach_info->type) {
  327. case S3C2410_LCDCON1_DSCAN4:
  328. case S3C2410_LCDCON1_STN8:
  329. hs = var->xres / 8;
  330. break;
  331. case S3C2410_LCDCON1_STN4:
  332. hs = var->xres / 4;
  333. break;
  334. default:
  335. case S3C2410_LCDCON1_TFT:
  336. hs = var->xres;
  337. break;
  338. }
  339. /* Special cases : STN color displays */
  340. if ( ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN8BPP) \
  341. || ((fbi->regs.lcdcon1 & S3C2410_LCDCON1_MODEMASK) == S3C2410_LCDCON1_STN12BPP) ) {
  342. hs = hs * 3;
  343. }
  344. fbi->regs.lcdcon3 &= ~S3C2410_LCDCON3_HOZVAL(0x7ff);
  345. fbi->regs.lcdcon3 |= S3C2410_LCDCON3_HOZVAL(hs - 1);
  346. if (var->pixclock > 0) {
  347. int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
  348. if (fbi->mach_info->type == S3C2410_LCDCON1_TFT) {
  349. clkdiv = (clkdiv / 2) -1;
  350. if (clkdiv < 0)
  351. clkdiv = 0;
  352. }
  353. else {
  354. clkdiv = (clkdiv / 2);
  355. if (clkdiv < 2)
  356. clkdiv = 2;
  357. }
  358. fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
  359. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
  360. }
  361. /* write new registers */
  362. dprintk("new register set:\n");
  363. dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
  364. dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
  365. dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
  366. dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
  367. dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
  368. writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
  369. writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
  370. writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
  371. writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
  372. writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
  373. /* set lcd address pointers */
  374. s3c2410fb_set_lcdaddr(fbi);
  375. writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
  376. }
  377. /*
  378. * s3c2410fb_set_par - Optional function. Alters the hardware state.
  379. * @info: frame buffer structure that represents a single frame buffer
  380. *
  381. */
  382. static int s3c2410fb_set_par(struct fb_info *info)
  383. {
  384. struct s3c2410fb_info *fbi = info->par;
  385. struct fb_var_screeninfo *var = &info->var;
  386. switch (var->bits_per_pixel)
  387. {
  388. case 16:
  389. fbi->fb->fix.visual = FB_VISUAL_TRUECOLOR;
  390. break;
  391. case 1:
  392. fbi->fb->fix.visual = FB_VISUAL_MONO01;
  393. break;
  394. default:
  395. fbi->fb->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  396. break;
  397. }
  398. fbi->fb->fix.line_length = (var->width*var->bits_per_pixel)/8;
  399. /* activate this new configuration */
  400. s3c2410fb_activate_var(fbi, var);
  401. return 0;
  402. }
  403. static void schedule_palette_update(struct s3c2410fb_info *fbi,
  404. unsigned int regno, unsigned int val)
  405. {
  406. unsigned long flags;
  407. unsigned long irqen;
  408. local_irq_save(flags);
  409. fbi->palette_buffer[regno] = val;
  410. if (!fbi->palette_ready) {
  411. fbi->palette_ready = 1;
  412. /* enable IRQ */
  413. irqen = readl(S3C2410_LCDINTMSK);
  414. irqen &= ~S3C2410_LCDINT_FRSYNC;
  415. writel(irqen, S3C2410_LCDINTMSK);
  416. }
  417. local_irq_restore(flags);
  418. }
  419. /* from pxafb.c */
  420. static inline unsigned int chan_to_field(unsigned int chan, struct fb_bitfield *bf)
  421. {
  422. chan &= 0xffff;
  423. chan >>= 16 - bf->length;
  424. return chan << bf->offset;
  425. }
  426. static int s3c2410fb_setcolreg(unsigned regno,
  427. unsigned red, unsigned green, unsigned blue,
  428. unsigned transp, struct fb_info *info)
  429. {
  430. struct s3c2410fb_info *fbi = info->par;
  431. unsigned int val;
  432. /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n", regno, red, green, blue); */
  433. switch (fbi->fb->fix.visual) {
  434. case FB_VISUAL_TRUECOLOR:
  435. /* true-colour, use pseuo-palette */
  436. if (regno < 16) {
  437. u32 *pal = fbi->fb->pseudo_palette;
  438. val = chan_to_field(red, &fbi->fb->var.red);
  439. val |= chan_to_field(green, &fbi->fb->var.green);
  440. val |= chan_to_field(blue, &fbi->fb->var.blue);
  441. pal[regno] = val;
  442. }
  443. break;
  444. case FB_VISUAL_PSEUDOCOLOR:
  445. if (regno < 256) {
  446. /* currently assume RGB 5-6-5 mode */
  447. val = ((red >> 0) & 0xf800);
  448. val |= ((green >> 5) & 0x07e0);
  449. val |= ((blue >> 11) & 0x001f);
  450. writel(val, S3C2410_TFTPAL(regno));
  451. schedule_palette_update(fbi, regno, val);
  452. }
  453. break;
  454. default:
  455. return 1; /* unknown type */
  456. }
  457. return 0;
  458. }
  459. /**
  460. * s3c2410fb_blank
  461. * @blank_mode: the blank mode we want.
  462. * @info: frame buffer structure that represents a single frame buffer
  463. *
  464. * Blank the screen if blank_mode != 0, else unblank. Return 0 if
  465. * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
  466. * video mode which doesn't support it. Implements VESA suspend
  467. * and powerdown modes on hardware that supports disabling hsync/vsync:
  468. * blank_mode == 2: suspend vsync
  469. * blank_mode == 3: suspend hsync
  470. * blank_mode == 4: powerdown
  471. *
  472. * Returns negative errno on error, or zero on success.
  473. *
  474. */
  475. static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
  476. {
  477. dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
  478. if (mach_info == NULL)
  479. return -EINVAL;
  480. if (blank_mode == FB_BLANK_UNBLANK)
  481. writel(0x0, S3C2410_TPAL);
  482. else {
  483. dprintk("setting TPAL to output 0x000000\n");
  484. writel(S3C2410_TPAL_EN, S3C2410_TPAL);
  485. }
  486. return 0;
  487. }
  488. static int s3c2410fb_debug_show(struct device *dev, struct device_attribute *attr, char *buf)
  489. {
  490. return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
  491. }
  492. static int s3c2410fb_debug_store(struct device *dev, struct device_attribute *attr,
  493. const char *buf, size_t len)
  494. {
  495. if (mach_info == NULL)
  496. return -EINVAL;
  497. if (len < 1)
  498. return -EINVAL;
  499. if (strnicmp(buf, "on", 2) == 0 ||
  500. strnicmp(buf, "1", 1) == 0) {
  501. debug = 1;
  502. printk(KERN_DEBUG "s3c2410fb: Debug On");
  503. } else if (strnicmp(buf, "off", 3) == 0 ||
  504. strnicmp(buf, "0", 1) == 0) {
  505. debug = 0;
  506. printk(KERN_DEBUG "s3c2410fb: Debug Off");
  507. } else {
  508. return -EINVAL;
  509. }
  510. return len;
  511. }
  512. static DEVICE_ATTR(debug, 0666,
  513. s3c2410fb_debug_show,
  514. s3c2410fb_debug_store);
  515. static struct fb_ops s3c2410fb_ops = {
  516. .owner = THIS_MODULE,
  517. .fb_check_var = s3c2410fb_check_var,
  518. .fb_set_par = s3c2410fb_set_par,
  519. .fb_blank = s3c2410fb_blank,
  520. .fb_setcolreg = s3c2410fb_setcolreg,
  521. .fb_fillrect = cfb_fillrect,
  522. .fb_copyarea = cfb_copyarea,
  523. .fb_imageblit = cfb_imageblit,
  524. };
  525. /*
  526. * s3c2410fb_map_video_memory():
  527. * Allocates the DRAM memory for the frame buffer. This buffer is
  528. * remapped into a non-cached, non-buffered, memory region to
  529. * allow palette and pixel writes to occur without flushing the
  530. * cache. Once this area is remapped, all virtual memory
  531. * access to the video memory should occur at the new region.
  532. */
  533. static int __init s3c2410fb_map_video_memory(struct s3c2410fb_info *fbi)
  534. {
  535. dprintk("map_video_memory(fbi=%p)\n", fbi);
  536. fbi->map_size = PAGE_ALIGN(fbi->fb->fix.smem_len + PAGE_SIZE);
  537. fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
  538. &fbi->map_dma, GFP_KERNEL);
  539. fbi->map_size = fbi->fb->fix.smem_len;
  540. if (fbi->map_cpu) {
  541. /* prevent initial garbage on screen */
  542. dprintk("map_video_memory: clear %p:%08x\n",
  543. fbi->map_cpu, fbi->map_size);
  544. memset(fbi->map_cpu, 0xf0, fbi->map_size);
  545. fbi->screen_dma = fbi->map_dma;
  546. fbi->fb->screen_base = fbi->map_cpu;
  547. fbi->fb->fix.smem_start = fbi->screen_dma;
  548. dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
  549. fbi->map_dma, fbi->map_cpu, fbi->fb->fix.smem_len);
  550. }
  551. return fbi->map_cpu ? 0 : -ENOMEM;
  552. }
  553. static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
  554. {
  555. dma_free_writecombine(fbi->dev,fbi->map_size,fbi->map_cpu, fbi->map_dma);
  556. }
  557. static inline void modify_gpio(void __iomem *reg,
  558. unsigned long set, unsigned long mask)
  559. {
  560. unsigned long tmp;
  561. tmp = readl(reg) & ~mask;
  562. writel(tmp | set, reg);
  563. }
  564. /*
  565. * s3c2410fb_init_registers - Initialise all LCD-related registers
  566. */
  567. static int s3c2410fb_init_registers(struct s3c2410fb_info *fbi)
  568. {
  569. unsigned long flags;
  570. /* Initialise LCD with values from haret */
  571. local_irq_save(flags);
  572. /* modify the gpio(s) with interrupts set (bjd) */
  573. modify_gpio(S3C2410_GPCUP, mach_info->gpcup, mach_info->gpcup_mask);
  574. modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
  575. modify_gpio(S3C2410_GPDUP, mach_info->gpdup, mach_info->gpdup_mask);
  576. modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
  577. local_irq_restore(flags);
  578. writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
  579. writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
  580. writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
  581. writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
  582. writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
  583. s3c2410fb_set_lcdaddr(fbi);
  584. dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
  585. writel(mach_info->lpcsel, S3C2410_LPCSEL);
  586. dprintk("replacing TPAL %08x\n", readl(S3C2410_TPAL));
  587. /* ensure temporary palette disabled */
  588. writel(0x00, S3C2410_TPAL);
  589. /* Enable video by setting the ENVID bit to 1 */
  590. fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
  591. writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
  592. return 0;
  593. }
  594. static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
  595. {
  596. unsigned int i;
  597. unsigned long ent;
  598. fbi->palette_ready = 0;
  599. for (i = 0; i < 256; i++) {
  600. if ((ent = fbi->palette_buffer[i]) == PALETTE_BUFF_CLEAR)
  601. continue;
  602. writel(ent, S3C2410_TFTPAL(i));
  603. /* it seems the only way to know exactly
  604. * if the palette wrote ok, is to check
  605. * to see if the value verifies ok
  606. */
  607. if (readw(S3C2410_TFTPAL(i)) == ent)
  608. fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
  609. else
  610. fbi->palette_ready = 1; /* retry */
  611. }
  612. }
  613. static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
  614. {
  615. struct s3c2410fb_info *fbi = dev_id;
  616. unsigned long lcdirq = readl(S3C2410_LCDINTPND);
  617. if (lcdirq & S3C2410_LCDINT_FRSYNC) {
  618. if (fbi->palette_ready)
  619. s3c2410fb_write_palette(fbi);
  620. writel(S3C2410_LCDINT_FRSYNC, S3C2410_LCDINTPND);
  621. writel(S3C2410_LCDINT_FRSYNC, S3C2410_LCDSRCPND);
  622. }
  623. return IRQ_HANDLED;
  624. }
  625. static char driver_name[]="s3c2410fb";
  626. static int __init s3c2410fb_probe(struct platform_device *pdev)
  627. {
  628. struct s3c2410fb_info *info;
  629. struct fb_info *fbinfo;
  630. struct s3c2410fb_hw *mregs;
  631. int ret;
  632. int irq;
  633. int i;
  634. u32 lcdcon1;
  635. mach_info = pdev->dev.platform_data;
  636. if (mach_info == NULL) {
  637. dev_err(&pdev->dev,"no platform data for lcd, cannot attach\n");
  638. return -EINVAL;
  639. }
  640. mregs = &mach_info->regs;
  641. irq = platform_get_irq(pdev, 0);
  642. if (irq < 0) {
  643. dev_err(&pdev->dev, "no irq for device\n");
  644. return -ENOENT;
  645. }
  646. fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
  647. if (!fbinfo) {
  648. return -ENOMEM;
  649. }
  650. info = fbinfo->par;
  651. info->fb = fbinfo;
  652. info->dev = &pdev->dev;
  653. platform_set_drvdata(pdev, fbinfo);
  654. dprintk("devinit\n");
  655. strcpy(fbinfo->fix.id, driver_name);
  656. memcpy(&info->regs, &mach_info->regs, sizeof(info->regs));
  657. /* Stop the video and unset ENVID if set */
  658. info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
  659. lcdcon1 = readl(S3C2410_LCDCON1);
  660. writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
  661. info->mach_info = pdev->dev.platform_data;
  662. fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
  663. fbinfo->fix.type_aux = 0;
  664. fbinfo->fix.xpanstep = 0;
  665. fbinfo->fix.ypanstep = 0;
  666. fbinfo->fix.ywrapstep = 0;
  667. fbinfo->fix.accel = FB_ACCEL_NONE;
  668. fbinfo->var.nonstd = 0;
  669. fbinfo->var.activate = FB_ACTIVATE_NOW;
  670. fbinfo->var.height = mach_info->height;
  671. fbinfo->var.width = mach_info->width;
  672. fbinfo->var.accel_flags = 0;
  673. fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
  674. fbinfo->fbops = &s3c2410fb_ops;
  675. fbinfo->flags = FBINFO_FLAG_DEFAULT;
  676. fbinfo->pseudo_palette = &info->pseudo_pal;
  677. fbinfo->var.xres = mach_info->xres.defval;
  678. fbinfo->var.xres_virtual = mach_info->xres.defval;
  679. fbinfo->var.yres = mach_info->yres.defval;
  680. fbinfo->var.yres_virtual = mach_info->yres.defval;
  681. fbinfo->var.bits_per_pixel = mach_info->bpp.defval;
  682. fbinfo->var.upper_margin = S3C2410_LCDCON2_GET_VBPD(mregs->lcdcon2) + 1;
  683. fbinfo->var.lower_margin = S3C2410_LCDCON2_GET_VFPD(mregs->lcdcon2) + 1;
  684. fbinfo->var.vsync_len = S3C2410_LCDCON2_GET_VSPW(mregs->lcdcon2) + 1;
  685. fbinfo->var.left_margin = S3C2410_LCDCON3_GET_HFPD(mregs->lcdcon3) + 1;
  686. fbinfo->var.right_margin = S3C2410_LCDCON3_GET_HBPD(mregs->lcdcon3) + 1;
  687. fbinfo->var.hsync_len = S3C2410_LCDCON4_GET_HSPW(mregs->lcdcon4) + 1;
  688. fbinfo->var.red.offset = 11;
  689. fbinfo->var.green.offset = 5;
  690. fbinfo->var.blue.offset = 0;
  691. fbinfo->var.transp.offset = 0;
  692. fbinfo->var.red.length = 5;
  693. fbinfo->var.green.length = 6;
  694. fbinfo->var.blue.length = 5;
  695. fbinfo->var.transp.length = 0;
  696. fbinfo->fix.smem_len = mach_info->xres.max *
  697. mach_info->yres.max *
  698. mach_info->bpp.max / 8;
  699. for (i = 0; i < 256; i++)
  700. info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
  701. if (!request_mem_region((unsigned long)S3C24XX_VA_LCD, SZ_1M, "s3c2410-lcd")) {
  702. ret = -EBUSY;
  703. goto dealloc_fb;
  704. }
  705. dprintk("got LCD region\n");
  706. ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
  707. if (ret) {
  708. dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
  709. ret = -EBUSY;
  710. goto release_mem;
  711. }
  712. info->clk = clk_get(NULL, "lcd");
  713. if (!info->clk || IS_ERR(info->clk)) {
  714. printk(KERN_ERR "failed to get lcd clock source\n");
  715. ret = -ENOENT;
  716. goto release_irq;
  717. }
  718. clk_enable(info->clk);
  719. dprintk("got and enabled clock\n");
  720. msleep(1);
  721. /* Initialize video memory */
  722. ret = s3c2410fb_map_video_memory(info);
  723. if (ret) {
  724. printk( KERN_ERR "Failed to allocate video RAM: %d\n", ret);
  725. ret = -ENOMEM;
  726. goto release_clock;
  727. }
  728. dprintk("got video memory\n");
  729. ret = s3c2410fb_init_registers(info);
  730. ret = s3c2410fb_check_var(&fbinfo->var, fbinfo);
  731. ret = register_framebuffer(fbinfo);
  732. if (ret < 0) {
  733. printk(KERN_ERR "Failed to register framebuffer device: %d\n", ret);
  734. goto free_video_memory;
  735. }
  736. /* create device files */
  737. device_create_file(&pdev->dev, &dev_attr_debug);
  738. printk(KERN_INFO "fb%d: %s frame buffer device\n",
  739. fbinfo->node, fbinfo->fix.id);
  740. return 0;
  741. free_video_memory:
  742. s3c2410fb_unmap_video_memory(info);
  743. release_clock:
  744. clk_disable(info->clk);
  745. clk_put(info->clk);
  746. release_irq:
  747. free_irq(irq,info);
  748. release_mem:
  749. release_mem_region((unsigned long)S3C24XX_VA_LCD, S3C24XX_SZ_LCD);
  750. dealloc_fb:
  751. framebuffer_release(fbinfo);
  752. return ret;
  753. }
  754. /* s3c2410fb_stop_lcd
  755. *
  756. * shutdown the lcd controller
  757. */
  758. static void s3c2410fb_stop_lcd(struct s3c2410fb_info *fbi)
  759. {
  760. unsigned long flags;
  761. local_irq_save(flags);
  762. fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
  763. writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
  764. local_irq_restore(flags);
  765. }
  766. /*
  767. * Cleanup
  768. */
  769. static int s3c2410fb_remove(struct platform_device *pdev)
  770. {
  771. struct fb_info *fbinfo = platform_get_drvdata(pdev);
  772. struct s3c2410fb_info *info = fbinfo->par;
  773. int irq;
  774. s3c2410fb_stop_lcd(info);
  775. msleep(1);
  776. s3c2410fb_unmap_video_memory(info);
  777. if (info->clk) {
  778. clk_disable(info->clk);
  779. clk_put(info->clk);
  780. info->clk = NULL;
  781. }
  782. irq = platform_get_irq(pdev, 0);
  783. free_irq(irq,info);
  784. release_mem_region((unsigned long)S3C24XX_VA_LCD, S3C24XX_SZ_LCD);
  785. unregister_framebuffer(fbinfo);
  786. return 0;
  787. }
  788. #ifdef CONFIG_PM
  789. /* suspend and resume support for the lcd controller */
  790. static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
  791. {
  792. struct fb_info *fbinfo = platform_get_drvdata(dev);
  793. struct s3c2410fb_info *info = fbinfo->par;
  794. s3c2410fb_stop_lcd(info);
  795. /* sleep before disabling the clock, we need to ensure
  796. * the LCD DMA engine is not going to get back on the bus
  797. * before the clock goes off again (bjd) */
  798. msleep(1);
  799. clk_disable(info->clk);
  800. return 0;
  801. }
  802. static int s3c2410fb_resume(struct platform_device *dev)
  803. {
  804. struct fb_info *fbinfo = platform_get_drvdata(dev);
  805. struct s3c2410fb_info *info = fbinfo->par;
  806. clk_enable(info->clk);
  807. msleep(1);
  808. s3c2410fb_init_registers(info);
  809. return 0;
  810. }
  811. #else
  812. #define s3c2410fb_suspend NULL
  813. #define s3c2410fb_resume NULL
  814. #endif
  815. static struct platform_driver s3c2410fb_driver = {
  816. .probe = s3c2410fb_probe,
  817. .remove = s3c2410fb_remove,
  818. .suspend = s3c2410fb_suspend,
  819. .resume = s3c2410fb_resume,
  820. .driver = {
  821. .name = "s3c2410-lcd",
  822. .owner = THIS_MODULE,
  823. },
  824. };
  825. int __devinit s3c2410fb_init(void)
  826. {
  827. return platform_driver_register(&s3c2410fb_driver);
  828. }
  829. static void __exit s3c2410fb_cleanup(void)
  830. {
  831. platform_driver_unregister(&s3c2410fb_driver);
  832. }
  833. module_init(s3c2410fb_init);
  834. module_exit(s3c2410fb_cleanup);
  835. MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, Ben Dooks <ben-linux@fluff.org>");
  836. MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
  837. MODULE_LICENSE("GPL");