s1d13xxxfb.c 20 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775
  1. /* drivers/video/s1d13xxxfb.c
  2. *
  3. * (c) 2004 Simtec Electronics
  4. * (c) 2005 Thibaut VARENE <varenet@parisc-linux.org>
  5. *
  6. * Driver for Epson S1D13xxx series framebuffer chips
  7. *
  8. * Adapted from
  9. * linux/drivers/video/skeletonfb.c
  10. * linux/drivers/video/epson1355fb.c
  11. * linux/drivers/video/epson/s1d13xxxfb.c (2.4 driver by Epson)
  12. *
  13. * Note, currently only tested on S1D13806 with 16bit CRT.
  14. * As such, this driver might still contain some hardcoded bits relating to
  15. * S1D13806.
  16. * Making it work on other S1D13XXX chips should merely be a matter of adding
  17. * a few switch()s, some missing glue here and there maybe, and split header
  18. * files.
  19. *
  20. * TODO: - handle dual screen display (CRT and LCD at the same time).
  21. * - check_var(), mode change, etc.
  22. * - PM untested.
  23. * - Accelerated interfaces.
  24. * - Probably not SMP safe :)
  25. *
  26. * This file is subject to the terms and conditions of the GNU General Public
  27. * License. See the file COPYING in the main directory of this archive for
  28. * more details.
  29. */
  30. #include <linux/module.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/delay.h>
  33. #include <linux/types.h>
  34. #include <linux/errno.h>
  35. #include <linux/mm.h>
  36. #include <linux/mman.h>
  37. #include <linux/fb.h>
  38. #include <asm/io.h>
  39. #include <video/s1d13xxxfb.h>
  40. #define PFX "s1d13xxxfb: "
  41. #if 0
  42. #define dbg(fmt, args...) do { printk(KERN_INFO fmt, ## args); } while(0)
  43. #else
  44. #define dbg(fmt, args...) do { } while (0)
  45. #endif
  46. /*
  47. * Here we define the default struct fb_fix_screeninfo
  48. */
  49. static struct fb_fix_screeninfo __devinitdata s1d13xxxfb_fix = {
  50. .id = S1D_FBID,
  51. .type = FB_TYPE_PACKED_PIXELS,
  52. .visual = FB_VISUAL_PSEUDOCOLOR,
  53. .xpanstep = 0,
  54. .ypanstep = 1,
  55. .ywrapstep = 0,
  56. .accel = FB_ACCEL_NONE,
  57. };
  58. static inline u8
  59. s1d13xxxfb_readreg(struct s1d13xxxfb_par *par, u16 regno)
  60. {
  61. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
  62. regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
  63. #endif
  64. return readb(par->regs + regno);
  65. }
  66. static inline void
  67. s1d13xxxfb_writereg(struct s1d13xxxfb_par *par, u16 regno, u8 value)
  68. {
  69. #if defined(CONFIG_PLAT_M32700UT) || defined(CONFIG_PLAT_OPSPUT) || defined(CONFIG_PLAT_MAPPI3)
  70. regno=((regno & 1) ? (regno & ~1L) : (regno + 1));
  71. #endif
  72. writeb(value, par->regs + regno);
  73. }
  74. static inline void
  75. s1d13xxxfb_runinit(struct s1d13xxxfb_par *par,
  76. const struct s1d13xxxfb_regval *initregs,
  77. const unsigned int size)
  78. {
  79. int i;
  80. for (i = 0; i < size; i++) {
  81. if ((initregs[i].addr == S1DREG_DELAYOFF) ||
  82. (initregs[i].addr == S1DREG_DELAYON))
  83. mdelay((int)initregs[i].value);
  84. else {
  85. s1d13xxxfb_writereg(par, initregs[i].addr, initregs[i].value);
  86. }
  87. }
  88. /* make sure the hardware can cope with us */
  89. mdelay(1);
  90. }
  91. static inline void
  92. lcd_enable(struct s1d13xxxfb_par *par, int enable)
  93. {
  94. u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
  95. if (enable)
  96. mode |= 0x01;
  97. else
  98. mode &= ~0x01;
  99. s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
  100. }
  101. static inline void
  102. crt_enable(struct s1d13xxxfb_par *par, int enable)
  103. {
  104. u8 mode = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
  105. if (enable)
  106. mode |= 0x02;
  107. else
  108. mode &= ~0x02;
  109. s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, mode);
  110. }
  111. /* framebuffer control routines */
  112. static inline void
  113. s1d13xxxfb_setup_pseudocolour(struct fb_info *info)
  114. {
  115. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  116. info->var.red.length = 4;
  117. info->var.green.length = 4;
  118. info->var.blue.length = 4;
  119. }
  120. static inline void
  121. s1d13xxxfb_setup_truecolour(struct fb_info *info)
  122. {
  123. info->fix.visual = FB_VISUAL_TRUECOLOR;
  124. info->var.bits_per_pixel = 16;
  125. info->var.red.length = 5;
  126. info->var.red.offset = 11;
  127. info->var.green.length = 6;
  128. info->var.green.offset = 5;
  129. info->var.blue.length = 5;
  130. info->var.blue.offset = 0;
  131. }
  132. /**
  133. * s1d13xxxfb_set_par - Alters the hardware state.
  134. * @info: frame buffer structure
  135. *
  136. * Using the fb_var_screeninfo in fb_info we set the depth of the
  137. * framebuffer. This function alters the par AND the
  138. * fb_fix_screeninfo stored in fb_info. It doesn't not alter var in
  139. * fb_info since we are using that data. This means we depend on the
  140. * data in var inside fb_info to be supported by the hardware.
  141. * xxxfb_check_var is always called before xxxfb_set_par to ensure this.
  142. *
  143. * XXX TODO: write proper s1d13xxxfb_check_var(), without which that
  144. * function is quite useless.
  145. */
  146. static int
  147. s1d13xxxfb_set_par(struct fb_info *info)
  148. {
  149. struct s1d13xxxfb_par *s1dfb = info->par;
  150. unsigned int val;
  151. dbg("s1d13xxxfb_set_par: bpp=%d\n", info->var.bits_per_pixel);
  152. if ((s1dfb->display & 0x01)) /* LCD */
  153. val = s1d13xxxfb_readreg(s1dfb, S1DREG_LCD_DISP_MODE); /* read colour control */
  154. else /* CRT */
  155. val = s1d13xxxfb_readreg(s1dfb, S1DREG_CRT_DISP_MODE); /* read colour control */
  156. val &= ~0x07;
  157. switch (info->var.bits_per_pixel) {
  158. case 4:
  159. dbg("pseudo colour 4\n");
  160. s1d13xxxfb_setup_pseudocolour(info);
  161. val |= 2;
  162. break;
  163. case 8:
  164. dbg("pseudo colour 8\n");
  165. s1d13xxxfb_setup_pseudocolour(info);
  166. val |= 3;
  167. break;
  168. case 16:
  169. dbg("true colour\n");
  170. s1d13xxxfb_setup_truecolour(info);
  171. val |= 5;
  172. break;
  173. default:
  174. dbg("bpp not supported!\n");
  175. return -EINVAL;
  176. }
  177. dbg("writing %02x to display mode register\n", val);
  178. if ((s1dfb->display & 0x01)) /* LCD */
  179. s1d13xxxfb_writereg(s1dfb, S1DREG_LCD_DISP_MODE, val);
  180. else /* CRT */
  181. s1d13xxxfb_writereg(s1dfb, S1DREG_CRT_DISP_MODE, val);
  182. info->fix.line_length = info->var.xres * info->var.bits_per_pixel;
  183. info->fix.line_length /= 8;
  184. dbg("setting line_length to %d\n", info->fix.line_length);
  185. dbg("done setup\n");
  186. return 0;
  187. }
  188. /**
  189. * s1d13xxxfb_setcolreg - sets a color register.
  190. * @regno: Which register in the CLUT we are programming
  191. * @red: The red value which can be up to 16 bits wide
  192. * @green: The green value which can be up to 16 bits wide
  193. * @blue: The blue value which can be up to 16 bits wide.
  194. * @transp: If supported the alpha value which can be up to 16 bits wide.
  195. * @info: frame buffer info structure
  196. *
  197. * Returns negative errno on error, or zero on success.
  198. */
  199. static int
  200. s1d13xxxfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  201. u_int transp, struct fb_info *info)
  202. {
  203. struct s1d13xxxfb_par *s1dfb = info->par;
  204. unsigned int pseudo_val;
  205. if (regno >= S1D_PALETTE_SIZE)
  206. return -EINVAL;
  207. dbg("s1d13xxxfb_setcolreg: %d: rgb=%d,%d,%d, tr=%d\n",
  208. regno, red, green, blue, transp);
  209. if (info->var.grayscale)
  210. red = green = blue = (19595*red + 38470*green + 7471*blue) >> 16;
  211. switch (info->fix.visual) {
  212. case FB_VISUAL_TRUECOLOR:
  213. if (regno >= 16)
  214. return -EINVAL;
  215. /* deal with creating pseudo-palette entries */
  216. pseudo_val = (red >> 11) << info->var.red.offset;
  217. pseudo_val |= (green >> 10) << info->var.green.offset;
  218. pseudo_val |= (blue >> 11) << info->var.blue.offset;
  219. dbg("s1d13xxxfb_setcolreg: pseudo %d, val %08x\n",
  220. regno, pseudo_val);
  221. #if defined(CONFIG_PLAT_MAPPI)
  222. ((u32 *)info->pseudo_palette)[regno] = cpu_to_le16(pseudo_val);
  223. #else
  224. ((u32 *)info->pseudo_palette)[regno] = pseudo_val;
  225. #endif
  226. break;
  227. case FB_VISUAL_PSEUDOCOLOR:
  228. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_ADDR, regno);
  229. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, red);
  230. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, green);
  231. s1d13xxxfb_writereg(s1dfb, S1DREG_LKUP_DATA, blue);
  232. break;
  233. default:
  234. return -ENOSYS;
  235. }
  236. dbg("s1d13xxxfb_setcolreg: done\n");
  237. return 0;
  238. }
  239. /**
  240. * s1d13xxxfb_blank - blanks the display.
  241. * @blank_mode: the blank mode we want.
  242. * @info: frame buffer structure that represents a single frame buffer
  243. *
  244. * Blank the screen if blank_mode != 0, else unblank. Return 0 if
  245. * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
  246. * video mode which doesn't support it. Implements VESA suspend
  247. * and powerdown modes on hardware that supports disabling hsync/vsync:
  248. * blank_mode == 2: suspend vsync
  249. * blank_mode == 3: suspend hsync
  250. * blank_mode == 4: powerdown
  251. *
  252. * Returns negative errno on error, or zero on success.
  253. */
  254. static int
  255. s1d13xxxfb_blank(int blank_mode, struct fb_info *info)
  256. {
  257. struct s1d13xxxfb_par *par = info->par;
  258. dbg("s1d13xxxfb_blank: blank=%d, info=%p\n", blank_mode, info);
  259. switch (blank_mode) {
  260. case FB_BLANK_UNBLANK:
  261. case FB_BLANK_NORMAL:
  262. if ((par->display & 0x01) != 0)
  263. lcd_enable(par, 1);
  264. if ((par->display & 0x02) != 0)
  265. crt_enable(par, 1);
  266. break;
  267. case FB_BLANK_VSYNC_SUSPEND:
  268. case FB_BLANK_HSYNC_SUSPEND:
  269. break;
  270. case FB_BLANK_POWERDOWN:
  271. lcd_enable(par, 0);
  272. crt_enable(par, 0);
  273. break;
  274. default:
  275. return -EINVAL;
  276. }
  277. /* let fbcon do a soft blank for us */
  278. return ((blank_mode == FB_BLANK_NORMAL) ? 1 : 0);
  279. }
  280. /**
  281. * s1d13xxxfb_pan_display - Pans the display.
  282. * @var: frame buffer variable screen structure
  283. * @info: frame buffer structure that represents a single frame buffer
  284. *
  285. * Pan (or wrap, depending on the `vmode' field) the display using the
  286. * `yoffset' field of the `var' structure (`xoffset' not yet supported).
  287. * If the values don't fit, return -EINVAL.
  288. *
  289. * Returns negative errno on error, or zero on success.
  290. */
  291. static int
  292. s1d13xxxfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  293. {
  294. struct s1d13xxxfb_par *par = info->par;
  295. u32 start;
  296. if (var->xoffset != 0) /* not yet ... */
  297. return -EINVAL;
  298. if (var->yoffset + info->var.yres > info->var.yres_virtual)
  299. return -EINVAL;
  300. start = (info->fix.line_length >> 1) * var->yoffset;
  301. if ((par->display & 0x01)) {
  302. /* LCD */
  303. s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START0, (start & 0xff));
  304. s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START1, ((start >> 8) & 0xff));
  305. s1d13xxxfb_writereg(par, S1DREG_LCD_DISP_START2, ((start >> 16) & 0x0f));
  306. } else {
  307. /* CRT */
  308. s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START0, (start & 0xff));
  309. s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START1, ((start >> 8) & 0xff));
  310. s1d13xxxfb_writereg(par, S1DREG_CRT_DISP_START2, ((start >> 16) & 0x0f));
  311. }
  312. return 0;
  313. }
  314. /* framebuffer information structures */
  315. static struct fb_ops s1d13xxxfb_fbops = {
  316. .owner = THIS_MODULE,
  317. .fb_set_par = s1d13xxxfb_set_par,
  318. .fb_setcolreg = s1d13xxxfb_setcolreg,
  319. .fb_blank = s1d13xxxfb_blank,
  320. .fb_pan_display = s1d13xxxfb_pan_display,
  321. /* to be replaced by any acceleration we can */
  322. .fb_fillrect = cfb_fillrect,
  323. .fb_copyarea = cfb_copyarea,
  324. .fb_imageblit = cfb_imageblit,
  325. };
  326. static int s1d13xxxfb_width_tab[2][4] __devinitdata = {
  327. {4, 8, 16, -1},
  328. {9, 12, 18, -1},
  329. };
  330. /**
  331. * s1d13xxxfb_fetch_hw_state - Configure the framebuffer according to
  332. * hardware setup.
  333. * @info: frame buffer structure
  334. *
  335. * We setup the framebuffer structures according to the current
  336. * hardware setup. On some machines, the BIOS will have filled
  337. * the chip registers with such info, on others, these values will
  338. * have been written in some init procedure. In any case, the
  339. * software values needs to match the hardware ones. This is what
  340. * this function ensures.
  341. *
  342. * Note: some of the hardcoded values here might need some love to
  343. * work on various chips, and might need to no longer be hardcoded.
  344. */
  345. static void __devinit
  346. s1d13xxxfb_fetch_hw_state(struct fb_info *info)
  347. {
  348. struct fb_var_screeninfo *var = &info->var;
  349. struct fb_fix_screeninfo *fix = &info->fix;
  350. struct s1d13xxxfb_par *par = info->par;
  351. u8 panel, display;
  352. u16 offset;
  353. u32 xres, yres;
  354. u32 xres_virtual, yres_virtual;
  355. int bpp, lcd_bpp;
  356. int is_color, is_dual, is_tft;
  357. int lcd_enabled, crt_enabled;
  358. fix->type = FB_TYPE_PACKED_PIXELS;
  359. /* general info */
  360. par->display = s1d13xxxfb_readreg(par, S1DREG_COM_DISP_MODE);
  361. crt_enabled = (par->display & 0x02) != 0;
  362. lcd_enabled = (par->display & 0x01) != 0;
  363. if (lcd_enabled && crt_enabled)
  364. printk(KERN_WARNING PFX "Warning: LCD and CRT detected, using LCD\n");
  365. if (lcd_enabled)
  366. display = s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_MODE);
  367. else /* CRT */
  368. display = s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_MODE);
  369. bpp = display & 0x07;
  370. switch (bpp) {
  371. case 2: /* 4 bpp */
  372. case 3: /* 8 bpp */
  373. var->bits_per_pixel = 8;
  374. var->red.offset = var->green.offset = var->blue.offset = 0;
  375. var->red.length = var->green.length = var->blue.length = 8;
  376. break;
  377. case 5: /* 16 bpp */
  378. s1d13xxxfb_setup_truecolour(info);
  379. break;
  380. default:
  381. dbg("bpp: %i\n", bpp);
  382. }
  383. fb_alloc_cmap(&info->cmap, 256, 0);
  384. /* LCD info */
  385. panel = s1d13xxxfb_readreg(par, S1DREG_PANEL_TYPE);
  386. is_color = (panel & 0x04) != 0;
  387. is_dual = (panel & 0x02) != 0;
  388. is_tft = (panel & 0x01) != 0;
  389. lcd_bpp = s1d13xxxfb_width_tab[is_tft][(panel >> 4) & 3];
  390. if (lcd_enabled) {
  391. xres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_HWIDTH) + 1) * 8;
  392. yres = (s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT0) +
  393. ((s1d13xxxfb_readreg(par, S1DREG_LCD_DISP_VHEIGHT1) & 0x03) << 8) + 1);
  394. offset = (s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF0) +
  395. ((s1d13xxxfb_readreg(par, S1DREG_LCD_MEM_OFF1) & 0x7) << 8));
  396. } else { /* crt */
  397. xres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_HWIDTH) + 1) * 8;
  398. yres = (s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT0) +
  399. ((s1d13xxxfb_readreg(par, S1DREG_CRT_DISP_VHEIGHT1) & 0x03) << 8) + 1);
  400. offset = (s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF0) +
  401. ((s1d13xxxfb_readreg(par, S1DREG_CRT_MEM_OFF1) & 0x7) << 8));
  402. }
  403. xres_virtual = offset * 16 / var->bits_per_pixel;
  404. yres_virtual = fix->smem_len / (offset * 2);
  405. var->xres = xres;
  406. var->yres = yres;
  407. var->xres_virtual = xres_virtual;
  408. var->yres_virtual = yres_virtual;
  409. var->xoffset = var->yoffset = 0;
  410. fix->line_length = offset * 2;
  411. var->grayscale = !is_color;
  412. var->activate = FB_ACTIVATE_NOW;
  413. dbg(PFX "bpp=%d, lcd_bpp=%d, "
  414. "crt_enabled=%d, lcd_enabled=%d\n",
  415. var->bits_per_pixel, lcd_bpp, crt_enabled, lcd_enabled);
  416. dbg(PFX "xres=%d, yres=%d, vxres=%d, vyres=%d "
  417. "is_color=%d, is_dual=%d, is_tft=%d\n",
  418. xres, yres, xres_virtual, yres_virtual, is_color, is_dual, is_tft);
  419. }
  420. static int
  421. s1d13xxxfb_remove(struct platform_device *pdev)
  422. {
  423. struct fb_info *info = platform_get_drvdata(pdev);
  424. struct s1d13xxxfb_par *par = NULL;
  425. if (info) {
  426. par = info->par;
  427. if (par && par->regs) {
  428. /* disable output & enable powersave */
  429. s1d13xxxfb_writereg(par, S1DREG_COM_DISP_MODE, 0x00);
  430. s1d13xxxfb_writereg(par, S1DREG_PS_CNF, 0x11);
  431. iounmap(par->regs);
  432. }
  433. fb_dealloc_cmap(&info->cmap);
  434. if (info->screen_base)
  435. iounmap(info->screen_base);
  436. framebuffer_release(info);
  437. }
  438. release_mem_region(pdev->resource[0].start,
  439. pdev->resource[0].end - pdev->resource[0].start +1);
  440. release_mem_region(pdev->resource[1].start,
  441. pdev->resource[1].end - pdev->resource[1].start +1);
  442. return 0;
  443. }
  444. static int __devinit
  445. s1d13xxxfb_probe(struct platform_device *pdev)
  446. {
  447. struct s1d13xxxfb_par *default_par;
  448. struct fb_info *info;
  449. struct s1d13xxxfb_pdata *pdata = NULL;
  450. int ret = 0;
  451. u8 revision;
  452. dbg("probe called: device is %p\n", dev);
  453. printk(KERN_INFO "Epson S1D13XXX FB Driver\n");
  454. /* enable platform-dependent hardware glue, if any */
  455. if (pdev->dev.platform_data)
  456. pdata = pdev->dev.platform_data;
  457. if (pdata && pdata->platform_init_video)
  458. pdata->platform_init_video();
  459. if (pdev->num_resources != 2) {
  460. dev_err(&pdev->dev, "invalid num_resources: %i\n",
  461. pdev->num_resources);
  462. ret = -ENODEV;
  463. goto bail;
  464. }
  465. /* resource[0] is VRAM, resource[1] is registers */
  466. if (pdev->resource[0].flags != IORESOURCE_MEM
  467. || pdev->resource[1].flags != IORESOURCE_MEM) {
  468. dev_err(&pdev->dev, "invalid resource type\n");
  469. ret = -ENODEV;
  470. goto bail;
  471. }
  472. if (!request_mem_region(pdev->resource[0].start,
  473. pdev->resource[0].end - pdev->resource[0].start +1, "s1d13xxxfb mem")) {
  474. dev_dbg(&pdev->dev, "request_mem_region failed\n");
  475. ret = -EBUSY;
  476. goto bail;
  477. }
  478. if (!request_mem_region(pdev->resource[1].start,
  479. pdev->resource[1].end - pdev->resource[1].start +1, "s1d13xxxfb regs")) {
  480. dev_dbg(&pdev->dev, "request_mem_region failed\n");
  481. ret = -EBUSY;
  482. goto bail;
  483. }
  484. info = framebuffer_alloc(sizeof(struct s1d13xxxfb_par) + sizeof(u32) * 256, &pdev->dev);
  485. if (!info) {
  486. ret = -ENOMEM;
  487. goto bail;
  488. }
  489. platform_set_drvdata(pdev, info);
  490. default_par = info->par;
  491. default_par->regs = ioremap_nocache(pdev->resource[1].start,
  492. pdev->resource[1].end - pdev->resource[1].start +1);
  493. if (!default_par->regs) {
  494. printk(KERN_ERR PFX "unable to map registers\n");
  495. ret = -ENOMEM;
  496. goto bail;
  497. }
  498. info->pseudo_palette = default_par->pseudo_palette;
  499. info->screen_base = ioremap_nocache(pdev->resource[0].start,
  500. pdev->resource[0].end - pdev->resource[0].start +1);
  501. if (!info->screen_base) {
  502. printk(KERN_ERR PFX "unable to map framebuffer\n");
  503. ret = -ENOMEM;
  504. goto bail;
  505. }
  506. revision = s1d13xxxfb_readreg(default_par, S1DREG_REV_CODE);
  507. if ((revision >> 2) != S1D_CHIP_REV) {
  508. printk(KERN_INFO PFX "chip not found: %i\n", (revision >> 2));
  509. ret = -ENODEV;
  510. goto bail;
  511. }
  512. info->fix = s1d13xxxfb_fix;
  513. info->fix.mmio_start = pdev->resource[1].start;
  514. info->fix.mmio_len = pdev->resource[1].end - pdev->resource[1].start +1;
  515. info->fix.smem_start = pdev->resource[0].start;
  516. info->fix.smem_len = pdev->resource[0].end - pdev->resource[0].start +1;
  517. printk(KERN_INFO PFX "regs mapped at 0x%p, fb %d KiB mapped at 0x%p\n",
  518. default_par->regs, info->fix.smem_len / 1024, info->screen_base);
  519. info->par = default_par;
  520. info->fbops = &s1d13xxxfb_fbops;
  521. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  522. /* perform "manual" chip initialization, if needed */
  523. if (pdata && pdata->initregs)
  524. s1d13xxxfb_runinit(info->par, pdata->initregs, pdata->initregssize);
  525. s1d13xxxfb_fetch_hw_state(info);
  526. if (register_framebuffer(info) < 0) {
  527. ret = -EINVAL;
  528. goto bail;
  529. }
  530. printk(KERN_INFO "fb%d: %s frame buffer device\n",
  531. info->node, info->fix.id);
  532. return 0;
  533. bail:
  534. s1d13xxxfb_remove(pdev);
  535. return ret;
  536. }
  537. #ifdef CONFIG_PM
  538. static int s1d13xxxfb_suspend(struct platform_device *dev, pm_message_t state)
  539. {
  540. struct fb_info *info = platform_get_drvdata(dev);
  541. struct s1d13xxxfb_par *s1dfb = info->par;
  542. struct s1d13xxxfb_pdata *pdata = NULL;
  543. /* disable display */
  544. lcd_enable(s1dfb, 0);
  545. crt_enable(s1dfb, 0);
  546. if (dev->dev.platform_data)
  547. pdata = dev->dev.platform_data;
  548. #if 0
  549. if (!s1dfb->disp_save)
  550. s1dfb->disp_save = kmalloc(info->fix.smem_len, GFP_KERNEL);
  551. if (!s1dfb->disp_save) {
  552. printk(KERN_ERR PFX "no memory to save screen");
  553. return -ENOMEM;
  554. }
  555. memcpy_fromio(s1dfb->disp_save, info->screen_base, info->fix.smem_len);
  556. #else
  557. s1dfb->disp_save = NULL;
  558. #endif
  559. if (!s1dfb->regs_save)
  560. s1dfb->regs_save = kmalloc(info->fix.mmio_len, GFP_KERNEL);
  561. if (!s1dfb->regs_save) {
  562. printk(KERN_ERR PFX "no memory to save registers");
  563. return -ENOMEM;
  564. }
  565. /* backup all registers */
  566. memcpy_fromio(s1dfb->regs_save, s1dfb->regs, info->fix.mmio_len);
  567. /* now activate power save mode */
  568. s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x11);
  569. if (pdata && pdata->platform_suspend_video)
  570. return pdata->platform_suspend_video();
  571. else
  572. return 0;
  573. }
  574. static int s1d13xxxfb_resume(struct platform_device *dev)
  575. {
  576. struct fb_info *info = platform_get_drvdata(dev);
  577. struct s1d13xxxfb_par *s1dfb = info->par;
  578. struct s1d13xxxfb_pdata *pdata = NULL;
  579. /* awaken the chip */
  580. s1d13xxxfb_writereg(s1dfb, S1DREG_PS_CNF, 0x10);
  581. /* do not let go until SDRAM "wakes up" */
  582. while ((s1d13xxxfb_readreg(s1dfb, S1DREG_PS_STATUS) & 0x01))
  583. udelay(10);
  584. if (dev->dev.platform_data)
  585. pdata = dev->dev.platform_data;
  586. if (s1dfb->regs_save) {
  587. /* will write RO regs, *should* get away with it :) */
  588. memcpy_toio(s1dfb->regs, s1dfb->regs_save, info->fix.mmio_len);
  589. kfree(s1dfb->regs_save);
  590. }
  591. if (s1dfb->disp_save) {
  592. memcpy_toio(info->screen_base, s1dfb->disp_save,
  593. info->fix.smem_len);
  594. kfree(s1dfb->disp_save); /* XXX kmalloc()'d when? */
  595. }
  596. if ((s1dfb->display & 0x01) != 0)
  597. lcd_enable(s1dfb, 1);
  598. if ((s1dfb->display & 0x02) != 0)
  599. crt_enable(s1dfb, 1);
  600. if (pdata && pdata->platform_resume_video)
  601. return pdata->platform_resume_video();
  602. else
  603. return 0;
  604. }
  605. #endif /* CONFIG_PM */
  606. static struct platform_driver s1d13xxxfb_driver = {
  607. .probe = s1d13xxxfb_probe,
  608. .remove = s1d13xxxfb_remove,
  609. #ifdef CONFIG_PM
  610. .suspend = s1d13xxxfb_suspend,
  611. .resume = s1d13xxxfb_resume,
  612. #endif
  613. .driver = {
  614. .name = S1D_DEVICENAME,
  615. },
  616. };
  617. static int __init
  618. s1d13xxxfb_init(void)
  619. {
  620. if (fb_get_options("s1d13xxxfb", NULL))
  621. return -ENODEV;
  622. return platform_driver_register(&s1d13xxxfb_driver);
  623. }
  624. static void __exit
  625. s1d13xxxfb_exit(void)
  626. {
  627. platform_driver_unregister(&s1d13xxxfb_driver);
  628. }
  629. module_init(s1d13xxxfb_init);
  630. module_exit(s1d13xxxfb_exit);
  631. MODULE_LICENSE("GPL");
  632. MODULE_DESCRIPTION("Framebuffer driver for S1D13xxx devices");
  633. MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>, Thibaut VARENE <varenet@parisc-linux.org>");