pxafb.c 43 KB

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  1. /*
  2. * linux/drivers/video/pxafb.c
  3. *
  4. * Copyright (C) 1999 Eric A. Thomas.
  5. * Copyright (C) 2004 Jean-Frederic Clere.
  6. * Copyright (C) 2004 Ian Campbell.
  7. * Copyright (C) 2004 Jeff Lackey.
  8. * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
  9. * which in turn is
  10. * Based on acornfb.c Copyright (C) Russell King.
  11. *
  12. * This file is subject to the terms and conditions of the GNU General Public
  13. * License. See the file COPYING in the main directory of this archive for
  14. * more details.
  15. *
  16. * Intel PXA250/210 LCD Controller Frame Buffer Driver
  17. *
  18. * Please direct your questions and comments on this driver to the following
  19. * email address:
  20. *
  21. * linux-arm-kernel@lists.arm.linux.org.uk
  22. *
  23. */
  24. #include <linux/module.h>
  25. #include <linux/moduleparam.h>
  26. #include <linux/kernel.h>
  27. #include <linux/sched.h>
  28. #include <linux/errno.h>
  29. #include <linux/string.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/slab.h>
  32. #include <linux/fb.h>
  33. #include <linux/delay.h>
  34. #include <linux/init.h>
  35. #include <linux/ioport.h>
  36. #include <linux/cpufreq.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/dma-mapping.h>
  39. #include <asm/hardware.h>
  40. #include <asm/io.h>
  41. #include <asm/irq.h>
  42. #include <asm/uaccess.h>
  43. #include <asm/div64.h>
  44. #include <asm/arch/pxa-regs.h>
  45. #include <asm/arch/bitfield.h>
  46. #include <asm/arch/pxafb.h>
  47. /*
  48. * Complain if VAR is out of range.
  49. */
  50. #define DEBUG_VAR 1
  51. #include "pxafb.h"
  52. /* Bits which should not be set in machine configuration structures */
  53. #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
  54. #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
  55. static void (*pxafb_backlight_power)(int);
  56. static void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
  57. static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
  58. static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  59. #ifdef CONFIG_FB_PXA_PARAMETERS
  60. #define PXAFB_OPTIONS_SIZE 256
  61. static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
  62. #endif
  63. static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
  64. {
  65. unsigned long flags;
  66. local_irq_save(flags);
  67. /*
  68. * We need to handle two requests being made at the same time.
  69. * There are two important cases:
  70. * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
  71. * We must perform the unblanking, which will do our REENABLE for us.
  72. * 2. When we are blanking, but immediately unblank before we have
  73. * blanked. We do the "REENABLE" thing here as well, just to be sure.
  74. */
  75. if (fbi->task_state == C_ENABLE && state == C_REENABLE)
  76. state = (u_int) -1;
  77. if (fbi->task_state == C_DISABLE && state == C_ENABLE)
  78. state = C_REENABLE;
  79. if (state != (u_int)-1) {
  80. fbi->task_state = state;
  81. schedule_work(&fbi->task);
  82. }
  83. local_irq_restore(flags);
  84. }
  85. static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
  86. {
  87. chan &= 0xffff;
  88. chan >>= 16 - bf->length;
  89. return chan << bf->offset;
  90. }
  91. static int
  92. pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
  93. u_int trans, struct fb_info *info)
  94. {
  95. struct pxafb_info *fbi = (struct pxafb_info *)info;
  96. u_int val, ret = 1;
  97. if (regno < fbi->palette_size) {
  98. if (fbi->fb.var.grayscale) {
  99. val = ((blue >> 8) & 0x00ff);
  100. } else {
  101. val = ((red >> 0) & 0xf800);
  102. val |= ((green >> 5) & 0x07e0);
  103. val |= ((blue >> 11) & 0x001f);
  104. }
  105. fbi->palette_cpu[regno] = val;
  106. ret = 0;
  107. }
  108. return ret;
  109. }
  110. static int
  111. pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  112. u_int trans, struct fb_info *info)
  113. {
  114. struct pxafb_info *fbi = (struct pxafb_info *)info;
  115. unsigned int val;
  116. int ret = 1;
  117. /*
  118. * If inverse mode was selected, invert all the colours
  119. * rather than the register number. The register number
  120. * is what you poke into the framebuffer to produce the
  121. * colour you requested.
  122. */
  123. if (fbi->cmap_inverse) {
  124. red = 0xffff - red;
  125. green = 0xffff - green;
  126. blue = 0xffff - blue;
  127. }
  128. /*
  129. * If greyscale is true, then we convert the RGB value
  130. * to greyscale no matter what visual we are using.
  131. */
  132. if (fbi->fb.var.grayscale)
  133. red = green = blue = (19595 * red + 38470 * green +
  134. 7471 * blue) >> 16;
  135. switch (fbi->fb.fix.visual) {
  136. case FB_VISUAL_TRUECOLOR:
  137. /*
  138. * 16-bit True Colour. We encode the RGB value
  139. * according to the RGB bitfield information.
  140. */
  141. if (regno < 16) {
  142. u32 *pal = fbi->fb.pseudo_palette;
  143. val = chan_to_field(red, &fbi->fb.var.red);
  144. val |= chan_to_field(green, &fbi->fb.var.green);
  145. val |= chan_to_field(blue, &fbi->fb.var.blue);
  146. pal[regno] = val;
  147. ret = 0;
  148. }
  149. break;
  150. case FB_VISUAL_STATIC_PSEUDOCOLOR:
  151. case FB_VISUAL_PSEUDOCOLOR:
  152. ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
  153. break;
  154. }
  155. return ret;
  156. }
  157. /*
  158. * pxafb_bpp_to_lccr3():
  159. * Convert a bits per pixel value to the correct bit pattern for LCCR3
  160. */
  161. static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
  162. {
  163. int ret = 0;
  164. switch (var->bits_per_pixel) {
  165. case 1: ret = LCCR3_1BPP; break;
  166. case 2: ret = LCCR3_2BPP; break;
  167. case 4: ret = LCCR3_4BPP; break;
  168. case 8: ret = LCCR3_8BPP; break;
  169. case 16: ret = LCCR3_16BPP; break;
  170. }
  171. return ret;
  172. }
  173. #ifdef CONFIG_CPU_FREQ
  174. /*
  175. * pxafb_display_dma_period()
  176. * Calculate the minimum period (in picoseconds) between two DMA
  177. * requests for the LCD controller. If we hit this, it means we're
  178. * doing nothing but LCD DMA.
  179. */
  180. static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
  181. {
  182. /*
  183. * Period = pixclock * bits_per_byte * bytes_per_transfer
  184. * / memory_bits_per_pixel;
  185. */
  186. return var->pixclock * 8 * 16 / var->bits_per_pixel;
  187. }
  188. extern unsigned int get_clk_frequency_khz(int info);
  189. #endif
  190. /*
  191. * Select the smallest mode that allows the desired resolution to be
  192. * displayed. If desired parameters can be rounded up.
  193. */
  194. static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach, struct fb_var_screeninfo *var)
  195. {
  196. struct pxafb_mode_info *mode = NULL;
  197. struct pxafb_mode_info *modelist = mach->modes;
  198. unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
  199. unsigned int i;
  200. for (i = 0 ; i < mach->num_modes ; i++) {
  201. if (modelist[i].xres >= var->xres && modelist[i].yres >= var->yres &&
  202. modelist[i].xres < best_x && modelist[i].yres < best_y &&
  203. modelist[i].bpp >= var->bits_per_pixel ) {
  204. best_x = modelist[i].xres;
  205. best_y = modelist[i].yres;
  206. mode = &modelist[i];
  207. }
  208. }
  209. return mode;
  210. }
  211. static void pxafb_setmode(struct fb_var_screeninfo *var, struct pxafb_mode_info *mode)
  212. {
  213. var->xres = mode->xres;
  214. var->yres = mode->yres;
  215. var->bits_per_pixel = mode->bpp;
  216. var->pixclock = mode->pixclock;
  217. var->hsync_len = mode->hsync_len;
  218. var->left_margin = mode->left_margin;
  219. var->right_margin = mode->right_margin;
  220. var->vsync_len = mode->vsync_len;
  221. var->upper_margin = mode->upper_margin;
  222. var->lower_margin = mode->lower_margin;
  223. var->sync = mode->sync;
  224. var->grayscale = mode->cmap_greyscale;
  225. var->xres_virtual = var->xres;
  226. var->yres_virtual = var->yres;
  227. }
  228. /*
  229. * pxafb_check_var():
  230. * Get the video params out of 'var'. If a value doesn't fit, round it up,
  231. * if it's too big, return -EINVAL.
  232. *
  233. * Round up in the following order: bits_per_pixel, xres,
  234. * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
  235. * bitfields, horizontal timing, vertical timing.
  236. */
  237. static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  238. {
  239. struct pxafb_info *fbi = (struct pxafb_info *)info;
  240. struct pxafb_mach_info *inf = fbi->dev->platform_data;
  241. if (var->xres < MIN_XRES)
  242. var->xres = MIN_XRES;
  243. if (var->yres < MIN_YRES)
  244. var->yres = MIN_YRES;
  245. if (inf->fixed_modes) {
  246. struct pxafb_mode_info *mode;
  247. mode = pxafb_getmode(inf, var);
  248. if (!mode)
  249. return -EINVAL;
  250. pxafb_setmode(var, mode);
  251. } else {
  252. if (var->xres > inf->modes->xres)
  253. return -EINVAL;
  254. if (var->yres > inf->modes->yres)
  255. return -EINVAL;
  256. if (var->bits_per_pixel > inf->modes->bpp)
  257. return -EINVAL;
  258. }
  259. var->xres_virtual =
  260. max(var->xres_virtual, var->xres);
  261. var->yres_virtual =
  262. max(var->yres_virtual, var->yres);
  263. /*
  264. * Setup the RGB parameters for this display.
  265. *
  266. * The pixel packing format is described on page 7-11 of the
  267. * PXA2XX Developer's Manual.
  268. */
  269. if (var->bits_per_pixel == 16) {
  270. var->red.offset = 11; var->red.length = 5;
  271. var->green.offset = 5; var->green.length = 6;
  272. var->blue.offset = 0; var->blue.length = 5;
  273. var->transp.offset = var->transp.length = 0;
  274. } else {
  275. var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
  276. var->red.length = 8;
  277. var->green.length = 8;
  278. var->blue.length = 8;
  279. var->transp.length = 0;
  280. }
  281. #ifdef CONFIG_CPU_FREQ
  282. pr_debug("pxafb: dma period = %d ps, clock = %d kHz\n",
  283. pxafb_display_dma_period(var),
  284. get_clk_frequency_khz(0));
  285. #endif
  286. return 0;
  287. }
  288. static inline void pxafb_set_truecolor(u_int is_true_color)
  289. {
  290. pr_debug("pxafb: true_color = %d\n", is_true_color);
  291. // do your machine-specific setup if needed
  292. }
  293. /*
  294. * pxafb_set_par():
  295. * Set the user defined part of the display for the specified console
  296. */
  297. static int pxafb_set_par(struct fb_info *info)
  298. {
  299. struct pxafb_info *fbi = (struct pxafb_info *)info;
  300. struct fb_var_screeninfo *var = &info->var;
  301. unsigned long palette_mem_size;
  302. pr_debug("pxafb: set_par\n");
  303. if (var->bits_per_pixel == 16)
  304. fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
  305. else if (!fbi->cmap_static)
  306. fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
  307. else {
  308. /*
  309. * Some people have weird ideas about wanting static
  310. * pseudocolor maps. I suspect their user space
  311. * applications are broken.
  312. */
  313. fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
  314. }
  315. fbi->fb.fix.line_length = var->xres_virtual *
  316. var->bits_per_pixel / 8;
  317. if (var->bits_per_pixel == 16)
  318. fbi->palette_size = 0;
  319. else
  320. fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
  321. palette_mem_size = fbi->palette_size * sizeof(u16);
  322. pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
  323. fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
  324. fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
  325. /*
  326. * Set (any) board control register to handle new color depth
  327. */
  328. pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
  329. if (fbi->fb.var.bits_per_pixel == 16)
  330. fb_dealloc_cmap(&fbi->fb.cmap);
  331. else
  332. fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
  333. pxafb_activate_var(var, fbi);
  334. return 0;
  335. }
  336. /*
  337. * Formal definition of the VESA spec:
  338. * On
  339. * This refers to the state of the display when it is in full operation
  340. * Stand-By
  341. * This defines an optional operating state of minimal power reduction with
  342. * the shortest recovery time
  343. * Suspend
  344. * This refers to a level of power management in which substantial power
  345. * reduction is achieved by the display. The display can have a longer
  346. * recovery time from this state than from the Stand-by state
  347. * Off
  348. * This indicates that the display is consuming the lowest level of power
  349. * and is non-operational. Recovery from this state may optionally require
  350. * the user to manually power on the monitor
  351. *
  352. * Now, the fbdev driver adds an additional state, (blank), where they
  353. * turn off the video (maybe by colormap tricks), but don't mess with the
  354. * video itself: think of it semantically between on and Stand-By.
  355. *
  356. * So here's what we should do in our fbdev blank routine:
  357. *
  358. * VESA_NO_BLANKING (mode 0) Video on, front/back light on
  359. * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
  360. * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
  361. * VESA_POWERDOWN (mode 3) Video off, front/back light off
  362. *
  363. * This will match the matrox implementation.
  364. */
  365. /*
  366. * pxafb_blank():
  367. * Blank the display by setting all palette values to zero. Note, the
  368. * 16 bpp mode does not really use the palette, so this will not
  369. * blank the display in all modes.
  370. */
  371. static int pxafb_blank(int blank, struct fb_info *info)
  372. {
  373. struct pxafb_info *fbi = (struct pxafb_info *)info;
  374. int i;
  375. pr_debug("pxafb: blank=%d\n", blank);
  376. switch (blank) {
  377. case FB_BLANK_POWERDOWN:
  378. case FB_BLANK_VSYNC_SUSPEND:
  379. case FB_BLANK_HSYNC_SUSPEND:
  380. case FB_BLANK_NORMAL:
  381. if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
  382. fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
  383. for (i = 0; i < fbi->palette_size; i++)
  384. pxafb_setpalettereg(i, 0, 0, 0, 0, info);
  385. pxafb_schedule_work(fbi, C_DISABLE);
  386. //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
  387. break;
  388. case FB_BLANK_UNBLANK:
  389. //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
  390. if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
  391. fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
  392. fb_set_cmap(&fbi->fb.cmap, info);
  393. pxafb_schedule_work(fbi, C_ENABLE);
  394. }
  395. return 0;
  396. }
  397. static int pxafb_mmap(struct fb_info *info,
  398. struct vm_area_struct *vma)
  399. {
  400. struct pxafb_info *fbi = (struct pxafb_info *)info;
  401. unsigned long off = vma->vm_pgoff << PAGE_SHIFT;
  402. if (off < info->fix.smem_len) {
  403. vma->vm_pgoff += 1;
  404. return dma_mmap_writecombine(fbi->dev, vma, fbi->map_cpu,
  405. fbi->map_dma, fbi->map_size);
  406. }
  407. return -EINVAL;
  408. }
  409. static struct fb_ops pxafb_ops = {
  410. .owner = THIS_MODULE,
  411. .fb_check_var = pxafb_check_var,
  412. .fb_set_par = pxafb_set_par,
  413. .fb_setcolreg = pxafb_setcolreg,
  414. .fb_fillrect = cfb_fillrect,
  415. .fb_copyarea = cfb_copyarea,
  416. .fb_imageblit = cfb_imageblit,
  417. .fb_blank = pxafb_blank,
  418. .fb_mmap = pxafb_mmap,
  419. };
  420. /*
  421. * Calculate the PCD value from the clock rate (in picoseconds).
  422. * We take account of the PPCR clock setting.
  423. * From PXA Developer's Manual:
  424. *
  425. * PixelClock = LCLK
  426. * -------------
  427. * 2 ( PCD + 1 )
  428. *
  429. * PCD = LCLK
  430. * ------------- - 1
  431. * 2(PixelClock)
  432. *
  433. * Where:
  434. * LCLK = LCD/Memory Clock
  435. * PCD = LCCR3[7:0]
  436. *
  437. * PixelClock here is in Hz while the pixclock argument given is the
  438. * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
  439. *
  440. * The function get_lclk_frequency_10khz returns LCLK in units of
  441. * 10khz. Calling the result of this function lclk gives us the
  442. * following
  443. *
  444. * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
  445. * -------------------------------------- - 1
  446. * 2
  447. *
  448. * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
  449. */
  450. static inline unsigned int get_pcd(unsigned int pixclock)
  451. {
  452. unsigned long long pcd;
  453. /* FIXME: Need to take into account Double Pixel Clock mode
  454. * (DPC) bit? or perhaps set it based on the various clock
  455. * speeds */
  456. pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
  457. do_div(pcd, 100000000 * 2);
  458. /* no need for this, since we should subtract 1 anyway. they cancel */
  459. /* pcd += 1; */ /* make up for integer math truncations */
  460. return (unsigned int)pcd;
  461. }
  462. /*
  463. * Some touchscreens need hsync information from the video driver to
  464. * function correctly. We export it here.
  465. */
  466. static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
  467. {
  468. unsigned long long htime;
  469. if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
  470. fbi->hsync_time=0;
  471. return;
  472. }
  473. htime = (unsigned long long)get_lcdclk_frequency_10khz() * 10000;
  474. do_div(htime, pcd * fbi->fb.var.hsync_len);
  475. fbi->hsync_time = htime;
  476. }
  477. unsigned long pxafb_get_hsync_time(struct device *dev)
  478. {
  479. struct pxafb_info *fbi = dev_get_drvdata(dev);
  480. /* If display is blanked/suspended, hsync isn't active */
  481. if (!fbi || (fbi->state != C_ENABLE))
  482. return 0;
  483. return fbi->hsync_time;
  484. }
  485. EXPORT_SYMBOL(pxafb_get_hsync_time);
  486. /*
  487. * pxafb_activate_var():
  488. * Configures LCD Controller based on entries in var parameter. Settings are
  489. * only written to the controller if changes were made.
  490. */
  491. static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
  492. {
  493. struct pxafb_lcd_reg new_regs;
  494. u_long flags;
  495. u_int lines_per_panel, pcd = get_pcd(var->pixclock);
  496. pr_debug("pxafb: Configuring PXA LCD\n");
  497. pr_debug("var: xres=%d hslen=%d lm=%d rm=%d\n",
  498. var->xres, var->hsync_len,
  499. var->left_margin, var->right_margin);
  500. pr_debug("var: yres=%d vslen=%d um=%d bm=%d\n",
  501. var->yres, var->vsync_len,
  502. var->upper_margin, var->lower_margin);
  503. pr_debug("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
  504. #if DEBUG_VAR
  505. if (var->xres < 16 || var->xres > 1024)
  506. printk(KERN_ERR "%s: invalid xres %d\n",
  507. fbi->fb.fix.id, var->xres);
  508. switch(var->bits_per_pixel) {
  509. case 1:
  510. case 2:
  511. case 4:
  512. case 8:
  513. case 16:
  514. break;
  515. default:
  516. printk(KERN_ERR "%s: invalid bit depth %d\n",
  517. fbi->fb.fix.id, var->bits_per_pixel);
  518. break;
  519. }
  520. if (var->hsync_len < 1 || var->hsync_len > 64)
  521. printk(KERN_ERR "%s: invalid hsync_len %d\n",
  522. fbi->fb.fix.id, var->hsync_len);
  523. if (var->left_margin < 1 || var->left_margin > 255)
  524. printk(KERN_ERR "%s: invalid left_margin %d\n",
  525. fbi->fb.fix.id, var->left_margin);
  526. if (var->right_margin < 1 || var->right_margin > 255)
  527. printk(KERN_ERR "%s: invalid right_margin %d\n",
  528. fbi->fb.fix.id, var->right_margin);
  529. if (var->yres < 1 || var->yres > 1024)
  530. printk(KERN_ERR "%s: invalid yres %d\n",
  531. fbi->fb.fix.id, var->yres);
  532. if (var->vsync_len < 1 || var->vsync_len > 64)
  533. printk(KERN_ERR "%s: invalid vsync_len %d\n",
  534. fbi->fb.fix.id, var->vsync_len);
  535. if (var->upper_margin < 0 || var->upper_margin > 255)
  536. printk(KERN_ERR "%s: invalid upper_margin %d\n",
  537. fbi->fb.fix.id, var->upper_margin);
  538. if (var->lower_margin < 0 || var->lower_margin > 255)
  539. printk(KERN_ERR "%s: invalid lower_margin %d\n",
  540. fbi->fb.fix.id, var->lower_margin);
  541. #endif
  542. new_regs.lccr0 = fbi->lccr0 |
  543. (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
  544. LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
  545. new_regs.lccr1 =
  546. LCCR1_DisWdth(var->xres) +
  547. LCCR1_HorSnchWdth(var->hsync_len) +
  548. LCCR1_BegLnDel(var->left_margin) +
  549. LCCR1_EndLnDel(var->right_margin);
  550. /*
  551. * If we have a dual scan LCD, we need to halve
  552. * the YRES parameter.
  553. */
  554. lines_per_panel = var->yres;
  555. if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
  556. lines_per_panel /= 2;
  557. new_regs.lccr2 =
  558. LCCR2_DisHght(lines_per_panel) +
  559. LCCR2_VrtSnchWdth(var->vsync_len) +
  560. LCCR2_BegFrmDel(var->upper_margin) +
  561. LCCR2_EndFrmDel(var->lower_margin);
  562. new_regs.lccr3 = fbi->lccr3 |
  563. pxafb_bpp_to_lccr3(var) |
  564. (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
  565. (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
  566. if (pcd)
  567. new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
  568. pr_debug("nlccr0 = 0x%08x\n", new_regs.lccr0);
  569. pr_debug("nlccr1 = 0x%08x\n", new_regs.lccr1);
  570. pr_debug("nlccr2 = 0x%08x\n", new_regs.lccr2);
  571. pr_debug("nlccr3 = 0x%08x\n", new_regs.lccr3);
  572. /* Update shadow copy atomically */
  573. local_irq_save(flags);
  574. /* setup dma descriptors */
  575. fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
  576. fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
  577. fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
  578. fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
  579. fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
  580. fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
  581. #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
  582. /* populate descriptors */
  583. fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
  584. fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
  585. fbi->dmadesc_fblow_cpu->fidr = 0;
  586. fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
  587. fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
  588. fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
  589. fbi->dmadesc_fbhigh_cpu->fidr = 0;
  590. fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
  591. fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
  592. fbi->dmadesc_palette_cpu->fidr = 0;
  593. fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
  594. if (var->bits_per_pixel == 16) {
  595. /* palette shouldn't be loaded in true-color mode */
  596. fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
  597. fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
  598. /* init it to something, even though we won't be using it */
  599. fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
  600. } else {
  601. fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
  602. fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
  603. fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
  604. }
  605. #if 0
  606. pr_debug("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
  607. pr_debug("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
  608. pr_debug("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
  609. pr_debug("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
  610. pr_debug("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
  611. pr_debug("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
  612. pr_debug("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
  613. pr_debug("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
  614. pr_debug("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
  615. pr_debug("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
  616. pr_debug("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
  617. pr_debug("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
  618. pr_debug("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
  619. pr_debug("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
  620. pr_debug("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
  621. #endif
  622. fbi->reg_lccr0 = new_regs.lccr0;
  623. fbi->reg_lccr1 = new_regs.lccr1;
  624. fbi->reg_lccr2 = new_regs.lccr2;
  625. fbi->reg_lccr3 = new_regs.lccr3;
  626. set_hsync_time(fbi, pcd);
  627. local_irq_restore(flags);
  628. /*
  629. * Only update the registers if the controller is enabled
  630. * and something has changed.
  631. */
  632. if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
  633. (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
  634. (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
  635. pxafb_schedule_work(fbi, C_REENABLE);
  636. return 0;
  637. }
  638. /*
  639. * NOTE! The following functions are purely helpers for set_ctrlr_state.
  640. * Do not call them directly; set_ctrlr_state does the correct serialisation
  641. * to ensure that things happen in the right way 100% of time time.
  642. * -- rmk
  643. */
  644. static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
  645. {
  646. pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
  647. if (pxafb_backlight_power)
  648. pxafb_backlight_power(on);
  649. }
  650. static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
  651. {
  652. pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
  653. if (pxafb_lcd_power)
  654. pxafb_lcd_power(on, &fbi->fb.var);
  655. }
  656. static void pxafb_setup_gpio(struct pxafb_info *fbi)
  657. {
  658. int gpio, ldd_bits;
  659. unsigned int lccr0 = fbi->lccr0;
  660. /*
  661. * setup is based on type of panel supported
  662. */
  663. /* 4 bit interface */
  664. if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
  665. (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
  666. (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
  667. ldd_bits = 4;
  668. /* 8 bit interface */
  669. else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
  670. ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
  671. ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
  672. (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
  673. ldd_bits = 8;
  674. /* 16 bit interface */
  675. else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
  676. ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
  677. ldd_bits = 16;
  678. else {
  679. printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
  680. return;
  681. }
  682. for (gpio = 58; ldd_bits; gpio++, ldd_bits--)
  683. pxa_gpio_mode(gpio | GPIO_ALT_FN_2_OUT);
  684. pxa_gpio_mode(GPIO74_LCD_FCLK_MD);
  685. pxa_gpio_mode(GPIO75_LCD_LCLK_MD);
  686. pxa_gpio_mode(GPIO76_LCD_PCLK_MD);
  687. pxa_gpio_mode(GPIO77_LCD_ACBIAS_MD);
  688. }
  689. static void pxafb_enable_controller(struct pxafb_info *fbi)
  690. {
  691. pr_debug("pxafb: Enabling LCD controller\n");
  692. pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
  693. pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
  694. pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
  695. pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
  696. pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
  697. pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
  698. /* enable LCD controller clock */
  699. pxa_set_cken(CKEN16_LCD, 1);
  700. /* Sequence from 11.7.10 */
  701. LCCR3 = fbi->reg_lccr3;
  702. LCCR2 = fbi->reg_lccr2;
  703. LCCR1 = fbi->reg_lccr1;
  704. LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
  705. FDADR0 = fbi->fdadr0;
  706. FDADR1 = fbi->fdadr1;
  707. LCCR0 |= LCCR0_ENB;
  708. pr_debug("FDADR0 0x%08x\n", (unsigned int) FDADR0);
  709. pr_debug("FDADR1 0x%08x\n", (unsigned int) FDADR1);
  710. pr_debug("LCCR0 0x%08x\n", (unsigned int) LCCR0);
  711. pr_debug("LCCR1 0x%08x\n", (unsigned int) LCCR1);
  712. pr_debug("LCCR2 0x%08x\n", (unsigned int) LCCR2);
  713. pr_debug("LCCR3 0x%08x\n", (unsigned int) LCCR3);
  714. }
  715. static void pxafb_disable_controller(struct pxafb_info *fbi)
  716. {
  717. DECLARE_WAITQUEUE(wait, current);
  718. pr_debug("pxafb: disabling LCD controller\n");
  719. set_current_state(TASK_UNINTERRUPTIBLE);
  720. add_wait_queue(&fbi->ctrlr_wait, &wait);
  721. LCSR = 0xffffffff; /* Clear LCD Status Register */
  722. LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
  723. LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
  724. schedule_timeout(200 * HZ / 1000);
  725. remove_wait_queue(&fbi->ctrlr_wait, &wait);
  726. /* disable LCD controller clock */
  727. pxa_set_cken(CKEN16_LCD, 0);
  728. }
  729. /*
  730. * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
  731. */
  732. static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
  733. {
  734. struct pxafb_info *fbi = dev_id;
  735. unsigned int lcsr = LCSR;
  736. if (lcsr & LCSR_LDD) {
  737. LCCR0 |= LCCR0_LDM;
  738. wake_up(&fbi->ctrlr_wait);
  739. }
  740. LCSR = lcsr;
  741. return IRQ_HANDLED;
  742. }
  743. /*
  744. * This function must be called from task context only, since it will
  745. * sleep when disabling the LCD controller, or if we get two contending
  746. * processes trying to alter state.
  747. */
  748. static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
  749. {
  750. u_int old_state;
  751. down(&fbi->ctrlr_sem);
  752. old_state = fbi->state;
  753. /*
  754. * Hack around fbcon initialisation.
  755. */
  756. if (old_state == C_STARTUP && state == C_REENABLE)
  757. state = C_ENABLE;
  758. switch (state) {
  759. case C_DISABLE_CLKCHANGE:
  760. /*
  761. * Disable controller for clock change. If the
  762. * controller is already disabled, then do nothing.
  763. */
  764. if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
  765. fbi->state = state;
  766. //TODO __pxafb_lcd_power(fbi, 0);
  767. pxafb_disable_controller(fbi);
  768. }
  769. break;
  770. case C_DISABLE_PM:
  771. case C_DISABLE:
  772. /*
  773. * Disable controller
  774. */
  775. if (old_state != C_DISABLE) {
  776. fbi->state = state;
  777. __pxafb_backlight_power(fbi, 0);
  778. __pxafb_lcd_power(fbi, 0);
  779. if (old_state != C_DISABLE_CLKCHANGE)
  780. pxafb_disable_controller(fbi);
  781. }
  782. break;
  783. case C_ENABLE_CLKCHANGE:
  784. /*
  785. * Enable the controller after clock change. Only
  786. * do this if we were disabled for the clock change.
  787. */
  788. if (old_state == C_DISABLE_CLKCHANGE) {
  789. fbi->state = C_ENABLE;
  790. pxafb_enable_controller(fbi);
  791. //TODO __pxafb_lcd_power(fbi, 1);
  792. }
  793. break;
  794. case C_REENABLE:
  795. /*
  796. * Re-enable the controller only if it was already
  797. * enabled. This is so we reprogram the control
  798. * registers.
  799. */
  800. if (old_state == C_ENABLE) {
  801. __pxafb_lcd_power(fbi, 0);
  802. pxafb_disable_controller(fbi);
  803. pxafb_setup_gpio(fbi);
  804. pxafb_enable_controller(fbi);
  805. __pxafb_lcd_power(fbi, 1);
  806. }
  807. break;
  808. case C_ENABLE_PM:
  809. /*
  810. * Re-enable the controller after PM. This is not
  811. * perfect - think about the case where we were doing
  812. * a clock change, and we suspended half-way through.
  813. */
  814. if (old_state != C_DISABLE_PM)
  815. break;
  816. /* fall through */
  817. case C_ENABLE:
  818. /*
  819. * Power up the LCD screen, enable controller, and
  820. * turn on the backlight.
  821. */
  822. if (old_state != C_ENABLE) {
  823. fbi->state = C_ENABLE;
  824. pxafb_setup_gpio(fbi);
  825. pxafb_enable_controller(fbi);
  826. __pxafb_lcd_power(fbi, 1);
  827. __pxafb_backlight_power(fbi, 1);
  828. }
  829. break;
  830. }
  831. up(&fbi->ctrlr_sem);
  832. }
  833. /*
  834. * Our LCD controller task (which is called when we blank or unblank)
  835. * via keventd.
  836. */
  837. static void pxafb_task(struct work_struct *work)
  838. {
  839. struct pxafb_info *fbi =
  840. container_of(work, struct pxafb_info, task);
  841. u_int state = xchg(&fbi->task_state, -1);
  842. set_ctrlr_state(fbi, state);
  843. }
  844. #ifdef CONFIG_CPU_FREQ
  845. /*
  846. * CPU clock speed change handler. We need to adjust the LCD timing
  847. * parameters when the CPU clock is adjusted by the power management
  848. * subsystem.
  849. *
  850. * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
  851. */
  852. static int
  853. pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
  854. {
  855. struct pxafb_info *fbi = TO_INF(nb, freq_transition);
  856. //TODO struct cpufreq_freqs *f = data;
  857. u_int pcd;
  858. switch (val) {
  859. case CPUFREQ_PRECHANGE:
  860. set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
  861. break;
  862. case CPUFREQ_POSTCHANGE:
  863. pcd = get_pcd(fbi->fb.var.pixclock);
  864. set_hsync_time(fbi, pcd);
  865. fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
  866. set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
  867. break;
  868. }
  869. return 0;
  870. }
  871. static int
  872. pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
  873. {
  874. struct pxafb_info *fbi = TO_INF(nb, freq_policy);
  875. struct fb_var_screeninfo *var = &fbi->fb.var;
  876. struct cpufreq_policy *policy = data;
  877. switch (val) {
  878. case CPUFREQ_ADJUST:
  879. case CPUFREQ_INCOMPATIBLE:
  880. printk(KERN_DEBUG "min dma period: %d ps, "
  881. "new clock %d kHz\n", pxafb_display_dma_period(var),
  882. policy->max);
  883. // TODO: fill in min/max values
  884. break;
  885. #if 0
  886. case CPUFREQ_NOTIFY:
  887. printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
  888. do {} while(0);
  889. /* todo: panic if min/max values aren't fulfilled
  890. * [can't really happen unless there's a bug in the
  891. * CPU policy verification process *
  892. */
  893. break;
  894. #endif
  895. }
  896. return 0;
  897. }
  898. #endif
  899. #ifdef CONFIG_PM
  900. /*
  901. * Power management hooks. Note that we won't be called from IRQ context,
  902. * unlike the blank functions above, so we may sleep.
  903. */
  904. static int pxafb_suspend(struct platform_device *dev, pm_message_t state)
  905. {
  906. struct pxafb_info *fbi = platform_get_drvdata(dev);
  907. set_ctrlr_state(fbi, C_DISABLE_PM);
  908. return 0;
  909. }
  910. static int pxafb_resume(struct platform_device *dev)
  911. {
  912. struct pxafb_info *fbi = platform_get_drvdata(dev);
  913. set_ctrlr_state(fbi, C_ENABLE_PM);
  914. return 0;
  915. }
  916. #else
  917. #define pxafb_suspend NULL
  918. #define pxafb_resume NULL
  919. #endif
  920. /*
  921. * pxafb_map_video_memory():
  922. * Allocates the DRAM memory for the frame buffer. This buffer is
  923. * remapped into a non-cached, non-buffered, memory region to
  924. * allow palette and pixel writes to occur without flushing the
  925. * cache. Once this area is remapped, all virtual memory
  926. * access to the video memory should occur at the new region.
  927. */
  928. static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
  929. {
  930. u_long palette_mem_size;
  931. /*
  932. * We reserve one page for the palette, plus the size
  933. * of the framebuffer.
  934. */
  935. fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
  936. fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
  937. &fbi->map_dma, GFP_KERNEL);
  938. if (fbi->map_cpu) {
  939. /* prevent initial garbage on screen */
  940. memset(fbi->map_cpu, 0, fbi->map_size);
  941. fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
  942. fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
  943. /*
  944. * FIXME: this is actually the wrong thing to place in
  945. * smem_start. But fbdev suffers from the problem that
  946. * it needs an API which doesn't exist (in this case,
  947. * dma_writecombine_mmap)
  948. */
  949. fbi->fb.fix.smem_start = fbi->screen_dma;
  950. fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
  951. palette_mem_size = fbi->palette_size * sizeof(u16);
  952. pr_debug("pxafb: palette_mem_size = 0x%08lx\n", palette_mem_size);
  953. fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
  954. fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
  955. }
  956. return fbi->map_cpu ? 0 : -ENOMEM;
  957. }
  958. static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
  959. {
  960. struct pxafb_info *fbi;
  961. void *addr;
  962. struct pxafb_mach_info *inf = dev->platform_data;
  963. struct pxafb_mode_info *mode = inf->modes;
  964. int i, smemlen;
  965. /* Alloc the pxafb_info and pseudo_palette in one step */
  966. fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
  967. if (!fbi)
  968. return NULL;
  969. memset(fbi, 0, sizeof(struct pxafb_info));
  970. fbi->dev = dev;
  971. strcpy(fbi->fb.fix.id, PXA_NAME);
  972. fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
  973. fbi->fb.fix.type_aux = 0;
  974. fbi->fb.fix.xpanstep = 0;
  975. fbi->fb.fix.ypanstep = 0;
  976. fbi->fb.fix.ywrapstep = 0;
  977. fbi->fb.fix.accel = FB_ACCEL_NONE;
  978. fbi->fb.var.nonstd = 0;
  979. fbi->fb.var.activate = FB_ACTIVATE_NOW;
  980. fbi->fb.var.height = -1;
  981. fbi->fb.var.width = -1;
  982. fbi->fb.var.accel_flags = 0;
  983. fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
  984. fbi->fb.fbops = &pxafb_ops;
  985. fbi->fb.flags = FBINFO_DEFAULT;
  986. fbi->fb.node = -1;
  987. addr = fbi;
  988. addr = addr + sizeof(struct pxafb_info);
  989. fbi->fb.pseudo_palette = addr;
  990. pxafb_setmode(&fbi->fb.var, mode);
  991. fbi->cmap_inverse = inf->cmap_inverse;
  992. fbi->cmap_static = inf->cmap_static;
  993. fbi->lccr0 = inf->lccr0;
  994. fbi->lccr3 = inf->lccr3;
  995. fbi->state = C_STARTUP;
  996. fbi->task_state = (u_char)-1;
  997. for (i = 0; i < inf->num_modes; i++) {
  998. smemlen = mode[i].xres * mode[i].yres * mode[i].bpp / 8;
  999. if (smemlen > fbi->fb.fix.smem_len)
  1000. fbi->fb.fix.smem_len = smemlen;
  1001. }
  1002. init_waitqueue_head(&fbi->ctrlr_wait);
  1003. INIT_WORK(&fbi->task, pxafb_task);
  1004. init_MUTEX(&fbi->ctrlr_sem);
  1005. return fbi;
  1006. }
  1007. #ifdef CONFIG_FB_PXA_PARAMETERS
  1008. static int __init pxafb_parse_options(struct device *dev, char *options)
  1009. {
  1010. struct pxafb_mach_info *inf = dev->platform_data;
  1011. char *this_opt;
  1012. if (!options || !*options)
  1013. return 0;
  1014. dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
  1015. /* could be made table driven or similar?... */
  1016. while ((this_opt = strsep(&options, ",")) != NULL) {
  1017. if (!strncmp(this_opt, "mode:", 5)) {
  1018. const char *name = this_opt+5;
  1019. unsigned int namelen = strlen(name);
  1020. int res_specified = 0, bpp_specified = 0;
  1021. unsigned int xres = 0, yres = 0, bpp = 0;
  1022. int yres_specified = 0;
  1023. int i;
  1024. for (i = namelen-1; i >= 0; i--) {
  1025. switch (name[i]) {
  1026. case '-':
  1027. namelen = i;
  1028. if (!bpp_specified && !yres_specified) {
  1029. bpp = simple_strtoul(&name[i+1], NULL, 0);
  1030. bpp_specified = 1;
  1031. } else
  1032. goto done;
  1033. break;
  1034. case 'x':
  1035. if (!yres_specified) {
  1036. yres = simple_strtoul(&name[i+1], NULL, 0);
  1037. yres_specified = 1;
  1038. } else
  1039. goto done;
  1040. break;
  1041. case '0'...'9':
  1042. break;
  1043. default:
  1044. goto done;
  1045. }
  1046. }
  1047. if (i < 0 && yres_specified) {
  1048. xres = simple_strtoul(name, NULL, 0);
  1049. res_specified = 1;
  1050. }
  1051. done:
  1052. if (res_specified) {
  1053. dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
  1054. inf->modes[0].xres = xres; inf->modes[0].yres = yres;
  1055. }
  1056. if (bpp_specified)
  1057. switch (bpp) {
  1058. case 1:
  1059. case 2:
  1060. case 4:
  1061. case 8:
  1062. case 16:
  1063. inf->modes[0].bpp = bpp;
  1064. dev_info(dev, "overriding bit depth: %d\n", bpp);
  1065. break;
  1066. default:
  1067. dev_err(dev, "Depth %d is not valid\n", bpp);
  1068. }
  1069. } else if (!strncmp(this_opt, "pixclock:", 9)) {
  1070. inf->modes[0].pixclock = simple_strtoul(this_opt+9, NULL, 0);
  1071. dev_info(dev, "override pixclock: %ld\n", inf->modes[0].pixclock);
  1072. } else if (!strncmp(this_opt, "left:", 5)) {
  1073. inf->modes[0].left_margin = simple_strtoul(this_opt+5, NULL, 0);
  1074. dev_info(dev, "override left: %u\n", inf->modes[0].left_margin);
  1075. } else if (!strncmp(this_opt, "right:", 6)) {
  1076. inf->modes[0].right_margin = simple_strtoul(this_opt+6, NULL, 0);
  1077. dev_info(dev, "override right: %u\n", inf->modes[0].right_margin);
  1078. } else if (!strncmp(this_opt, "upper:", 6)) {
  1079. inf->modes[0].upper_margin = simple_strtoul(this_opt+6, NULL, 0);
  1080. dev_info(dev, "override upper: %u\n", inf->modes[0].upper_margin);
  1081. } else if (!strncmp(this_opt, "lower:", 6)) {
  1082. inf->modes[0].lower_margin = simple_strtoul(this_opt+6, NULL, 0);
  1083. dev_info(dev, "override lower: %u\n", inf->modes[0].lower_margin);
  1084. } else if (!strncmp(this_opt, "hsynclen:", 9)) {
  1085. inf->modes[0].hsync_len = simple_strtoul(this_opt+9, NULL, 0);
  1086. dev_info(dev, "override hsynclen: %u\n", inf->modes[0].hsync_len);
  1087. } else if (!strncmp(this_opt, "vsynclen:", 9)) {
  1088. inf->modes[0].vsync_len = simple_strtoul(this_opt+9, NULL, 0);
  1089. dev_info(dev, "override vsynclen: %u\n", inf->modes[0].vsync_len);
  1090. } else if (!strncmp(this_opt, "hsync:", 6)) {
  1091. if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
  1092. dev_info(dev, "override hsync: Active Low\n");
  1093. inf->modes[0].sync &= ~FB_SYNC_HOR_HIGH_ACT;
  1094. } else {
  1095. dev_info(dev, "override hsync: Active High\n");
  1096. inf->modes[0].sync |= FB_SYNC_HOR_HIGH_ACT;
  1097. }
  1098. } else if (!strncmp(this_opt, "vsync:", 6)) {
  1099. if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
  1100. dev_info(dev, "override vsync: Active Low\n");
  1101. inf->modes[0].sync &= ~FB_SYNC_VERT_HIGH_ACT;
  1102. } else {
  1103. dev_info(dev, "override vsync: Active High\n");
  1104. inf->modes[0].sync |= FB_SYNC_VERT_HIGH_ACT;
  1105. }
  1106. } else if (!strncmp(this_opt, "dpc:", 4)) {
  1107. if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
  1108. dev_info(dev, "override double pixel clock: false\n");
  1109. inf->lccr3 &= ~LCCR3_DPC;
  1110. } else {
  1111. dev_info(dev, "override double pixel clock: true\n");
  1112. inf->lccr3 |= LCCR3_DPC;
  1113. }
  1114. } else if (!strncmp(this_opt, "outputen:", 9)) {
  1115. if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
  1116. dev_info(dev, "override output enable: active low\n");
  1117. inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
  1118. } else {
  1119. dev_info(dev, "override output enable: active high\n");
  1120. inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
  1121. }
  1122. } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
  1123. if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
  1124. dev_info(dev, "override pixel clock polarity: falling edge\n");
  1125. inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
  1126. } else {
  1127. dev_info(dev, "override pixel clock polarity: rising edge\n");
  1128. inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
  1129. }
  1130. } else if (!strncmp(this_opt, "color", 5)) {
  1131. inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
  1132. } else if (!strncmp(this_opt, "mono", 4)) {
  1133. inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
  1134. } else if (!strncmp(this_opt, "active", 6)) {
  1135. inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
  1136. } else if (!strncmp(this_opt, "passive", 7)) {
  1137. inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
  1138. } else if (!strncmp(this_opt, "single", 6)) {
  1139. inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
  1140. } else if (!strncmp(this_opt, "dual", 4)) {
  1141. inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
  1142. } else if (!strncmp(this_opt, "4pix", 4)) {
  1143. inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
  1144. } else if (!strncmp(this_opt, "8pix", 4)) {
  1145. inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
  1146. } else {
  1147. dev_err(dev, "unknown option: %s\n", this_opt);
  1148. return -EINVAL;
  1149. }
  1150. }
  1151. return 0;
  1152. }
  1153. #endif
  1154. int __init pxafb_probe(struct platform_device *dev)
  1155. {
  1156. struct pxafb_info *fbi;
  1157. struct pxafb_mach_info *inf;
  1158. int ret;
  1159. dev_dbg(&dev->dev, "pxafb_probe\n");
  1160. inf = dev->dev.platform_data;
  1161. ret = -ENOMEM;
  1162. fbi = NULL;
  1163. if (!inf)
  1164. goto failed;
  1165. #ifdef CONFIG_FB_PXA_PARAMETERS
  1166. ret = pxafb_parse_options(&dev->dev, g_options);
  1167. if (ret < 0)
  1168. goto failed;
  1169. #endif
  1170. #ifdef DEBUG_VAR
  1171. /* Check for various illegal bit-combinations. Currently only
  1172. * a warning is given. */
  1173. if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
  1174. dev_warn(&dev->dev, "machine LCCR0 setting contains illegal bits: %08x\n",
  1175. inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
  1176. if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
  1177. dev_warn(&dev->dev, "machine LCCR3 setting contains illegal bits: %08x\n",
  1178. inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
  1179. if (inf->lccr0 & LCCR0_DPD &&
  1180. ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
  1181. (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
  1182. (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
  1183. dev_warn(&dev->dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
  1184. " single panel mode\n");
  1185. if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
  1186. (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
  1187. dev_warn(&dev->dev, "Dual panel only valid in passive mode\n");
  1188. if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
  1189. (inf->modes->upper_margin || inf->modes->lower_margin))
  1190. dev_warn(&dev->dev, "Upper and lower margins must be 0 in passive mode\n");
  1191. #endif
  1192. dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",inf->modes->xres, inf->modes->yres, inf->modes->bpp);
  1193. if (inf->modes->xres == 0 || inf->modes->yres == 0 || inf->modes->bpp == 0) {
  1194. dev_err(&dev->dev, "Invalid resolution or bit depth\n");
  1195. ret = -EINVAL;
  1196. goto failed;
  1197. }
  1198. pxafb_backlight_power = inf->pxafb_backlight_power;
  1199. pxafb_lcd_power = inf->pxafb_lcd_power;
  1200. fbi = pxafb_init_fbinfo(&dev->dev);
  1201. if (!fbi) {
  1202. dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
  1203. ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
  1204. goto failed;
  1205. }
  1206. /* Initialize video memory */
  1207. ret = pxafb_map_video_memory(fbi);
  1208. if (ret) {
  1209. dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
  1210. ret = -ENOMEM;
  1211. goto failed;
  1212. }
  1213. ret = request_irq(IRQ_LCD, pxafb_handle_irq, IRQF_DISABLED, "LCD", fbi);
  1214. if (ret) {
  1215. dev_err(&dev->dev, "request_irq failed: %d\n", ret);
  1216. ret = -EBUSY;
  1217. goto failed;
  1218. }
  1219. /*
  1220. * This makes sure that our colour bitfield
  1221. * descriptors are correctly initialised.
  1222. */
  1223. pxafb_check_var(&fbi->fb.var, &fbi->fb);
  1224. pxafb_set_par(&fbi->fb);
  1225. platform_set_drvdata(dev, fbi);
  1226. ret = register_framebuffer(&fbi->fb);
  1227. if (ret < 0) {
  1228. dev_err(&dev->dev, "Failed to register framebuffer device: %d\n", ret);
  1229. goto failed;
  1230. }
  1231. #ifdef CONFIG_PM
  1232. // TODO
  1233. #endif
  1234. #ifdef CONFIG_CPU_FREQ
  1235. fbi->freq_transition.notifier_call = pxafb_freq_transition;
  1236. fbi->freq_policy.notifier_call = pxafb_freq_policy;
  1237. cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
  1238. cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
  1239. #endif
  1240. /*
  1241. * Ok, now enable the LCD controller
  1242. */
  1243. set_ctrlr_state(fbi, C_ENABLE);
  1244. return 0;
  1245. failed:
  1246. platform_set_drvdata(dev, NULL);
  1247. kfree(fbi);
  1248. return ret;
  1249. }
  1250. static struct platform_driver pxafb_driver = {
  1251. .probe = pxafb_probe,
  1252. #ifdef CONFIG_PM
  1253. .suspend = pxafb_suspend,
  1254. .resume = pxafb_resume,
  1255. #endif
  1256. .driver = {
  1257. .name = "pxa2xx-fb",
  1258. },
  1259. };
  1260. #ifndef MODULE
  1261. int __devinit pxafb_setup(char *options)
  1262. {
  1263. # ifdef CONFIG_FB_PXA_PARAMETERS
  1264. if (options)
  1265. strlcpy(g_options, options, sizeof(g_options));
  1266. # endif
  1267. return 0;
  1268. }
  1269. #else
  1270. # ifdef CONFIG_FB_PXA_PARAMETERS
  1271. module_param_string(options, g_options, sizeof(g_options), 0);
  1272. MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
  1273. # endif
  1274. #endif
  1275. int __devinit pxafb_init(void)
  1276. {
  1277. #ifndef MODULE
  1278. char *option = NULL;
  1279. if (fb_get_options("pxafb", &option))
  1280. return -ENODEV;
  1281. pxafb_setup(option);
  1282. #endif
  1283. return platform_driver_register(&pxafb_driver);
  1284. }
  1285. module_init(pxafb_init);
  1286. MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
  1287. MODULE_LICENSE("GPL");